Samsung electronics co., ltd. (20240162193). SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract
Contents
- 1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.9.1 Unanswered Questions
- 1.9.2 How does this technology compare to existing semiconductor packaging methods in terms of performance and cost-effectiveness?
- 1.9.3 What are the specific materials used in the adhesion layers and how do they contribute to the overall performance of the semiconductor package?
- 1.10 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
UN-BYOUNG Kang of Suwon-si (KR)
SANG-SICK Park of Suwon-si (KR)
Seungyoon Jung of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240162193 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The semiconductor package described in the patent application consists of multiple semiconductor chips stacked on top of each other with adhesion layers in between. The lower adhesion layer has a cutting surface connected to its top surface, while the upper adhesion layer is in contact with this cutting surface.
- The semiconductor package includes a first semiconductor chip.
- There is a lower adhesion layer on the first semiconductor chip.
- A second semiconductor chip is placed on the lower adhesion layer.
- An upper adhesion layer is on the second semiconductor chip.
- A third semiconductor chip is on the upper adhesion layer.
Potential Applications
The technology described in this patent application could be used in various electronic devices such as smartphones, tablets, laptops, and other consumer electronics where compact and efficient semiconductor packaging is required.
Problems Solved
This technology solves the problem of efficiently stacking multiple semiconductor chips in a compact package while ensuring proper adhesion between the chips.
Benefits
The benefits of this technology include increased functionality in a smaller form factor, improved performance due to stacked semiconductor chips, and potentially reduced manufacturing costs.
Potential Commercial Applications
- "Innovative Semiconductor Package Design for Enhanced Performance and Compactness"
Possible Prior Art
There may be prior art related to semiconductor packaging techniques involving multiple stacked chips with adhesion layers, but specific examples are not provided in this patent application.
Unanswered Questions
How does this technology compare to existing semiconductor packaging methods in terms of performance and cost-effectiveness?
This article does not provide a direct comparison between this technology and existing semiconductor packaging methods.
What are the specific materials used in the adhesion layers and how do they contribute to the overall performance of the semiconductor package?
The patent application does not detail the specific materials used in the adhesion layers or their impact on the semiconductor package's performance.
Original Abstract Submitted
disclosed are semiconductor packages and their fabrication methods. the semiconductor package comprises a first semiconductor chip, a lower adhesion layer on the first semiconductor chip, a second semiconductor chip on the lower adhesion layer, an upper adhesion layer on the second semiconductor chip, and a third semiconductor chip on the upper adhesion layer. the lower adhesion layer includes a first cutting surface connected to a top surface of the lower adhesion layer. the upper adhesion layer is in contact with the first cutting surface of the lower adhesion layer.
