Samsung Electronics Co., Ltd. patent applications on January 9th, 2025
Patent Applications by Samsung Electronics Co., Ltd. on January 9th, 2025
Samsung Electronics Co., Ltd.: 182 patent applications
Samsung Electronics Co., Ltd. has applied for patents in the areas of H01L23/00 (22), H01L25/065 (14), H10B12/00 (14), H01L23/498 (11), H01L23/31 (11) H10B12/482 (5), H10B12/315 (4), H01L23/5283 (3), H01L25/0657 (3), H10B43/27 (3)
With keywords such as: device, layer, semiconductor, including, structure, based, surface, memory, channel, and portion in patent application abstracts.
Patent Applications by Samsung Electronics Co., Ltd.
Inventor(s): Sinae KIM of Suwon-si (KR) for samsung electronics co., ltd., Kihwan KWON of Suwon-si (KR) for samsung electronics co., ltd., Kiyong LEE of Suwon-si (KR) for samsung electronics co., ltd., Byunghun JUNG of Suwon-si (KR) for samsung electronics co., ltd., Yunwon JUNG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): A47L9/28
CPC Code(s): A47L9/2873
Abstract: a station configured to receive a used pad separated from a robot cleaner and supply a new pad to be coupled to the robot cleaner includes a station body, a pad replacement unit loaded with the used pad separated from the robot cleaner, a pad storage unit including a received pad container configured to store the used pad and a pad supply container configured to store the new pad, and a pad transfer unit arranged in the station body to reciprocate between the pad replacement unit and the pad storage unit, wherein the pad storage unit is configured to change positions of the received pad container and the pad supply container such that the received pad container and the pad supply container are located on a movement path of the pad transfer unit at different times.
Inventor(s): lndon JU of Suwon-si (KR) for samsung electronics co., ltd., Byunghwa LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): A61B5/11, A61B5/00, G16H20/30
CPC Code(s): A61B5/1121
Abstract: a wearable device may include a communication module configured to communicate with an electronic device worn on a body of a user, a driving module configured to generate a torque and provide the user with the generated torque, at least one inertial measurement unit (imu) configured to obtain motion information including at least one of acceleration information or rotation angle information of the user, and a processor(s). the processor(s) may to control the driving module to provide the torque to the user, receive sensing data obtained by the electronic device from the electronic device through the communication module, determine a coordinate value of a first point corresponding to a first part of the body using the received sensing data, receive the obtained motion information from the imu, determine respective coordinate values of a second point and a third point respectively corresponding to a second part and a third part of the body based on the received motion information, and determine a posture of the user based on the respective coordinate values of the first point, the second point, and the third point.
Inventor(s): Chiyoung AHN of Suwon-si (KR) for samsung electronics co., ltd., Donghee KANG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): A61H3/00, G16H20/30
CPC Code(s): A61H3/00
Abstract: a haptic feedback control method of controlling haptic feedback of a wearable device, a wearable device and/or an electronic device for performing the same are provided. a haptic feedback control method may include, when an exercise program is performed using the wearable device, receiving sensor data including motion information of a user from the wearable device, determining a threshold range with respect to haptic intensity of the haptic feedback based on at least one of user profile data of the user, exercise attribute data of the exercise program, and the sensor data, determining haptic intensity of haptic feedback to be provided to the user within the threshold range with respect to the determined haptic intensity, and when a haptic feedback provision event occurs, transmitting a control signal configured to control to provide the user with haptic feedback at the determined haptic intensity.
Inventor(s): Hyunjoo KANG of Suwon-si (KR) for samsung electronics co., ltd., Seungjoon LEE of Suwon-si (KR) for samsung electronics co., ltd., Heeyoung CHO of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): A63B21/00, A63B24/00
CPC Code(s): A63B21/00069
Abstract: a wearable device may obtain information for recognizing a disease of a user, recognize a disease of the user through the obtained information, determine an exercise mode of the wearable device based on the recognized disease, determine a first torque value based on a first angle value obtained by measuring an angle of a joint of the user in the determined exercise mode and values of parameters, generate a first torque corresponding to the determined first torque value and provide the first torque to the user, through a driving module of the wearable device, and when a start of a designated motion in the determined exercise mode is detected based on a second angle value obtained by measuring the angle of the joint, perform a control for generating a second torque so that the second torque generated by the driving module acts as a resistance to the designated motion.
Inventor(s): Jongin LEE of Suwon-si (KR) for samsung electronics co., ltd., Sehyun KIM of Suwon-si (KR) for samsung electronics co., ltd., Donguk KIM of Suwon-si (KR) for samsung electronics co., ltd., Jaeim PARK of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): A63F13/537, A63F13/22
CPC Code(s): A63F13/537
Abstract: a display apparatus including: a display; a communication interface; a memory configured to store at least one instruction; a processor configured to execute the at least one instruction stored in the memory to: receive, from an input device, an input instructing execution of a game launcher providing at least one game application, identify a type of the input device, transmit information about the type of the input device to a game server corresponding to the game launcher, receive, from the game server, information about the at least one game application that is controllable based on the type of the input device and configure a user interface screen provided by the game launcher based on the information about the at least one game application that is controllable based on the type of the input device, and display the user interface screen.
20250010243. WATER TREATMENT APPARATUS_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Youngkyu Cho of Suwon-si (KR) for samsung electronics co., ltd., Yumee Kim of Suwon-si (KR) for samsung electronics co., ltd., Hyoungkyun Kim of Suwon-si (KR) for samsung electronics co., ltd., Heejin Park of Suwon-si (KR) for samsung electronics co., ltd., Changhoon Oh of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): B01D61/42, C02F1/469
CPC Code(s): B01D61/4281
Abstract: a water treatment apparatus includes a first ion removal module including a first cation exchange membrane, a first anion exchange membrane, and a first deionization channel therebetween; a second ion removal module including a second cation exchange membrane, a second anion exchange membrane, and a second deionization channel therebetween; and a fluid separation device to separate a fluid, discharged from the first deionization channel, and to guide the fluid. the fluid separation device includes an outer guide to guide a portion of the fluid discharged from the first deionization channel to an outside of the second deionization channel, and a center guide to guide another portion of the fluid from the first deionization channel to the second deionization channel, and the center guide arranged inside of the outer guide.
Inventor(s): Dongsik Yang of Seoul (KR) for samsung electronics co., ltd., Hyukjae Kwon of Suwon-si (KR) for samsung electronics co., ltd., Minseok Koo of Suwon-si (KR) for samsung electronics co., ltd., Sukeun Kuk of Suwon-si (KR) for samsung electronics co., ltd., Sehyeong Oh of Seoul (KR) for samsung electronics co., ltd., Hyun Chul Lee of Hwaseong-si (KR) for samsung electronics co., ltd., Sangmin Ji of Yongin-si (KR) for samsung electronics co., ltd.
IPC Code(s): B01J7/00, C23C16/448, H01L21/67
CPC Code(s): B01J7/00
Abstract: a process apparatus includes a gas supplier which supplies a reaction gas having a constant concentration, and a processor which performs a predetermined process by the reaction gas supplied from the gas supplier, where the gas supplier includes a reactor which accommodates a solid phase reactant, a heater which applies heat to the solid phase reactant to convert the solid phase reactant to a reaction gas in a gas phase, a gas pump which applies a predetermined pumping pressure to the reactor, and a gas outlet which discharges the reaction gas to the processor.
Inventor(s): Changbae LIM of Suwon-si (KR) for samsung electronics co., ltd., Sungwon KIM of Suwon-si (KR) for samsung electronics co., ltd., Heejin PARK of Suwon-si (KR) for samsung electronics co., ltd., Sungpil HONG of Suwon-si (KR) for samsung electronics co., ltd., Yumee KIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): C02F1/46, C02F1/461, C02F1/469
CPC Code(s): C02F1/4602
Abstract: provided is a water treatment apparatus, including a first channel including a first current collector and an anion exchange membrane, a second channel including a second current collector and a cation exchange membrane, a third channel including the anion exchange membrane and the cation exchange membrane, and at least one processor configured to during a deionization operation, apply a negative voltage to the second current collector to move cations contained in water in the third channel to the second channel, during a regeneration operation, apply a first positive voltage to the second current collector to move cations in the second channel to the third channel, and during a descaling operation, apply a second positive voltage greater than the first positive voltage to the second current collector to electrolyze water in the second channel.
Inventor(s): Wonji JUNG of Suwon-si (KR) for samsung electronics co., ltd., Sungwon KIM of Suwon-si (KR) for samsung electronics co., ltd., Jeeyeon KIM of Suwon-si (KR) for samsung electronics co., ltd., Heejin PARK of Suwon-si (KR) for samsung electronics co., ltd., Sungpil HONG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): C02F1/469, C02F1/461
CPC Code(s): C02F1/4691
Abstract: disclosed is an electrode for a capacitive deionization apparatus including a current collector and an active material layer disposed on one side of the current collector, wherein the active material layer includes: a plurality of pore structures, each of the plurality of pore structures including a plurality of carbon nanotubes; and a binder fixing the plurality of pore structures to the current collector, and the each of the plurality of pore structure includes a wide bottom-narrow top structure widening in a direction away from the current collector.
Inventor(s): Hyune Jea LEE of Suwon-si (KR) for samsung electronics co., ltd., Sang Soo JEE of Suwon-si (KR) for samsung electronics co., ltd., Kee Chang LEE of Suwon-si (KR) for samsung electronics co., ltd., Jung Hoon LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): C09G1/02, H01L21/321
CPC Code(s): C09G1/02
Abstract: a polishing slurry and a method of manufacturing a semiconductor device using the polishing slurry. the polishing slurry includes plate-shaped particles having a mohs hardness of less than or equal to about 5, and a spherical abrasive. the plate-shaped particles have a thermal conductivity in a dimensional direction of greater than or equal to about 10 w/mk, and the plate-shaped particles have a larger average particle size than the spherical abrasive. also, the plate-shaped particles and the spherical abrasive are not chemically bonded to the other.
Inventor(s): Kyungsang CHO of Gwacheon-si (KR) for samsung electronics co., ltd., Sohee JEONG of Seoul (KR) for samsung electronics co., ltd., Taewan KIM of Suwon-si (KR) for samsung electronics co., ltd., Yooseong YANG of Yongin-si (KR) for samsung electronics co., ltd., Seongmin PARK of Gwangju (KR) for samsung electronics co., ltd.
IPC Code(s): C09K11/74, B82Y20/00, B82Y40/00, C01G28/00, C09K11/88
CPC Code(s): C09K11/7492
Abstract: according to an aspect, a method of preparing quantum dots includes a first operation of preparing a quantum dot seed solution; a second operation of growing a quantum dot by continuously injecting a quantum dot cluster solution into the quantum dot seed solution; a third operation of separating the grown quantum dot and dispersing the quantum dot in a solvent; and a fourth operation of further growing the quantum dot by continuously injecting the quantum dot cluster solution into the dispersed quantum dot.
Inventor(s): Cheol HAM of Suwon-si (KR) for samsung electronics co., ltd., Byungjoon KANG of Suwon-si (KR) for samsung electronics co., ltd., Sangwan KIM of Hwaseong-si (KR) for samsung electronics co., ltd., Sungmin KIM of Suwon-si (KR) for samsung electronics co., ltd., Insun PARK of Suwon-si (KR) for samsung electronics co., ltd., Gayoung SONG of Hwaseong-si (KR) for samsung electronics co., ltd., Jungmin OH of Hwaseong-si (KR) for samsung electronics co., ltd., Kyuyoung HWANG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): C09K13/06, H01L21/3213
CPC Code(s): C09K13/06
Abstract: provided are an etching composition, a method of etching a metal-containing film using the same, and a method of manufacturing a semiconductor device by using the same. the etching composition includes an oxidizing agent, an acid, and a selective etching inhibitor, wherein the oxidizing agent is metal-free, the selective etching inhibitor includes a copolymer including a first repeating unit and a second repeating unit, the first repeating unit is different from the second repeating unit, and the first repeating unit is a nitrogen-containing repeating unit.
Inventor(s): Junho Lee of Suwon-si (KR) for samsung electronics co., ltd., Yeontae Kim of Suwon-si (KR) for samsung electronics co., ltd., Yihwan Kim of Suwon-si (KR) for samsung electronics co., ltd., Youngbok Lee of Suwon-si (KR) for samsung electronics co., ltd., Sangchul Han of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): C23C16/455
CPC Code(s): C23C16/45565
Abstract: a showerhead includes a showerhead body positioned at an upper surface of a reaction chamber and configured to inject a reaction gas toward a substrate in the reaction chamber and at least one groove in a lower surface of the showerhead body, where the showerhead body is oriented toward the substrate and the lower surface of the showerhead body includes a slanted structure.
Inventor(s): Taein EOM of Suwon-si (KR) for samsung electronics co., ltd., Daesung KI of Suwon-si (KR) for samsung electronics co., ltd., Chanyoung PARK of Suwon-si (KR) for samsung electronics co., ltd., Hyunuk PARK of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): E05F15/614, F25D23/02
CPC Code(s): E05F15/614
Abstract: a refrigerator and a control method thereof. the refrigerator includes a housing, a door configured to be rotatably coupled to the housing by including a hinge shaft and a hinge gear fixed to the hinge shaft, and a door opening and closing device provided at one end of the door to control opening and closing of the door. the door opening and closing device includes a drive motor, a final gear configured to receive power from the drive motor and transmit the power to the hinge shaft, the final gear arranged at one end of the door opening and closing device to interlock with the hinge gear, and a door position sensor arranged on one side of the final gear to detect a rotation angle of the final gear.
20250012398. VACUUM INSULATION PANEL_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Sunghwan HONG of Suwon-si (KR) for samsung electronics co., ltd., Jungsoo Lim of Suwon-si (KR) for samsung electronics co., ltd., Yeonkyoung Jung of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): F16L59/065
CPC Code(s): F16L59/065
Abstract: provided is a vacuum insulation panel including a core material and a covering material on an outer side of the core material. the covering material forms an internal space in which the core material is accommodated, wherein the core material includes a first plate in the internal space and having a first thickness. the core material includes a second plate in the internal space, spaced from the first plate, and has the first thickness. the core material includes one supporting member between the first plate and the second plate and having a second thickness that is greater than the first thickness, wherein each of a surface of the first plate that is perpendicular to a thickness direction of the core material and a surface of the second plate that is perpendicular to the thickness direction has a first area.
Inventor(s): Junwoo SUH of Suwon-si (KR) for samsung electronics co., ltd., Minsoo KIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): F25B21/00
CPC Code(s): F25B21/00
Abstract: a cooling cycle apparatus including: a first heat exchanger configured to emit heat and a second heat exchanger configured to absorb heat; a magnetic cooling device comprising a magnetocaloric material and configured to heat a first fluid flowing into the first heat exchanger and cool a second fluid flowing into the second heat exchanger; and an auxiliary cooling device comprising a heater configured to further heat the first fluid flowing into the first heat exchanger, and a cooler configured to further cool the second fluid flowing to the second heat exchanger.
20250012556. SEMICONDUCTOR MEASUREMENT APPARATUS_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Younguk Jin of Suwon-si (KR) for samsung electronics co., ltd., Wookrae Kim of Suwon-si (KR) for samsung electronics co., ltd., Jinseob Kim of Suwon-si (KR) for samsung electronics co., ltd., Jinyong Kim of Suwon-si (KR) for samsung electronics co., ltd., Garam Choi of Suwon-si (KR) for samsung electronics co., ltd., Daehoon Han of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G01B9/02, G01B9/02001, G01B9/02056
CPC Code(s): G01B9/02044
Abstract: a semiconductor measurement apparatus includes lighting unit; a light receiving unit; and a control unit configured to: generate a prediction equation representing the original image, where the prediction equation is based on a plurality of elements of a mueller matrix, approximate each of the plurality of elements of the mueller matrix to a polynomial including bases of a zernike polynomial and coefficients, generate optimization coefficients based on a sum of the coefficients and a difference between the prediction equation and the original image, determine whether an optimization condition is satisfied based on the optimization coefficients and a minimum value, and select a dimension based on the optimization coefficients and the bases when the optimization condition is satisfied.
Inventor(s): Dohun Kim of Suwon-si (KR) for samsung electronics co., ltd., Mincheol Kwak of Suwon-si (KR) for samsung electronics co., ltd., Junseong Yoon of Suwon-si (KR) for samsung electronics co., ltd., Jeongjin Lee of Suwon-si (KR) for samsung electronics co., ltd., Seungyoon Lee of Suwon-si (KR) for samsung electronics co., ltd., Chan Hwang of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G01N21/956, G01N21/95, G06T7/00
CPC Code(s): G01N21/956
Abstract: a method of optimizing an overlay measurement condition includes measuring, for each overlay measurement condition of multiple overlay measurement conditions, an overlay at multiple positions on a substrate; calculating, for each of the multiple overlay measurement conditions, key parameter indexes (kpis) based on the measured overlay; converting, for each of the multiple overlay measurement conditions, the kpis into key parameter function (kpf) values based on a kpf, where each of the kpfs has a same dimensional representation; integrating, for each of the multiple overlay measurement conditions, the kpf values to generate an integrated kpf value; and selecting an optimized overlay measurement condition from among the multiple overlay measurement conditions based on the integrated kpf values associated with each of the multiple overlay measurement conditions.
Inventor(s): Jihyun CHOI of Suwon-si (KR) for samsung electronics co., ltd., Seonmi LEE of Suwon-si (KR) for samsung electronics co., ltd., Yonggyun KIM of Suwon-si (KR) for samsung electronics co., ltd., Seongseob SHIN of Suwon-si (KR) for samsung electronics co., ltd., Dahm YU of Suwon-si (KR) for samsung electronics co., ltd., Dongho LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G01R31/28
CPC Code(s): G01R31/2875
Abstract: a test device includes a test board, a connector attached to a lower surface of the test board, a heating device disposed on an upper surface of the test board, the heating device configured to emit heat in response to a signal input through the connector, a temperature sensor disposed on the upper surface of the test board, the temperature sensor configured to measure a temperature of the heating device, and a test socket disposed on the upper surface of the test board, the test socket configured to transmit and receive a signal to and from the heating device and the temperature sensor. before a test process is performed or after the test process is completed, an internal temperature of a chamber may be verified, thereby improving reliability of the test process.
Inventor(s): Dawoon JUNG of Suwon-si (KR) for samsung electronics co., ltd., Hyejin KANG of Suwon-si (KR) for samsung electronics co., ltd., Heesu KIM of Suwon-si (KR) for samsung electronics co., ltd., Jihye CHOI of Suwon-si (KR) for samsung electronics co., ltd., Kwanghoon HAN of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G01S13/76, G08B3/10, G08B5/22
CPC Code(s): G01S13/767
Abstract: a method and a device for ultra wideband (uwb) communication are provided. the electronic device includes a communication circuitry, memory storing one or more computer programs, and one or more processors communicatively coupled to the communication circuitry and the memory, wherein the one instructions, when executed by the one or more processors individually or collectively, cause the electronic device to control the communication circuitry to broadcast a ranging request message including an address selected from among a plurality of addresses configured in a specified broadcast address pool, by using short-range wireless communication, and receive a ranging response message from at least one external electronic device to which the selected address is allocated by using the designated broadcast address pool, wherein the address allocated to the at least one external electronic device corresponds to the address included in the ranging request message.
Inventor(s): Haneung KIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G02B13/00, G02B5/00, G02B9/62, H04N23/55
CPC Code(s): G02B13/0045
Abstract: provided is an electronic device including a lens assembly that includes a plurality of lenses aligned along an optical axis from an object side of the lens assembly to an image side of the lens assembly, the plurality of lenses including a first lens having positive refractive power, a second lens, a third lens, a fourth lens having negative refractive power and an image side of the fourth lens being concave, a fifth lens, and a sixth lens having positive refractive power, and an image sensor comprising an imaging plane on which an image is formed, and wherein an air gap between the fourth lens and the fifth lens is larger than an air gap between other two adjacent lenses.
Inventor(s): Taeyeon KIM of Suwon-si (KR) for samsung electronics co., ltd., Sungyeol KIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G02F1/13357
CPC Code(s): G02F1/133608
Abstract: a light source apparatus includes an optical member, a substrate on a rear side of the optical member, a light source mounted on the substrate and configured to emit light, and a supporter between the optical member and the substrate and including a support body at one end of the supporter facing the substrate and mounted on the substrate, and an adsorption portion at another end of the supporter facing the optical member and configured to form an adsorption space having a pressure less than the pressure outside the supporter in a state in which the supporter supports the optical member.
Inventor(s): Hyungsuk KIM of Suwon-si (KR) for samsung electronics co., ltd., Sungyeol Kim of Suwon-si (KR) for samsung electronics co., ltd., Chunsoon Park of Suwon-si (KR) for samsung electronics co., ltd., Taeyeon Kim of Suwon-si (KR) for samsung electronics co., ltd., Junsung Choi of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G02F1/1335, G02F1/13357
CPC Code(s): G02F1/133612
Abstract: a light source device includes: a reflective sheet including a hole formed therein; and a light source module including a portion inserted into the hole, a substrate including a first layer including a feeding line, and a second layer laminated in an upper portion of the first layer, a light-emitting diode on the second layer, a feeding pad, connected to the feeding line, in a window formed in the second layer and configured to contact the light-emitting diode, an insulating dome on the second layer, and an antistatic pad on the second layer and including a silver plating layer, a first antistatic pad within a region defined by the hole, and a second antistatic pad outside of the region defined by the hole and extending in the longitudinal direction of the feeding line spaced a first length therefrom in the width direction of the feeding line.
Inventor(s): Yunhan LEE of Suwon-si (KR) for samsung electronics co., ltd., Goonmo KOO of Suwon-si (KR) for samsung electronics co., ltd., Mun Ja KIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G03F1/64, G03F1/66
CPC Code(s): G03F1/64
Abstract: a pellicle assembly may include a pellicle frame configured to provide a first opening, a pellicle on the pellicle frame, and a plurality of pellicle electrodes arranged along an edge of the pellicle and spaced apart from each other. the pellicle may include a pellicle border having a shape of a tetragonal or rectangular frame, and a pellicle membrane placed on and coupled to a top surface of the pellicle border. each of the pellicle electrodes may include a contact member placed on and in contact with a top surface of the pellicle membrane.
Inventor(s): Yangsoo CHOI of Suwon-si (KR) for samsung electronics co., ltd., Sukdong KIM of Suwon-si (KR) for samsung electronics co., ltd., Jihea PARK of Suwon-si (KR) for samsung electronics co., ltd., Junghyeob LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G05B15/02, G06F1/16, G09G3/00
CPC Code(s): G05B15/02
Abstract: an electronic device having a first housing, a second housing movable with respect to the first housing, a flexible display mounted on the second housing that is configured to be inserted into or ejected from the first housing. the electronic device also includes a motor driving unit for moving the second housing, a memory for storing executable instructions, and at least one processor accessing the memory to execute the instructions. the processor outputs a control signal to the motor driving unit upon receiving a first signal, compares a measurement value related to the movement of the motor driving unit with a preset reference value, determines whether calibration of the motor driving unit is necessary based on the comparison, and provides a user notification if calibration is needed.
Inventor(s): Seongmin KANG of Suwon-si (KR) for samsung electronics co., ltd., Heungwoo Han of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G05D1/229, G01S17/89, G05D1/224, G05D1/24, G06V10/764
CPC Code(s): G05D1/2295
Abstract: an electronic apparatus includes a first sensor, a second sensor, at least one memory storing at least one instruction, and at least one processor operably connected with the first sensor, the second sensor, and the at least one memory, wherein the at least one processor, executing the at least one instruction, configured to acquire sensing data through the first sensor, identify a plurality of driving locations based on the sensing data, acquire a plurality of photographed images through the second sensor, store the plurality of driving locations and the plurality of photographed images in the at least one memory, and based on identifying an event preventing driving, identify a first time point corresponding to the event preventing driving, identify a second time point preceding the first time point by a threshold time, identify a driving location, among the plurality of driving locations, corresponding to the second time point, identify a photographed image, among the plurality of photographed images, corresponding to the second time point, and register the event preventing driving based on event information, and wherein the event information may include the driving location corresponding to the second time point and the photographed image corresponding to the second time point.
Inventor(s): Seongyu HWANG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06F1/16
CPC Code(s): G06F1/1681
Abstract: an electronic device is provided. the electronic device includes a first housing and a second housing, wherein the first housing includes a rear plate including at least one first opening, a support bracket disposed adjacent to the rear plate to support the rear plate, and at least one rubber member disposed to penetrate the first opening of the rear plate, and wherein the support bracket includes a fastening part disposed adjacent to the rubber member, at least one fixing part extending from one side of the fastening part, a supporting part extending from the at least one fixing part and at least partially disposed to face the rear plate, and at least one rotating part connected with the supporting part and coupled to be rotatable about the supporting part.
Inventor(s): Soobin CHOI of Suwon-si (KR) for samsung electronics co., ltd., Junho KIM of Suwon-si (KR) for samsung electronics co., ltd., Yeop HWANGBO of Suwon-si (KR) for samsung electronics co., ltd., Yonggil HAN of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06F3/0484, G06F12/02
CPC Code(s): G06F3/0484
Abstract: a processor according to an embodiment is configured to display a first visual object of visual objects arranged according to an order of variance of sizes of the groups corresponding to a plurality of files, in an area of a first screen for managing memory. the visual objects respectively correspond to the groups of the plurality of files stored in the memory. the processor is configured to, based on an input of the first visual object, display a second screen including a list of first files corresponding to a specified condition of a first group corresponding to the first visual object and a visual element for removal of the first files.
Inventor(s): BYOUNGKON JO of Suwon si (KR) for samsung electronics co., ltd., Minwoo LEE of Suwon si (KR) for samsung electronics co., ltd., Joonho JUN of Suwon si (KR) for samsung electronics co., ltd., Duk Sung KIM of Suwon si (KR) for samsung electronics co., ltd., Doohee HWANG of Suwon si (KR) for samsung electronics co., ltd.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0608
Abstract: there is provided a memory device including a content addressable memory physical layer connected to external data pads. during the write operation, the content addressable memory physical layer transmits a selected data pattern from among data patterns stored in a content addressable memory cell array as input data to selected memory cells of a memory cell array corresponding to an address received from external device based on first data received from the external data pads. during the read operation, the content addressable memory physical layer compares output data read from the memory cell array with the data patterns based on an address received from external device, and outputs content addressable memory address corresponding to data pattern matched by a result of the comparing as second data through the external data pads.
Inventor(s): Heesung KIM of Suwon-si (KR) for samsung electronics co., ltd., Hyunwook SHIN of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: a storage device includes a first non-volatile memory device storing a data; a first selector connected to the first non-volatile memory device; a plurality of channels connected to the first selector; and a memory controller connected to the plurality of channels, transmitting a command for sensing a state of a channel to the plurality of channels in order to transmit the data to the first non-volatile memory device, receiving a channel state signal indicating whether each channel is in an idle state or not from the plurality of channels as a response to the command, selecting a first channel among the plurality of channels based on the channel state signal, and outputting a channel selection signal including an information of the first channel to the first selector so that the first selector connects the first channel and the first non-volatile memory device.
Inventor(s): Gunneswara R. Marripudi of Fremont CA (US) for samsung electronics co., ltd., Vishwanath Maram of San Jose CA (US) for samsung electronics co., ltd.
IPC Code(s): G06F3/06, G06F11/34
CPC Code(s): G06F3/0653
Abstract: provided is a storage device including a first non-volatile storage media having first performance capabilities; a second non-volatile storage media having second performance capabilities different from the first performance capabilities; and a device controller configured to report to a host software the first performance capabilities, the second performance capabilities, changes to the first performance capabilities, and changes to the second performance capabilities.
Inventor(s): Vinod Kumar DAGA of Cupertino CA (US) for samsung electronics co., ltd., Angel AVILES of San Jose CA (US) for samsung electronics co., ltd., Venkata Bhanu Prakash GOLLAPUDI of Pleasanton CA (US) for samsung electronics co., ltd.
IPC Code(s): G06F3/06, G06F13/16
CPC Code(s): G06F3/0655
Abstract: provided is a method of data storage in a data storage system, the method including identifying object headers respectively corresponding to object data, storing the object data at one side of an allocated data chunk, and storing the object headers at another side of the allocated data chunk.
Inventor(s): Chun-Chu Chen-Jhy Archie WU of San Carlos CA (US) for samsung electronics co., ltd., Sumanth JANNYAVULA VENKATA of Pleasanton CA (US) for samsung electronics co., ltd., Young Deok KIM of San Jose CA (US) for samsung electronics co., ltd.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0659
Abstract: methods and devices are provided in which a controller of a storage device generates copy-read subcommands and copy-write subcommands of a copy command. the controller executes a blocking no-operation (nop) command that spans a first storage address range of the copy-write subcommands in a first storage address space. the controller generates a mapping of the copy-write subcommands from the first storage address range, to mapped copy-write subcommands at a corresponding second storage address range in a second storage address space that is higher than a maximum storage address of the first storage address space. the controller executes the copy-read subcommands and the mapped copy-write subcommands. the mapped copy-write subcommands copy data for execution at the first storage address range.
Inventor(s): Jimin RYU of Hwaseong-si (KR) for samsung electronics co., ltd., Jongju KIM of Yeongcheon-si (KR) for samsung electronics co., ltd., Jeong-Woo PARK of Hwaseong-si (KR) for samsung electronics co., ltd., Byung-Ki LEE of Hwaseong-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: disclosed is a storage device, which includes a nonvolatile memory device, and a controller that controls the nonvolatile memory device. in response to a first command, a barrier command, and a second command being received from an external host device, the controller supports an order guarantee between the first command and the second command. each of the first command and the second command is selected from two or more different commands. in response to a request from the external host device, the controller circuitry is configured to provide the external host device with a device descriptor associated with the ordering.
Inventor(s): Byeongcheol YOON of Suwon-si (KR) for samsung electronics co., ltd., Yesol LEE of Suwon-si (KR) for samsung electronics co., ltd., Younghak KONG of Suwon-si (KR) for samsung electronics co., ltd., Hyelim PARK of Suwon-si (KR) for samsung electronics co., ltd., Soohyun SUNG of Suwon-si (KR) for samsung electronics co., ltd., Myoungsoo JANG of Suwon-si (KR) for samsung electronics co., ltd., Chihong CHO of Suwon-si (KR) for samsung electronics co., ltd., Juhyeon PAENG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06F3/16, G10L25/66, G10L25/72
CPC Code(s): G06F3/165
Abstract: a method of controlling a home appliance, and an electronic device for performing the method are provided. the method includes obtaining sleep information of a user and operation information of each of a plurality of home appliances, determining a noise source device which causes noise outside a deep sleep range, from among the plurality of home appliances, at a time when a sleep phase of the user included in the sleep information is changed, and controlling operation of the noise source device so that noise caused from the noise source device is generated within the deep sleep range.
Inventor(s): Jongyeon PARK of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06F7/58
CPC Code(s): G06F7/588
Abstract: a processor includes a controller configured to respectively assign different index numbers to a plurality of operations, a shuffling logic configured to perform a bitwise operation based on a modular addition operation and a rotation shift operation on each of the index numbers and to shuffle the index numbers, and an operation logic configured to perform the plurality of operations based on the shuffled index numbers.
Inventor(s): Ilgu Hong of Santa Clara CA (US) for samsung electronics co., ltd., Yang Seok Ki of Palo Alto CA (US) for samsung electronics co., ltd., Changho Choi of San Jose CA (US) for samsung electronics co., ltd.
IPC Code(s): G06F9/455, G06F3/06, G06F9/48
CPC Code(s): G06F9/45558
Abstract: a system for scheduling input/output (i/o) requests from virtual machines includes a storage device including storage device resources for processing i/o requests to access a non-volatile memory of the storage device, a first virtual machine configured to send an i/o request to the storage device, a resource manager configured to calculate a first amount of the storage device resources and assign the first amount to the first virtual machine, and a traffic controller associated with the first virtual machine, the traffic controller being configured to reschedule the i/o request from the first virtual machine based on an availability of the first amount.
Inventor(s): Chun-Chu Chen-Jhy Archie WU of San Carlos CA (US) for samsung electronics co., ltd., Vasili ZHDANKIN of Prior Lake MN (US) for samsung electronics co., ltd., Mark Allen GAERTNER of Minneapolis MN (US) for samsung electronics co., ltd.
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5033
Abstract: a system and method for managing arbitration and command fetching in a data communication system are provided. the method includes determining that a number of command requests is greater than or equal to a minimum fetch threshold or a number of resources to receive the command requests is greater than or equal to a resource threshold, and transmitting the command requests in response to the number of the command requests being greater than or equal to the minimum fetch threshold or the number of resources to receive the command requests being greater than or equal to the resource threshold.
Inventor(s): Ni XUE of Xi'an (CN) for samsung electronics co., ltd., Yeyang WANG of Xi'an (CN) for samsung electronics co., ltd., Zhixue ZHAO of Xi'an (CN) for samsung electronics co., ltd., Jiaming WANG of Xi'an (CN) for samsung electronics co., ltd.
IPC Code(s): G06F11/22, G06F11/277
CPC Code(s): G06F11/2268
Abstract: an anomaly detection processing method and device for solid-state drive (ssd) are provided. the anomaly detection processing method for ssd including collecting test data of an ssd, the test data including at least one of self-monitoring, analysis and reporting technology s.m.a.r.t. data, nand flash cell threshold voltage distribution data, and bit error rate eye diagram data, determining whether the ssd has an anomaly based on the test data, and determining an anomaly cause of the ssd based on a subset of test data, the subset including specific test data based on which the ssd has been determined to have an anomaly may be provided.
Inventor(s): YOUNGSAM SHIN of SUWON-SI (KR) for samsung electronics co., ltd., DEOK JAE OH of SUWON-SI (KR) for samsung electronics co., ltd., YEONGON CHO of SUWON-SI (KR) for samsung electronics co., ltd.
IPC Code(s): G06F12/1009, G06F12/1036, G06F12/1081
CPC Code(s): G06F12/1009
Abstract: a memory device includes a memory and a controller. the memory is configured to store data. the controller is configured to receive first address data based on multi-level paging from a processing unit, convert the first address data into second address data by performing on at least one of levels a page table walk of the multi-level paging, and access the memory using the second address data.
Inventor(s): Beomwoo Lee of Suwon si (KR) for samsung electronics co., ltd., Donghyon Kang of Suwon si (KR) for samsung electronics co., ltd., Mikyung Kim of Suwon si (KR) for samsung electronics co., ltd., Cheonsu Lee of Suwon si (KR) for samsung electronics co., ltd.
IPC Code(s): G06F13/20, G06F1/06
CPC Code(s): G06F13/20
Abstract: an interface functional block includes first and second data i/o circuits arranged sequentially along a first axis, a strobe signal i/o circuit disposed at a left side of the first axis from the first data i/o circuit, a clock generator circuit disposed at a right side of the first axis from the second data i/o circuit, first and second type routing cells arranged sequentially along a second axis perpendicular to the first axis at a first axis coordinate of the strobe signal i/o circuit, third and fourth type cells arranged sequentially along the second axis at a first axis coordinate of the first and second data i/o circuits, and further third and fourth type routing cells sequentially arranged. a clock generated by the clock generator circuit is transferred in a left direction of the first axis toward the first and second data i/o circuits and the strobe signal i/o circuit.
Inventor(s): Jiwon LEE of Suwon-si (KR) for samsung electronics co., ltd., Wonhyuk KANG of Suwon-si (KR) for samsung electronics co., ltd., Hyeongseob KIM of Suwon-si (KR) for samsung electronics co., ltd., Choonghoon LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06F16/23
CPC Code(s): G06F16/2379
Abstract: an electronic device is provided. the electronic device includes a communication circuit, memory storing one or more computer programs, and one or more processors communicatively coupled to the communication circuit and the memory. the one or more computer programs include computer-executable instructions that, when executed by the one or more processors, cause the electronic device to transmit a request, through the communication circuit a server configured to relay message transmission between nodes included in a blockchain network, to add a new block to the nodes included in the blockchain network, when the request is not rejected by the server, transmit, through the communication circuit to the server for transmission to the nodes via the server, transaction information to be stored in the new block, generate the new block including the transaction information, receive, through the communication circuit from the server, information about blocks generated by first nodes in an active state among the nodes, based on identifying that a number of blocks identical to the new block among the blocks generated by the first nodes is greater than a designated number, transmit, through the communication circuit to the server, information indicating agreement on adding the new block, and based on the transmitting, to the server, of the information indicating the agreement, add the new block to the memory.
Inventor(s): Jaehyuk LEE of Suwon-si (KR) for samsung electronics co., ltd., Dong-Jin CHANG of Suwon-si (KR) for samsung electronics co., ltd., Sungmeen MYUNG of Suwon-si (KR) for samsung electronics co., ltd., Daekun YOON of Suwon-si (KR) for samsung electronics co., ltd., Seok Ju YUN of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06F17/15
CPC Code(s): G06F17/15
Abstract: a processor-implemented method includes receiving an input vector comprising a plurality of channels, performing a first convolution operation by allocating first chunks, obtained by dividing the input vector, to a plurality of first in-memory computing (imc) macros, and performing a second convolution operation by allocating second chunks obtained by dividing a result of the first convolution operation to a plurality of second imc macros.
Inventor(s): Dongha KIM of Suwon-si (KR) for samsung electronics co., ltd., Seungki Hong of Suwon-si (KR) for samsung electronics co., ltd., Youngjae Park of Suwon-si (KR) for samsung electronics co., ltd., Dohan Kim of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06F21/56, G06F11/10
CPC Code(s): G06F21/566
Abstract: a semiconductor memory device includes a memory cell array, an error correction code (ecc) engine, an error check and scrub (ecs) circuit, a row hammer management circuit and a refresh control circuit. the ecc engine generates an error generation signal based on a result of an ecc decoding. the ecs circuit generates scrubbing addresses and outputs at least one of the scrubbing addresses as an error address based on the error generation signal. the row hammer management circuit stores an error flag with a first logic level in count cells, compares counted values with different reference number of times based on a logic level of the error flag and outputs a hammer address. the refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to the memory cell row corresponding to the hammer address.
Inventor(s): Min Young MUN of Suwon-si (KR) for samsung electronics co., ltd., Seok Ju YUN of Suwon-si (KR) for samsung electronics co., ltd., Sei Joon KIM of Suwon-si (KR) for samsung electronics co., ltd., Sang Joon KIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06N3/0464
CPC Code(s): G06N3/0464
Abstract: a convolutional neural network (cnn)-based analog in-sensor computing device may include a convolution layer including one or more convolution blocks configured to be used a predetermined number of times or more and perform a convolution operation, and an memory configured to temporarily store an output of the convolution layer and provide the stored analog output to a subsequent convolution layer.
Inventor(s): Shih-Chii LIU of Zurich (CH) for samsung electronics co., ltd., Bodo RUECKAUER of Zurich (CH) for samsung electronics co., ltd., Tobi DELBRUCK of Zurich (CH) for samsung electronics co., ltd.
IPC Code(s): G06N3/063, G06N3/082, G06N5/046
CPC Code(s): G06N3/063
Abstract: a processor-implemented neural network method includes: determining a reference sample among sequential input samples to be processed by a neural network, the neural network comprising an input layer, one or more hidden layers, and an output layer; performing an inference process of obtaining an output activation of the output layer based on operations in the hidden layers corresponding to the reference sample input to the input layer; determining layer contraction parameters for determining an affine transformation relationship between the input layer and the output layer, for approximation of the inference process; and performing inference on one or more other sequential input samples among the sequential input samples using affine transformation based on the layer contraction parameters determined with respect to the reference sample.
Inventor(s): Youngmin OH of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06N3/082
CPC Code(s): G06N3/082
Abstract: provided are an apparatus and method of compressing an artificial neural network. according to the method and the apparatus, an optimal compression rate and an optimal operation accuracy are determined by compressing an artificial neural network, determining a task accuracy of a compressed artificial neural network, and automatically calculating a compression rate and a compression ratio based on the determined task accuracy. the method includes obtaining an initial value of a task accuracy for a task processed by the artificial neural network, compressing the artificial neural network by adjusting weights of connections among layers of the artificial neural network included in information regarding the connections, determining a compression rate for the compressed artificial neural network based on the initial value of the task accuracy and a task accuracy of the compressed artificial neural network, and re-compressing the compressed artificial neural network according to the compression rate.
Inventor(s): Jyotirmoy KARJEE of Bengaluru (IN) for samsung electronics co., ltd., Praveen Naik S of Bangalore (IN) for samsung electronics co., ltd., Srinidhi NAGARAJA RAO of Bangalore (IN) for samsung electronics co., ltd., Eric Ho Ching YIP of Suwon-si (KR) for samsung electronics co., ltd., Prasenjit CHAKRABORTY of Bangalore (IN) for samsung electronics co., ltd., Ramesh Babu Venkat DABBIRU of Bangalore (IN) for samsung electronics co., ltd.
IPC Code(s): G06N3/098
CPC Code(s): G06N3/098
Abstract: systems and methods for optimal split federated learning (o-sfl) in a wireless network, including: receiving, by a federal device in the wireless network, local split points associated with a deep neural network (dnn) model over a time period from at least one client device of a plurality of client devices, wherein the plurality of client devices are connected to an edge device for training the dnn model using split federated learning (sfl); determining, by the federal device, an average of the local split points; determining, by the federal device, a global split point for partitioning the dnn model between the at least one client device and the edge device based on the average of the local split points; and applying, by the federal device, the determined global split point to train the dnn model.
Inventor(s): Hee Min CHOI of Suwon-si (KR) for samsung electronics co., ltd., Hyo A KANG of Suwon-si (KR) for samsung electronics co., ltd., Su Ji KIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06T3/4053, G06V10/77, G06V10/82
CPC Code(s): G06T3/4053
Abstract: a method of generating a model for image processing includes increasing, using a receptive field (rf) increasing module of at least one processor, a receptive field of an input image frame; generating, using a feature extraction (fe) module of the at least one processor, a feature map based on the input image frame with an increased receptive field; generating, using a super resolution (sr) module of the at least one processor, a target image having a target resolution, based on the feature map; and generating, using a model generation (mg) module of the at least one processor, a replacement model that replaces at least one of the rf increasing module, the fe module, and the sr module.
Inventor(s): Younghyun JO of Suwon-si (KR) for samsung electronics co., ltd., Sehwan KI of Suwon-si (KR) for samsung electronics co., ltd., Jung Soo KIM of Suwon-si (KR) for samsung electronics co., ltd., Dusic YOO of Suwon-si (KR) for samsung electronics co., ltd., Hyong Euk LEE of Suwon-si (KR) for samsung electronics co., ltd., Seungwon CHOI of Suwon-si (KR) for samsung electronics co., ltd., Jongseong CHOI of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06T5/50, G06T3/4007, G06T3/4053, G06T5/70
CPC Code(s): G06T5/50
Abstract: a processor-implemented method with super resolution includes: determining a direction type of an input image based on a gradient of the input image; acquiring a first intermediate image that is a super-resolution image corresponding to the input image based on a residual look-up table (lut) corresponding to a kernel set mapped to the determined direction type; determining a lut strength map of the input image based on the gradient of the input image and a preset tuning parameter; and generating an output image that is a super-resolution image of the input image based on the lut strength map and the first intermediate image.
20250014169. METHOD OF INSPECTING DEFECTS_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Bumjoo LEE of Suwon-si (KR) for samsung electronics co., ltd., Jinwoo LEE of Suwon-si (KR) for samsung electronics co., ltd., Suyoung LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06T7/00, G06T5/20, G06T5/70, G06T7/11
CPC Code(s): G06T7/001
Abstract: a defect inspection method includes: recognizing image peaks that are reference positions of image patterns included an inspection image; performing filtering on a reference image including reference patterns, recognizing reference peaks, and then selecting some of the reference peaks as peak samples; calculating candidate correction constants by overlapping the filtered inspection image and the filtered reference image, and then selecting a primary correction constant among the candidate correction constants; applying the first correction constant to the reference image and selecting a secondary correction constant by matching the image peaks to the reference peaks included in a primary corrected reference image, and then applying the secondary correction constant to the primary corrected reference image and forming a secondary corrected reference image aligned with the inspection image; and performing a defect inspection on the inspection image by matching the image patterns to reference patterns included in the secondary corrected reference image.
Inventor(s): Woo Jung PARK of Suwon-si (KR) for samsung electronics co., ltd., Jinhyuk CHOI of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06T7/55, G06T7/60
CPC Code(s): G06T7/55
Abstract: a processor-implemented method includes: determining a first length of a captured object included in an image frame captured by a single camera; determining a second length of a real object corresponding to the captured object; and estimating a target distance between an apparatus and the real object based on a ratio between the first length and the second length.
Inventor(s): Suhyun KIM of Gyeonggi-do (KR) for samsung electronics co., ltd., Dongil SON of Gyeonggi-do (KR) for samsung electronics co., ltd., Dohyoung KIM of Gyeonggi-do (KR) for samsung electronics co., ltd., Hyeongseok KIM of Gyeonggi-do (KR) for samsung electronics co., ltd., Gyujin LEE of Gyeonggi-do (KR) for samsung electronics co., ltd., Seungjoon LEE of Gyeonggi-do (KR) for samsung electronics co., ltd.
IPC Code(s): G06T11/60, G06F3/01, G06F3/16, G06V20/20, G06V40/20
CPC Code(s): G06T11/60
Abstract: a wearable device comprises a display, a sensor, a communication circuit, memory comprising instructions, and at least one processor. the instructions, when executed by the at least one processor, cause the wearable device to identify a context representing a situation of a user and a position of an object associated with the context based on information obtained through the sensor and the communication circuit, display a first visual object superimposed on a periphery of the object based on verifying that the object is positioned within a first area in a field of view (fov) area of the wearable device, display by blinking the first visual object based on verifying that the object is positioned within a second area in the fov area, and display a second visual object representing the object in the fov area based on verifying that the object is positioned outside of the fov area.
Inventor(s): Jisu RYU of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06V10/141, G06T7/20, G06V40/18, G06V40/19, H04N23/56, H04N23/90
CPC Code(s): G06V10/141
Abstract: a wearable device is provided. the wearable device includes a plurality of light sources configured to emit light toward an eye of a user wearing the wearable device. the wearable device includes a camera configured to capture images of at least a part of the eye of the user wearing the wearable device. the wearable device includes at least one processor comprising processing circuitry. the wearable device includes memory, comprising one or more storage mediums, storing instructions. the wearable device performs eye tracking based on the images captured by the camera while the plurality of the light sources are controlled to emit light toward the eye of the user. the wearable device performs iris recognition based on at least one image captured by the camera while a portion of the plurality of the light sources is controlled to emit light toward the eye of the user and a remaining portion of the plurality of the light sources is deactivated.
Inventor(s): Wenjuan LIU of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G06V10/60, G06T5/20, G06T5/40
CPC Code(s): G06V10/60
Abstract: the present disclosure provides an image processing method, an image processing device, an electronic apparatus, and a storage medium. the image processing method includes determining a dark channel image of an input image; determining an atmospheric luminosity according to a grayscale histogram of the dark channel image; determining a dehazing image of the input image based on the atmospheric luminosity.
Inventor(s): Pil-Seung HEO of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G09G3/20, H03M7/30
CPC Code(s): G09G3/2096
Abstract: a method performed by a mura compensation data generation device, the method includes: generating optical information for a plurality of pixels of a display panel operating based on test data; generating, based on the optical information, raw mura compensation data to compensate input video data provided to the display panel; extracting a high spatial frequency component and a low spatial frequency component from the raw mura compensation data; generating a compressed high spatial frequency component, by compressing, based on a first compression algorithm, the high spatial frequency component; generating a compressed low spatial frequency component, by compressing, based on a second compression algorithm, the low spatial frequency component; and storing the compressed high spatial frequency component and the compressed low spatial frequency component in an external storage circuit.
20250014515. DISPLAY DEVICE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Sunkwon KIM of Suwon-si (KR) for samsung electronics co., ltd., Uijong Song of Suwon-si (KR) for samsung electronics co., ltd., Yongil Kwon of Suwon-si (KR) for samsung electronics co., ltd., Seongyoung Ryu of Suwon-si (KR) for samsung electronics co., ltd., Yilho Lee of Suwon-si (KR) for samsung electronics co., ltd., Heejin Lee of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G09G3/3233
CPC Code(s): G09G3/3233
Abstract: a display device includes pixels arranged in rows and columns, a scan driver, and a read-out circuit, wherein the read-out circuit is configured to read-out electrical properties of a pixel through the read-out line. the first pixel includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first organic light-emitting diode connected between a second electrode of the seventh transistor and a ground node to which a ground voltage is applied, a second organic light-emitting diode between the second electrode of the eighth transistor and the ground node, and a third organic light-emitting diode connected between the second electrode of the ninth transistor and the ground node.
Inventor(s): Minhoon LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G09G3/34, G09G3/32
CPC Code(s): G09G3/3426
Abstract: a display device includes a backlight, a pixel controlling unit, a power driving unit, a source driving unit which transmits, to the pixel controlling unit, intensities of the leds connected to the pixel controlling unit, and a timing controlling unit. the pixel controlling unit adjusts, in a first time section, an intensity of a first led based on a first intensity received from the source driving unit, wherein the first led is connected to a first line which is activated by the power driving. the pixel controlling unit adjusts, in a second time section different from the first time section, an intensity of a second led based on a second intensity received from the source driving unit, wherein the second led is connected to a second line which is activated by the power driving unit.
Inventor(s): Vishwanath Pethri KAMATH of Bengaluru (IN) for samsung electronics co., ltd., Sushant KUMAR of Bengaluru (IN) for samsung electronics co., ltd.
IPC Code(s): G10L15/22, G10L15/18
CPC Code(s): G10L15/22
Abstract: a method for handling voice input by voice assistant device are provided. the method includes receiving, by the voice assistant device, a voice input from a user; identifying, by the voice assistant device, at least one first user intent and a plurality of slots based on the voice input, wherein the plurality of slots may include at least one slot related to the at least one first user intent and at least one slot unrelated to the at least one first user intent; identifying, by the voice assistant device, at least one second user intent based on the voice input and the at least one slot unrelated to the at least one first user intent; and performing, by the voice assistant device, at least one first operation based on the at least one first user intent and at least one second operation based on the at least one second user intent.
Inventor(s): Gyuseong Kang of Suwon-si (KR) for samsung electronics co., ltd., EUNJI LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G11C11/16
CPC Code(s): G11C11/1657
Abstract: a memory device includes a memory cell having an access transistor and a variable resistance element, a word line connected to a gate of the access transistor, and a gate driver circuit configured to provide a word line voltage to the word line in a read operation or a write operation, receive, during the read operation, a first power supply voltage from a power terminal and provide a second power supply voltage lower than the first power supply voltage to the word line by attenuating the first power supply voltage to the second power supply voltage, and receive, during the write operation, a third power supply voltage higher than the first power supply voltage from the power terminal and provide the third power supply voltage to the word line without attenuating the third power supply voltage.
Inventor(s): Chanho Lee of Suwon-si (KR) for samsung electronics co., ltd., Junghak Song of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G11C11/16
CPC Code(s): G11C11/1659
Abstract: a memory device may include a cell array including a first section and a second section that share a plurality of word lines comprising a first set of word lines and a second set of word lines, a first column decoder configured to select at least one bit line of a first set of bit lines connected to the first section, a second column decoder configured to select at least one bit line of a second set of bit lines connected to the second section, and a read circuit configured to output a data signal based on a comparison between an output of the first column decoder and an output of the second column decoder. the first section includes a plurality of first memory cells connected to at least one word line from the first set of word lines and configured to store bits of calibration data for calibrating the memory device, and the second section includes a plurality of second memory cells connected to the at least one word line and configured to store inverted bits of the calibration data.
Inventor(s): Jaehyeok Baek of Suwon-si (KR) for samsung electronics co., ltd., Sungyong Cho of Suwon-si (KR) for samsung electronics co., ltd., Hyeran Kim of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G11C11/4076, G11C11/4093, G11C11/4099
CPC Code(s): G11C11/4076
Abstract: a memory device includes a data input/output (i/o) pin, an output driver, a multi-level receiver and a calibrator. the output driver is connected to the data i/o pin, and generates an internal input signal based on a first clock signal. the multi-level receiver is connected to the data i/o pin, and includes a plurality of samplers. the plurality of samplers generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a second clock signal. the calibrator detects and compensates at least one of timing skew and offset associated with the plurality of samplers based on the plurality of decision signals. the internal input signal is a multi-level signal having three or more voltage levels that are different from each other.
Inventor(s): Seunghan Kim of Suwon-si (KR) for samsung electronics co., ltd., Gunhee Cho of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G11C11/4093, G11C11/4076, G11C11/408, G11C11/4096
CPC Code(s): G11C11/4093
Abstract: a semiconductor memory device includes a data input/output (i/o) buffer, a data first-in/first-out (fifo) circuit, an address comparing circuit. the data i/o buffer provides a memory cell array with write data. the data fifo circuit includes plurality of data fifo buffers which store read data that is read from the memory cell array in each of a plurality of read operations. the data fifo circuit outputs data stored in one of the plurality of data fifo buffers based on a plurality of sub matching signals. the address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.
Inventor(s): Jinseok KIM of Incheon (KR) for samsung electronics co., ltd., Yulhwa KIM of Daegu (KR) for samsung electronics co., ltd., Jae-Joon KIM of Pohang-si (KR) for samsung electronics co., ltd., Hyungjun KIM of Pohang-si (KR) for samsung electronics co., ltd.
IPC Code(s): G11C11/412, G06N3/08, G11C11/418, G11C11/419
CPC Code(s): G11C11/412
Abstract: disclosed are a first memory cell, a second memory cell, and a summing circuit. the first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. the second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
Inventor(s): Jaeduk LEE of Seongnam-si (KR) for samsung electronics co., ltd., Kinam Kim of Seoul (KR) for samsung electronics co., ltd., Sujin Ahn of Seoul (KR) for samsung electronics co., ltd.
IPC Code(s): G11C16/04, H01L23/522, H01L23/528, H10B41/10, H10B41/27, H10B41/35, H10B41/41, H10B43/10, H10B43/27, H10B43/35, H10B43/40
CPC Code(s): G11C16/0483
Abstract: provided are semiconductor devices and data storage systems including the same. the semiconductor devices may include first and second separation structures parallel to each other, a block between the first and second separation structures, and bit lines on the block. the block includes strings, the bit lines include a first bit line electrically connected to first and second strings, each of the strings includes a lower select transistor, memory cell transistors, and upper select transistors connected in series, the upper select transistors in each of the strings include a first upper select transistor and a second upper select transistor below the first upper select transistor. the first upper select transistors of the first and second strings may share a single first upper select gate electrode. gate electrodes of the lower select transistors of the first and second strings may include surfaces coplanar with each other.
Inventor(s): Minsu Kim of Suwon-si (KR) for samsung electronics co., ltd., Hongsoo Jeon of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G11C16/08, G11C5/06, G11C16/04, H10B41/10, H10B41/27, H10B41/35, H10B41/41, H10B43/10, H10B43/27, H10B43/35, H10B43/40
CPC Code(s): G11C16/08
Abstract: a nonvolatile memory device includes first and second semiconductor layers and pass transistors. the first semiconductor layer includes wordlines that extend in a first direction and bitlines that extend in a second direction, and further includes a first substrate and a memory cell array. the memory cell array is on the first substrate and connected to the wordlines and the bitlines. the second semiconductor layer is arranged with respect to the first semiconductor layer in a third direction, and includes a second substrate and a peripheral circuit. the peripheral circuit is on the second substrate and controls the memory cell array. the pass transistors are connected to the wordlines and control an electrical connection between the memory cell array and the peripheral circuit. a first part of the pass transistors are in the first semiconductor layer, and a second part of the pass transistors are in the second semiconductor layer.
Inventor(s): Won-bo SHIM of Seoul (KR) for samsung electronics co., ltd., Ji-ho CHO of Suwon-si (KR) for samsung electronics co., ltd., Yong-seok KIM of Suwon-si (KR) for samsung electronics co., ltd., Byoung-taek KIM of Hwaseong-si (KR) for samsung electronics co., ltd., Sun-gyung HWANG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G11C16/10, G06F3/06, G11C11/56, G11C16/04, G11C16/08, G11C16/34, H01L29/788, H10B41/35, H10B43/27, H10B43/35
CPC Code(s): G11C16/10
Abstract: a program method of a nonvolatile memory device that performs a plurality of program loops is provided. at least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (hci) program operation on a selected memory cell corresponding to the first side channel or the second side channel.
Inventor(s): Minuk KIM of Suwon-si (KR) for samsung electronics co., ltd., Soonyoung Kang of Suwon-si (KR) for samsung electronics co., ltd., Kwanwoo Noh of Suwon-si (KR) for samsung electronics co., ltd., Dong-Min Shin of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G11C16/10, G11C16/08
CPC Code(s): G11C16/102
Abstract: a storage device includes a nonvolatile memory device including a plurality of first memory cells coupled to a first wordline and a plurality of second memory cells coupled to a second wordline, the first wordline and the second wordline being adjacent to each other, and a storage controller configured to control the nonvolatile memory device. the storage controller is further configured to encode data to be programmed into the plurality of second memory cells, based on a program state of each of the plurality of first memory cells, and encode the data to be programmed into the second wordline such that a first portion of the data to be written into a first portion of the plurality of second memory cells satisfies a first condition, and a second portion of the data to be written into a second portion of the plurality of second memory cells satisfies a second condition.
Inventor(s): Youhwan Kim of Suwon-si (KR) for samsung electronics co., ltd., Kyungduk Lee of Suwon-si (KR) for samsung electronics co., ltd., Suyong Jang of Suwon-si (KR) for samsung electronics co., ltd., Hankyu Ko of Suwon-si (KR) for samsung electronics co., ltd., Ho-Sung Ahn of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G11C16/34, G11C16/10, G11C16/16, G11C16/28
CPC Code(s): G11C16/3495
Abstract: the present disclosure relates to storage devices. an example storage device includes a nonvolatile memory device that includes a plurality of memory blocks, and a memory controller that controls the nonvolatile memory device. the memory controller performs a soft erase operation on a first memory block among the plurality of memory blocks, measures a first cell count by applying a first reference voltage to a plurality of first memory cells selected in advance from a plurality of memory cells of the first memory block after performing the soft erase operation, generates a first health index associated with a retention characteristic of the first memory block based on the first cell count, and performs a reliability management operation on the first memory block based on the first health index.
Inventor(s): Minji Cho of Suwon-si (KR) for samsung electronics co., ltd., Hee-Woong Kang of Suwon-si (KR) for samsung electronics co., ltd., Jin-Young Kim of Suwon-si (KR) for samsung electronics co., ltd., Se Hwan Park of Suwon-si (KR) for samsung electronics co., ltd., Ji-Sang Lee of Suwon-si (KR) for samsung electronics co., ltd., Heewon Lee of Suwon-si (KR) for samsung electronics co., ltd., Su Chang Jeon of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G11C29/12, G11C29/42
CPC Code(s): G11C29/12005
Abstract: disclosed is a method of operating a storage device which includes a storage controller and a non-volatile memory device. the method includes providing, by the storage controller, the non-volatile memory device with a first request indicating a wordline selection operation of a target memory block, obtaining, by the non-volatile memory device, distribution information of a plurality of wordlines of the target memory block based on the first request, determining, by the non-volatile memory device, a deterioration wordline among the plurality of wordlines based on the distribution information, and providing, by the non-volatile memory device, the storage controller with wordline information indicating the deterioration wordline.
Inventor(s): Sang-Won Park of Suwon-si (KR) for samsung electronics co., ltd., Kuihan Ko of Suwon-si (KR) for samsung electronics co., ltd., Heewon Son of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): G11C29/52, G11C16/08, G11C16/16
CPC Code(s): G11C29/52
Abstract: a non-volatile integrated circuit memory device includes a first memory block having first and second memory sub-blocks therein, and a second memory block having third and fourth memory sub-blocks therein. a sub-block manager is also provided, which is configured to: (i) determine whether the second memory sub-block is a reclaim sub-block when the first memory sub-block has an uncorrectable error (uecc) therein, and (ii) reclaim the first and second memory sub-blocks to the third and fourth memory sub-blocks, respectively, in response to determining that the second memory sub-block is a reclaim sub-block.
Inventor(s): Sunwoo Han of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01G4/232, H01G4/30, H05K1/18
CPC Code(s): H01G4/232
Abstract: provided is a capacitor including a ceramic main body, an internal electrode inside the ceramic main body, and a plurality of external electrodes respectively on a first surface and a second surface that are opposite to each other in a horizontal direction of the ceramic main body. each of the plurality of external electrodes includes one or more prevention portions protruding in an outward direction of the ceramic main body or recessed in an inward direction of the ceramic main body.
Inventor(s): Sungwon CHO of Suwon-si (KR) for samsung electronics co., ltd., Kyunghyun KIM of Suwon-si (KR) for samsung electronics co., ltd., Ingi KIM of Suwon-si (KR) for samsung electronics co., ltd., Sangki NAM of Suwon-si (KR) for samsung electronics co., ltd., Dougyong SUNG of Suwon-si (KR) for samsung electronics co., ltd., Sejin OH of Suwon-si (KR) for samsung electronics co., ltd., Sungho JANG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01J37/32, H01L21/683
CPC Code(s): H01J37/32568
Abstract: according to an aspect of the present inventive concepts, a semiconductor processing apparatus includes: a chamber; an electrostatic chuck in an internal space of the chamber; a plurality of grid electrodes installed on the electrostatic chuck so as to be separated from each other in a first direction, perpendicular to an upper surface of the electrostatic chuck, and respectively having a plurality of through-holes; a plurality of reflectors between the plurality of grid electrodes and the electrostatic chuck and reflecting ions passing through the plurality of through-holes in each of the plurality of grid electrodes; and a voltage supply unit outputting a bias voltage having a predetermined cycle to at least one of the plurality of grid electrodes, wherein each of the plurality of grid electrodes includes a base plate containing a conductive material, and a cover layer covering a surface of the base plate and containing a metal oxide.
Inventor(s): SANGJINE PARK of Suwon-si (KR) for samsung electronics co., ltd., Ji Hwan PARK of Suwon-si (KR) for samsung electronics co., ltd., KUNTACK LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L21/67, G03F7/16, H01L21/66
CPC Code(s): H01L21/67051
Abstract: disclosed are substrate processing systems and substrate processing methods. the substrate processing method comprises performing an exposure process on a substrate, removing moisture on the substrate after the exposure process, performing a wetting process on the substrate from which the moisture is removed, and performing a drying process on the substrate after the wetting process. the step of removing the moisture on the substrate includes measuring a weight of the substrate and heating the substrate whose weight is measured. the step of performing the drying process on the substrate includes placing the substrate into a dry chamber and supplying the dry chamber with a supercritical fluid to dry a fluid on the substrate.
Inventor(s): Duckgyu Kim of Suwon-si (KR) for samsung electronics co., ltd., Sanguk Han of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/13, H01L21/48, H01L21/78, H01L23/498
CPC Code(s): H01L23/13
Abstract: provided is a semiconductor package including a rewiring structure including a rewiring pattern, and at least one insulating layer, a semiconductor device provided on the rewiring structure, and electrically connected to the rewiring pattern, and a side surface protector covering a first side surface of the semiconductor device, wherein an upper surface of the semiconductor device that is opposite to a lower surface of the semiconductor device facing the rewiring structure and an upper surface of the side surface protector are at the same vertical level and are coplanar with each other, and the side surface protector extends from the insulating layer of the rewiring structure.
Inventor(s): Jingu KIM of Suwon-si (KR) for samsung electronics co., ltd., Gongje LEE of Suwon-si (KR) for samsung electronics co., ltd., Yongjun LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/31, H01L23/00, H01L23/14, H01L23/26, H01L23/29, H01L23/49, H01L23/498, H01L25/00, H01L25/10
CPC Code(s): H01L23/3107
Abstract: a semiconductor package includes: a first redistribution structure including a first redistribution pattern and a first redistribution insulating layer at least partially surrounding the first redistribution pattern; a first semiconductor chip disposed on the first redistribution structure; a first molding member at least partially surrounding the first semiconductor chip and the first redistribution structure; a conductive pillar passing through the first molding member; a second redistribution structure disposed on the first molding member and including a second redistribution pattern and a second redistribution insulating layer at least partially surrounding the second redistribution pattern; a second semiconductor chip disposed on the second redistribution structure; and a second molding member at least partially surrounding the second semiconductor chip and the second redistribution structure.
20250014958. SEMICONDUCTOR PACKAGE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Jeonggi Jin of Seoul (KR) for samsung electronics co., ltd., Jumyong Park of Yongin-si (KR) for samsung electronics co., ltd., Jinho An of Seoul (KR) for samsung electronics co., ltd., Taehwa Jeong of Hwaseong-si (KR) for samsung electronics co., ltd., Jinho Chun of Seoul (KR) for samsung electronics co., ltd., Juil Choi of Seongnam-si (KR) for samsung electronics co., ltd., Atsushi Fujisaki of Seongnam-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/31, H01L23/29, H01L23/522
CPC Code(s): H01L23/3114
Abstract: a semiconductor package includes: a lower package including a lower semiconductor chip, a molding layer on a side surface of the lower semiconductor chip, a conductive post in the molding layer and having a concave top surface, a lower redistribution pattern electrically connecting the lower semiconductor chip to the conductive post, and an upper redistribution electrically connected the conductive post; and an upper package on the lower package, the upper package including an upper semiconductor chip. a first portion of an inner wall of the molding layer contacts a sidewall of the conductive post, and a second portion of the inner wall of the molding layer extends vertically above the top surface of the conductive post, wherein the first and second portions of the inner wall of the molding layer are vertically coplanar with each other and with the sidewall of the conductive post.
20250014963. SEMICONDUCTOR PACKAGE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Yongkwan Lee of Suwon-si (KR) for samsung electronics co., ltd., Kundae Yeom of Suwon-si (KR) for samsung electronics co., ltd., Hyeon Hwang of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/367, H01L23/00, H01L23/31, H01L25/18
CPC Code(s): H01L23/3675
Abstract: a semiconductor package includes a substrate, a first semiconductor chip on the substrate, a heat-dissipating structure on the first semiconductor chip, an adhesive layer between the first semiconductor chip and the heat-dissipating structure, a second semiconductor chip on the heat-dissipating structure, a molding film on the substrate and covering at least portions of the first semiconductor chip, the heat-dissipating structure, and the second semiconductor chip, and a shield layer on an upper surface and sidewalls of the molding film, wherein the shield layer includes a first portion extending into a first hole and contacting an upper surface of the first semiconductor chip, and the first hole may penetrate the molding film, the heat-dissipating structure, and the adhesive layer.
20250014968. SEMICONDUCTOR DEVICE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): SHAOFENG DING of Suwon-si (KR) for samsung electronics co., ltd., JEONG HOON AHN of Seongnam-si (KR) for samsung electronics co., ltd., YUN KI CHOI of Yongin-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/48, H01L23/00, H01L23/522, H01L23/528, H01L25/18
CPC Code(s): H01L23/481
Abstract: a semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. the first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. the second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. a first width in a first direction of the first via is greater than a second width in the first direction of the second via.
Inventor(s): Yun-Seok CHOI of Hwasung-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L23/485, H01L23/538
CPC Code(s): H01L23/49816
Abstract: a semiconductor package includes a package substrate, an interposer on the package substrate, and a first semiconductor device and a second semiconductor device on the interposer, the first and second semiconductor devices connected to each other by the interposer, wherein at least one of the first semiconductor device and the second semiconductor device includes an overhang portion protruding from a sidewall of the interposer.
Inventor(s): Jin YANG of San Jose CA (US) for samsung electronics co., ltd.
IPC Code(s): H01L23/522, H01L23/00, H01L23/498, H01L23/538, H01L25/00, H01L25/065
CPC Code(s): H01L23/5223
Abstract: provided is a semiconductor package which includes: a die stack including at least two semiconductor chips laterally arranged and isolated from each other by a molding material; and an interconnect package disposed above or below the die stack and connecting the semiconductor chips to each other, wherein the interconnect package having a smaller lateral width than the die stack is entirely overlapped by the die stack in a vertical direction, and a capacitor is disposed inside the interconnect package and connected to at least one of the semiconductor chips and configured to be connected to a voltage source and a ground.
Inventor(s): Rui ZHANG of Santa Clara CA (US) for samsung electronics co., ltd., Kyoungsoo Kim of Cupertino CA (US) for samsung electronics co., ltd., WooPoung Kim of Cupertino CA (US) for samsung electronics co., ltd.
IPC Code(s): H01L23/522, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L23/5223
Abstract: a semiconductor package comprises a core layer, an integrated stack capacitor (isc) on the core layer, one or more build-up layers on the core layer in which the isc is embedded, and one or more metal layers on the core layer.
20250014995. SEMICONDUCTOR DEVICES_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Jinwoo LEE of Suwon-si (KR) for samsung electronics co., ltd., Hojun CHOI of Suwon-si (KR) for samsung electronics co., ltd., Sutae KIM of Suwon-si (KR) for samsung electronics co., ltd., Hyelim KIM of Suwon-si (KR) for samsung electronics co., ltd., Seung CHOI of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/528, H01L23/522, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L23/5283
Abstract: a semiconductor device includes a plurality of active patterns respectively extending on a substrate in a first direction, a separation pattern extending on the substrate in a second direction, and dividing each of the plurality of active patterns into first and second active patterns, the separation pattern including a first separation pattern and a second separation pattern, the second separation pattern being shifted from the first separation pattern in the first direction to partially overlap the first separation pattern in the second direction, first and second dummy gate structures on first and second sides of the separation pattern, respectively, and extending along corresponding end portions of the first and second active patterns in the second direction, respectively, and a plurality of first and second gate structures crossing portions of the first and second active patterns, respectively, and extending in the second direction.
Inventor(s): Seungyoon Kim of Suwon-si (KR) for samsung electronics co., ltd., Jeongyong Sung of Suwon-si (KR) for samsung electronics co., ltd., Sanghun Chun of Suwon-si (KR) for samsung electronics co., ltd., Jihwan Kim of Suwon-si (KR) for samsung electronics co., ltd., Sunghee Chung of Suwon-si (KR) for samsung electronics co., ltd., Jeehoon Han of Hwaseong-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/528, H01L29/423, H10B43/27
CPC Code(s): H01L23/5283
Abstract: a semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.
Inventor(s): Junghoo SHIN of Seoul (KR) for samsung electronics co., ltd., Jongmin Baek of Seoul (KR) for samsung electronics co., ltd., Sanghoon Ahn of Seongnam-si (KR) for samsung electronics co., ltd., Woojin Lee of Hwaseong-si (KR) for samsung electronics co., ltd., Junhyuk Lim of Hwaseong-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L23/5283
Abstract: a semiconductor integrated circuit device includes a substrate; a transistor on the substrate; an interlayer insulating film on the transistor; an insulating liner on the interlayer insulating film; a first insulating film on the insulating liner; and a first wiring layer on the interlayer insulating film and surrounded by the insulating liner. a height of a top surface of the first insulating film in a vertical direction from a main surface of the interlayer insulating film is different than a height of a top surface of the first wiring layer in the vertical direction. a step exists between the top surfaces of the first wiring layer and the first insulating film. a height of the first insulating film is greater than a height of the first wiring layer. a width of the first wiring layer gradually narrows as the first wiring layer extends upwards along the vertical direction.
20250015005. SEMICONDUCTOR PACKAGE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Keunyoung Lee of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/538, H01L23/00, H01L25/065, H01L25/10, H10B80/00
CPC Code(s): H01L23/5382
Abstract: a semiconductor package includes: a plurality of transmission external terminals; a plurality of reception external terminals; a semiconductor chip including a plurality of transmission pads, a plurality of reception pads, and at least one option pad; a plurality of transmission lanes electrically connected between the plurality of transmission external terminals and the plurality of transmission pads; and a plurality of reception lanes electrically connected between the plurality of reception external terminals and the plurality of reception pads. the semiconductor chip is configured to swap signals or connections for the plurality of transmission pads, or swap signals or connections for the plurality of reception pads, selectively depending on an input of the at least one option pad.
20250015009. SEMICONDUCTOR PACKAGE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Ju-Il CHOI of Seongnam-si (KR) for samsung electronics co., ltd., Gyuho KANG of Cheonan-si (KR) for samsung electronics co., ltd., Un-Byoung KANG of Hwaseong-si (KR) for samsung electronics co., ltd., Byeongchan KIM of Asan-si (KR) for samsung electronics co., ltd., Junyoung PARK of Asan-si (KR) for samsung electronics co., ltd., Jongho LEE of Hwaseong-si (KR) for samsung electronics co., ltd., Hyunsu HWANG of Siheung-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/538, H01L23/00, H01L23/31, H01L23/498, H01L25/10
CPC Code(s): H01L23/5389
Abstract: a semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. the via portion, the pad portion, and the line portion may be connected to each other to form a single object. a level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. a width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.
Inventor(s): Jin YANG of San Jose CA (US) for samsung electronics co., ltd.
IPC Code(s): H01L23/64, H01L23/00, H01L23/538, H01L25/065
CPC Code(s): H01L23/642
Abstract: provided is a semiconductor package which includes: a redistribution layer including at least one insulation layer in which a plurality of wiring patterns are formed; a semiconductor chip, on the redistribution layer, connected to at least one of the plurality of wiring patterns; and a capacitor disposed in the redistribution layer.
Inventor(s): Junyeong Heo of Suwon-si (KR) for samsung electronics co., ltd., Sera Lee of Suwon-si (KR) for samsung electronics co., ltd., Yeongkwon Ko of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/00, H01L23/48
CPC Code(s): H01L24/05
Abstract: a semiconductor package includes a substrate, a dielectric structure disposed on the substrate, a via structure that penetrates the substrate and the dielectric structure, and a pad structure that is in contact with the via structure. the dielectric structure includes a first part and a second part disposed on the first part. the second part of the dielectric structure is disposed between the via structure and the pad structure. a top surface of the second part of the dielectric structure is coplanar with a top surface of the via structure.
Inventor(s): Hyuekjae Lee of Hwaseong-si (KR) for samsung electronics co., ltd., Jongho Lee of Hwaseong-si (KR) for samsung electronics co., ltd., Jihoon Kim of Cheonan-si (KR) for samsung electronics co., ltd., Taehun Kim of Asan-si (KR) for samsung electronics co., ltd., Sangcheon Park of Hwaseong-si (KR) for samsung electronics co., ltd., Jinkyeong Seol of Cheonan-si (KR) for samsung electronics co., ltd., Sanghoon Lee of Seongnam-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H01L24/06
Abstract: a semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.
Inventor(s): Jing Cheng LIN of Suwon-si (KR) for samsung electronics co., ltd., Youngkun JEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L23/498
CPC Code(s): H01L24/81
Abstract: a method of manufacturing a semiconductor package is provided. the method includes: forming a plurality of sacrificial pads on a carrier substrate and a plurality of sacrificial solder bumps on the plurality of sacrificial pads, respectively; forming a plurality of conductive pillars and a protective insulating layer on a semiconductor chip, the protective insulating layer surrounding a side surface of each of the plurality of conductive pillars; polishing the plurality of conductive pillars and the protective insulating layer to obtain a polished surface in which a surface of each of the plurality of conductive pillars is coplanar with a surface of the protective insulating layer; and bonding the plurality of conductive pillars to the plurality of sacrificial solder bumps, respectively.
Inventor(s): Jaeean LEE of Suwon-si (KR) for samsung electronics co., ltd., Dongwon KANG of Suwon-si (KR) for samsung electronics co., ltd., Changyeon SONG of Suwon-si (KR) for samsung electronics co., ltd., Sunguk LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L23/00, H01L23/31, H01L23/498
CPC Code(s): H01L24/82
Abstract: a semiconductor package includes: a first redistribution structure including a first upper connection pad and a first lower connection pad; a first semiconductor device on the first redistribution structure; a vertical connection conductor on the first redistribution structure; an encapsulant adjacent to the first semiconductor device; a second redistribution structure on the encapsulant and including a second redistribution pattern, a second insulating layer, a second upper connection pad, and a second lower connection pad; an insulating adhesive layer between the second redistribution structure and the encapsulant; and an intermediate connection terminal connecting the second lower connection pad with the vertical connection conductor, wherein the second upper connection pad is exposed by an upper opening of the second insulating layer. a cover conductive layer is on the second upper connection pad. a side surface of the intermediate connection terminal is covered with the insulating adhesive layer and the encapsulant.
20250015046. SEMICONDUCTOR PACKAGE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Seho You of Suwon-si (KR) for samsung electronics co., ltd., Kyungdon Mun of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L23/48, H01L23/522, H10B80/00
CPC Code(s): H01L25/0652
Abstract: a semiconductor package includes a package substrate including first and second wirings, a logic chip on the package substrate, electrically connected to the first wiring, and including a first wireless communication element, a chip structure on the logic chip, and including a buffer chip containing first and second through-electrodes, a first connection circuit electrically connected to the first through-electrode, and a second connection circuit electrically connected to the second through-electrode, and a plurality of memory chips stacked on the buffer chip and electrically connected to the first and second through-electrodes, a second wireless communication element within the buffer chip or between the buffer chip and the logic chip, electrically connected to the first connection circuit, and coupled to the first wireless communication element, and a plurality of conductive vertical structures between the chip structure and the package substrate and electrically connecting the second connection circuit and the second wiring.
20250015048. SEMICONDUCTOR PACKAGES_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): HYUNSOO CHUNG of Suwon-si (KR) for samsung electronics co., ltd., KWANG-SOO KIM of Suwon-si (KR) for samsung electronics co., ltd., SANG CHEON PARK of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L23/48, H10B80/00
CPC Code(s): H01L25/0657
Abstract: a semiconductor stack structure includes: a plurality of semiconductor dies vertically stacked on each other; and one or more dummy dies positioned between the plurality of semiconductor dies, wherein each of the one or more dummy dies includes: a dummy die base; a first interconnection structure positioned on a first side of the dummy die base and including a plurality of first bonding pads, wherein the first bonding pads are positioned at substantially regular intervals; and a second interconnection structure positioned on a second side of the dummy die base and including a plurality of second bonding pads, wherein the second bonding pads are positioned at substantially regular intervals.
Inventor(s): Hwanjoo Park of Suwon-si (KR) for samsung electronics co., ltd., Sunggu Kang of Suwon-si (KR) for samsung electronics co., ltd., Jae Choon Kim of Suwon-si (KR) for samsung electronics co., ltd., Taehwan Kim of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/48, H01L23/538, H10B80/00
CPC Code(s): H01L25/0657
Abstract: a semiconductor package includes a redistribution line structure that has a redistribution line layer. a first semiconductor chip is disposed above the redistribution line structure and includes a first region with a first thickness and a second region with a second thickness that is less than the first thickness. a sub-semiconductor package includes a second semiconductor chip and is disposed above the second region of the first semiconductor chip. a silicon through via penetrates the second region of the first semiconductor chip and electrically connects the sub-semiconductor package with the redistribution line structure. a sealant seals at least a portion of each of the first semiconductor chip and the sub-semiconductor package. the sub-semiconductor package is disposed within the second region of the first semiconductor chip.
Inventor(s): JUNBYEONG LEE of Suwon-si (KR) for samsung electronics co., ltd., JINMO KWON of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L25/00
CPC Code(s): H01L25/0657
Abstract: a semiconductor package includes a package substrate, a first group of semiconductor chips disposed on the package substrate and including at least two lower semiconductor chips that are sequentially stacked and are offset in a first horizontal direction, a second group of semiconductor chips stacked on the first group of semiconductor chips and including at least two upper semiconductor chips that are sequentially stacked and are offset in a direction opposite to the first horizontal direction, first bonding wires electrically connecting the chip pads of the first group of semiconductor chips to first substrate pads of the package substrate, second bonding wires electrically connecting the chip pads of the second group of semiconductor chips to second substrate pads of the package substrate and a molding member covering the first group of semiconductor chips and the second group of semiconductor chips on the package substrate.
20250015062. SEMICONDUCTOR PACKAGE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Junghoon KANG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L25/10, H01L23/00, H01L23/15, H01L23/31, H01L23/48, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L25/105
Abstract: a semiconductor package includes: a first redistribution substrate; a module structure on the first redistribution substrate; a first molding layer on the first redistribution substrate and surrounding the module structure; and a vertical connection structure on a side of the module structure, the vertical connection structure vertically extending and connected to the first redistribution substrate, wherein the module structure includes: an interposer substrate including a glass substrate, and a first semiconductor chip mounted on the interposer substrate; and a second semiconductor chip mounted on the interposer substrate.
Inventor(s): Jing Cheng Lin of Suwon-si (KR) for samsung electronics co., ltd., Youngkun Jee of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L25/10, H01L23/00, H01L23/31, H01L23/367, H01L23/48, H01L23/538, H01L25/065, H10B80/00
CPC Code(s): H01L25/105
Abstract: provided is a semiconductor package including a redistribution substrate, a first semiconductor chip on the redistribution substrate, a second semiconductor chip on the redistribution substrate and spaced apart from the first semiconductor chip in a horizontal direction, a third semiconductor chip on the second semiconductor chip, and a heat dissipation chip on the first semiconductor chip and spaced apart from the third semiconductor chip in the horizontal direction, wherein the second semiconductor chip includes a plurality of through vias passing through at least a portion of the second semiconductor chip in a vertical direction, and wherein a metal pad and an adhesive layer are between the first semiconductor chip and the heat dissipation chip.
Inventor(s): Yoon Young JEON of Suwon-si (KR) for samsung electronics co., ltd., Young Min KIM of Suwon-si (KR) for samsung electronics co., ltd., Ji Hyun LIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L25/16, H01L21/48, H01L23/00, H01L23/498, H01L23/538, H10B80/00
CPC Code(s): H01L25/16
Abstract: a semiconductor device is described, in which a multi-bridge is packaged in a substrate to improve a small form factor. the semiconductor device comprises a substrate including a first surface and a second surface, which face each other, and defining a first cavity passing through the first surface and the second surface, a first redistribution layer structure formed on the first surface of the substrate, a second redistribution layer structure formed on the second surface of the substrate, a connection terminal disposed on the second redistribution layer structure, and a multi-bridge packaged in the first cavity, including a first bridge facing the first surface and electrically connected to the first redistribution layer structure and a second bridge facing the second surface and electrically connected to the second redistribution layer structure.
20250015065. SEMICONDUCTOR PACKAGE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Myungsam KANG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L25/16, H01L23/00, H01L23/498
CPC Code(s): H01L25/162
Abstract: a semiconductor package includes a wiring structure including at least one first wiring layer and at least one first insulating layer, a semiconductor chip overlapping the wiring structure in a vertical direction, a second insulating layer overlapping the wiring structure in the vertical direction and including a cavity, an inductor in the cavity and electrically connected to the semiconductor chip, a lead-out pillar extending from one surface of the inductor facing the wiring structure and electrically connecting the inductor and the semiconductor chip, and an encapsulant encapsulating the inductor, wherein the inductor includes an insulating body and a coil portion in the insulating body, and configured to output a magnetic field in a direction, different from the vertical direction, and a region on one surface of the insulating body not overlapping the lead-out pillar is in direct contact with the encapsulant or the at least one first insulating layer.
20250015100. IMAGE SENSOR_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Eunsub Shim of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14603
Abstract: an image sensor includes a photodiode disposed in a substrate and including an n-type impurity region, wherein the n-type impurity region is doped with n-type impurities, a transfer gate (tg) structure partially buried in the substrate and disposed on the n-type impurity region, a recess disposed at an upper surface of the substrate and being spaced apart from the tg structure, a floating diffusion (fd) region disposed under the recess and doped with n-type impurities, and an impurity region disposed at a portion of the substrate between the tg structure and the recess and doped with p-type impurities. an upper surface of the fd region is lower than an upper surface of the impurity region.
20250015108. IMAGE SENSOR_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Younggu JIN of Suwon-si (KR) for samsung electronics co., ltd., Youngchan KIM of Suwon-si (KR) for samsung electronics co., ltd., Seunghyun LEE of Suwon-si (KR) for samsung electronics co., ltd., Taeun HWANG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14627
Abstract: an image sensor that includes a substrate including a first photodiode (pd) region and a second pd region adjacent to the first pd region; a first pd having a first area in the first pd region; a second pd in the second pd region, the second pd having a second area smaller than the first area; a micro-lens on the substrate and covering the first pd region; and a light splitter between the substrate and the micro-lens, the light splitter including a material having a refractive index different from a refractive index of the micro-lens. the light splitter extends from the first pd region to the second pd region.
Inventor(s): Sangeun Mun of Suwon-si (KR) for samsung electronics co., ltd., Sookyoung Roh of Suwon-si (KR) for samsung electronics co., ltd., Sungmo Ahn of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L27/146, G02B5/20, H04N23/55, H04N25/11
CPC Code(s): H01L27/14627
Abstract: an image sensor may include pixel groups arranged in a bayer pattern and a color separating lens array that separates incident light by wavelengths and concentrates the separated incident light on the pixels. the color separating lens array may include pixel corresponding groups, with each group having regions containing nanoposts in two layers. in each of the pixel corresponding groups in each of the two layers, there are a central group and a plurality of peripheral groups. the displacements of arrangement centers of the nanoposts in at least two of the peripheral groups have variations.
Inventor(s): Jeongkil SHIN of Suwon-si (KR) for samsung electronics co., ltd., Haneung KIM of Suwon-si (KR) for samsung electronics co., ltd., Jaekyu SHIM of Suwon-si (KR) for samsung electronics co., ltd., Kihuk LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14627
Abstract: according to an embodiment, an electronic device may comprise: at least one lens, an image sensor aligned along an optical axis from the at least one lens, and an optical member comprising a prism and/or mirror disposed between the at least one lens and the image sensor on the optical axis. the optical member may include a first optical member including a first surface on which light passing through the at least one lens is configured to be incident, a second surface inclined with respect to the first surface, and a third surface inclined with respect to the first surface and the second surface, and a second optical member including a fourth surface though which light is configured to exit, a fifth surface inclined with respect to the fourth surface, and a sixth surface inclined with respect to the fourth surface and the fifth surface and configured to face the third surface.
Inventor(s): Sanghoon LEE of Suwon-si (KR) for samsung electronics co., ltd., Jingyun Kim of Suwon-si (KR) for samsung electronics co., ltd., Seunghyun Lee of Suwon-si (KR) for samsung electronics co., ltd., Soojin Hong of Suown-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1463
Abstract: an image sensor according to an embodiment includes a substrate having first and second surfaces facing each other, separated by a deep trench, and including a plurality of pixel regions; a plurality of photoelectric conversion regions disposed in the plurality of pixel regions; a blocking region disposed in the plurality of pixel regions; and a plurality of color filters and a plurality of micro lenses disposed on the second surface of the substrate. the blocking region is disposed adjacent to the second surface of the substrate, the blocking region includes a first element of a first type, and the plurality of photoelectric conversion regions include a second element of a second type different from the first type. the concentration of the first element on the second surface of the substrate in the blocking region is about 1e16/cmto about 1e18/cm.
Inventor(s): Changju Moon of Suwon-si (KR) for samsung electronics co., ltd., Donggwan Shin of Suwon-si (KR) for samsung electronics co., ltd., Yonghee Park of Suwon-si (KR) for samsung electronics co., ltd., Myunggil Kang of Suwon-si (KR) for samsung electronics co., ltd., Jeongho Yoo of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L29/08, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/0847
Abstract: a semiconductor device includes an active region that extends on the substrate in a first direction; a plurality of semiconductor layers disposed on the active region and that are spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a gate structure disposed on the substrate and that crosses the active region and the plurality of semiconductor layers, surrounds each of the plurality of semiconductor layers, and extends in a second direction; a source/drain region disposed on at least one side of the gate structure and in contact with a portion of the plurality of semiconductor layers; and an epitaxial layer that is spaced apart from an uppermost semiconductor layer, is disposed below the source/drain region and between the active region and the source/drain region, and is in contact with at least a portion of the side surfaces of the lowermost semiconductor layer.
Inventor(s): Hwayeong Lee of Suwon-si (KR) for samsung electronics co., ltd., Seulji Song of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L29/08, H01L29/24, H01L29/423, H01L29/78, H10B12/00
CPC Code(s): H01L29/0847
Abstract: a vertical channel transistor includes a substrate having a bit line thereon, and a vertical channel layer including a first metal oxide, on the bit line. a lower insertion layer is provided, which extends between the bit line and a first end of the channel layer, and includes a second metal oxide having a greater bonding energy relative to the first metal oxide. a lower source/drain region is provided, which extends between the first end of the channel layer and the lower insertion layer, and includes a first metal dopant that is a reduced form of the first metal oxide. an upper source/drain region is provided, which is electrically connected to a second end of the channel layer, and includes the first metal dopant. an insulated gate line is provided on the channel layer.
Inventor(s): Beomjin Park of Suwon-si (KR) for samsung electronics co., ltd., Myung Gil Kang of Suwon-si (KR) for samsung electronics co., ltd., Dongwon Kim of Suwon-si (KR) for samsung electronics co., ltd., Younggwon Kim of Suwon-si (KR) for samsung electronics co., ltd., Jongsu Kim of Suwon-si (KR) for samsung electronics co., ltd., Hyumin Yoo of Suwon-si (KR) for samsung electronics co., ltd., Soojin Jeong of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L29/423, H01L27/088, H01L29/06, H01L29/417, H01L29/775, H01L29/786
CPC Code(s): H01L29/42364
Abstract: the present disclosure relates to semiconductor devices and their fabrication methods. an example semiconductor device comprises a substrate including an active pattern, a channel pattern including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, an inner gate electrode between two neighboring semiconductor patterns, an inner gate dielectric layer, and an inner high-k dielectric layer between the inner gate electrode and the inner gate dielectric layer. the inner gate dielectric layer includes an upper dielectric layer, a lower dielectric layer, and an inner spacer. a first thickness of the inner spacer is greater than a second thickness of the upper or lower dielectric layer. the first thickness is greater than a third thickness of the inner high-k dielectric layer.
Inventor(s): Siyeong Yang of SUWON-SI (KR) for samsung electronics co., ltd., Yuyeon Kim of SUWON-SI (KR) for samsung electronics co., ltd., Jaeho Jung of SUWON-SI (KR) for samsung electronics co., ltd.
IPC Code(s): H01L29/78, H01L25/065, H01L29/66, H10B41/27, H10B43/27, H10B80/00
CPC Code(s): H01L29/7827
Abstract: a semiconductor device includes a gate stacking structure that includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked with each other, and a plurality of channel structures that penetrate the gate stacking structure. the plurality of channel structures include a first channel structure that includes a first channel layer, and a plurality of second channel structures adjacent to the first channel structure and that include a plurality of second channel layers. the first channel layer in the first channel structure and the plurality of second channel layers in the plurality of second channel structures have a same crystal orientation.
Inventor(s): Hagyoul BAE of Hanam-si (KR) for samsung electronics co., ltd., Seunggeol NAM of Suwon-si (KR) for samsung electronics co., ltd., Jinseong HEO of Seoul (KR) for samsung electronics co., ltd., Sanghyun JO of Suwon-si (KR) for samsung electronics co., ltd., Dukhyun CHOE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01L29/78, H01L21/66, H01L29/06, H01L29/423, H01L29/51, H01L29/66, H01L29/786
CPC Code(s): H01L29/78391
Abstract: provided are a ferroelectric semiconductor device and a method of extracting a defect density of the same. a ferroelectric electronic device includes a first layer, an insulating layer including a ferroelectric layer and a first interface that is adjacent to the first layer, and an upper electrode over the insulating layer, wherein the insulating layer has a bulk defect density of 10cmevor more and an interface defect density of 10cmevor more.
Inventor(s): Shihyun KIM of Suwon-si (KR) for samsung electronics co., ltd., Sihoon YOUM of Suwon-si (KR) for samsung electronics co., ltd., Juneyoung HUR of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01M50/105, H01M10/42, H01M50/184, H01M50/186, H02H7/18
CPC Code(s): H01M50/105
Abstract: an electronic device according to an embodiment of the disclosure may include a housing. the electronic device may include a battery disposed inside the housing and configured to supply power to the electronic device. the battery may include an electrode assembly. the battery may include an upper pouch and a lower pouch disposed to accommodate the electrode assembly. the battery may include a sealing part formed at edges of the upper pouch and the lower pouch to seal the electrode assembly. the lower pouch may include a first cup recessed downwardly and configured to accommodate at least a portion of the electrode assembly. the first cup may have a front side, a rear side opposite to the front side, and a lateral side connecting the front side and the rear side. the sealing part may include a front sealing part extending from the front side of the first cup and disposed at a lower position than an upper end of the rear side of the first cup.
Inventor(s): Jungho CHU of Suwon-si (KR) for samsung electronics co., ltd., Shihyun Kim of Suwon-si (KR) for samsung electronics co., ltd., Seonyoung Park of Suwon-si (KR) for samsung electronics co., ltd., Kiyoun Jang of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01M50/536, H01M10/04, H01M50/247, H01M50/528
CPC Code(s): H01M50/536
Abstract: a battery may include: a negative electrodes including a negative electrode including a first tab portion, and a negative electrode current collector including a first recess; positive electrodes arranged alternately with the negative electrodes, and including a positive electrode including a second tab portion, and a positive electrode current collector including a second recess; a separator between two adjacent electrodes among the negative electrodes and the positive electrodes; a first lead tab in the first recess; and a second lead tab in the second recess, wherein the first tab portion is welded to the first lead tab so as to form a first welding portion located in the first recess, and the second tab portion is welded to the second lead tab so as to form a second welding portion located in the second recess.
Inventor(s): Minkyung LEE of Suwon-si (KR) for samsung electronics co., ltd., Woosuk KANG of Suwon-si (KR) for samsung electronics co., ltd., Yunsik KIM of Suwon-si (KR) for samsung electronics co., ltd., Mincheol SEO of Suwon-si (KR) for samsung electronics co., ltd., Kyungmoon SEOL of Suwon-si (KR) for samsung electronics co., ltd., Donghun SHIN of Suwon-si (KR) for samsung electronics co., ltd., Changha YU of Suwon-si (KR) for samsung electronics co., ltd., Gyubok PARK of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01Q1/22, H01Q1/48, H01Q9/04, H01Q9/40
CPC Code(s): H01Q1/22
Abstract: an electronic device according to an embodiment may comprise: a housing, including a first surface, a second surface facing the first surface at a distance, and a third surface disposed between the first surface and the second surface; at least one processor, comprising processing circuitry, disposed on the first surface of the housing; a communication circuit connected to at least one processor; and a printed circuit board (pcb) including an electronic component connected to at least one processor independently of the communication circuit and disposed on a surface thereof facing the third surface. the pcb can include a conductive pattern formed on the surface of the pcb facing the third surface and connected to a power supply line extending from the communication circuit. the pcb of the electronic device may be disposed to be adjacent to the third surface.
Inventor(s): Sungkoo PARK of Suwon-si (KR) for samsung electronics co., ltd., Hyungjoo LEE of Suwon-si (KR) for samsung electronics co., ltd., Shinho YOON of Suwon-si (KR) for samsung electronics co., ltd., Himchan YUN of Suwon-si (KR) for samsung electronics co., ltd., Soonho HWANG of Suwon-si (KR) for samsung electronics co., ltd., Jaebong CHUN of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01Q1/22, G06F1/16, H01Q1/38, H05K1/18
CPC Code(s): H01Q1/2266
Abstract: an electronic device is provided. the electronic device includes a foldable housing including, a hinge structure, a first housing structure including a first surface, a second surface, and a first side member, wherein the first side member encloses at least a portion of a space between the first surface and the second surface and includes a first conductive portion, a first non-conductive portion, and a second conductive portion, and a second housing structure including a third surface, a fourth surface, and a second side member, a printed circuit board, at least one wireless communication circuit including a first electrical path and a second electrical path, a first variable element including a first terminal, a second terminal, and a third terminal, and a second variable element including a fourth terminal, a fifth terminal, and a sixth terminal.
Inventor(s): Jiho SHIN of Suwon-si (KR) for samsung electronics co., ltd., Yi YANG of Suwon-si (KR) for samsung electronics co., ltd., Moonseok KANG of Suwon-si (KR) for samsung electronics co., ltd., Hyunchul KIM of Suwon-si (KR) for samsung electronics co., ltd., Sukgi HONG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H01Q21/28, H04L25/02
CPC Code(s): H01Q21/28
Abstract: an electronic device according to various embodiments comprises: a first antenna; a second antenna; a third antenna; a communication module comprising communication circuitry connected to the antennas and including a first receive port (rx) and a second rx; and at least one processor, comprising processing circuitry, wherein the communication module is configured to analyze a pattern of signals, based on signals received from the first rx and the second rx, and transmit information related to the analyzed pattern of signals to at least one processor, and at least one processor, individually and/or collectively, may be configured to perform a designated operation based on the information related to the pattern of signals from the communication module.
20250015760. VOLTAGE-CONTROLLED OSCILLATOR_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Dongsoo LEE of Suwon-si (KR) for samsung electronics co., ltd., Daehoon KWON of Suwon-si (KR) for samsung electronics co., ltd., Dongin KIM of Suwon-si (KR) for samsung electronics co., ltd., Chunsuk KIM of Suwon-si (KR) for samsung electronics co., ltd., Yiju ROH of Suwon-si (KR) for samsung electronics co., ltd., Inhyeok PARK of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H03B5/12
CPC Code(s): H03B5/1212
Abstract: disclosed are a voltage-controlled oscillator and an electronic device comprising same. a voltage-controlled oscillator according to one embodiment includes an lc tank and one or more gm cells connected to the lc tank. the lc tank includes a variable capacitor and a switched inductor connected in parallel to the variable capacitor. the gm cells include one or more decoupling capacitors inserted between the lc tank and one or more drain nodes of the gm cells.
Inventor(s): Peshal Nayak of Plano TX (US) for samsung electronics co., ltd., Boon Loong Ng of Plano TX (US) for samsung electronics co., ltd., Rubayet Shafin of Allen TX (US) for samsung electronics co., ltd., Vishnu Vardhan Ratnam of Plano TX (US) for samsung electronics co., ltd., Yue Qi of Plano TX (US) for samsung electronics co., ltd., Elliot Jen of Taipei City (TW) for samsung electronics co., ltd.
IPC Code(s): H04L5/00, H04L47/28, H04W84/12
CPC Code(s): H04L5/0078
Abstract: a first device associated with a second device in a wireless network, the first device comprising at least one station (sta) affiliated with the first device and a processor coupled to the at least one sta, the processor configured to transmit a request frame to the second device, wherein the request frame requests permission from the second device in order for the first device to provide to the second device timing information for packets transmitted to the second device, receive a response frame from the second device indicating acceptance to receive the timing information from the first device, and transmit the timing information to the second device.
Inventor(s): Youngsik Moon of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04L9/00, G06F21/62
CPC Code(s): H04L9/008
Abstract: provided are a homomorphic encryption arithmetic device and an operating method thereof. provided is an operating method of a homomorphic encryption arithmetic device, the operating method including receiving, from a client, a public key and an input identification value, generating an authenticator on the basis of a result of comparing an input identification value with a plurality of user identification values stored in a first database, obtaining a search result value by searching a second database on the basis of an input query, generating an arithmetic result value by performing an operation by using the search result value and the authenticator, and transmitting the arithmetic result value to the client.
Inventor(s): Juhyeon PAENG of Suwon-si (KR) for samsung electronics co., ltd., Yesol LEE of Suwon-si (KR) for samsung electronics co., ltd., Kyungjae KIM of Suwon-si (KR) for samsung electronics co., ltd., Hyelim PARK of Suwon-si (KR) for samsung electronics co., ltd., Soohyun SUNG of Suwon-si (KR) for samsung electronics co., ltd., Byeongcheol YOON of Suwon-si (KR) for samsung electronics co., ltd., Myoungsoo JANG of Suwon-si (KR) for samsung electronics co., ltd., Chihong CHO of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04L12/28
CPC Code(s): H04L12/282
Abstract: a home appliance control method is provided. the home appliance control method includes, when a user is detected in a first space among a plurality of spaces within a home, determining whether the user is using the first space, based on a first usage time for which the user stays in the first space, when it is determined that the detected user is using the first space, determining a second space predicted to be used next by the user among the plurality of spaces within the home, based on user routine information including a spatial movement prediction path of the user predicted in advance for the plurality of spaces within the home, and controlling an operation of at least one home appliance of the second space.
Inventor(s): Juhyeon PAENG of Suwon-si (KR) for samsung electronics co., ltd., Byeongcheol YOON of Suwon-si (KR) for samsung electronics co., ltd., Younghak KONG of Suwon-si (KR) for samsung electronics co., ltd., Hyelim PARK of Suwon-si (KR) for samsung electronics co., ltd., Soohyun SUNG of Suwon-si (KR) for samsung electronics co., ltd., Yesol LEE of Suwon-si (KR) for samsung electronics co., ltd., Myoungsoo JANG of Suwon-si (KR) for samsung electronics co., ltd., Chihong CHO of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04L12/28, A61B5/00, A61B5/01, A61B5/0205, A61B5/024, A61B5/08
CPC Code(s): H04L12/282
Abstract: a method of controlling a temperature adjusting device and a server device for performing the method are provided. the method includes obtaining user sleep information comprising at least one of a body temperature value, a heart rate value, or a respiration value of a user, determining a current sleep stage of the user based on the user sleep information, determining whether the body temperature value exceeds a body temperature range corresponding to the current sleep stage, and controlling at least one temperature adjusting device based on a determination that the body temperature value exceeds the body temperature range.
Inventor(s): Jinho Kim of Seoul (KR) for samsung electronics co., ltd., Jungmin Park of Seoul (KR) for samsung electronics co., ltd.
IPC Code(s): H04L27/26, H04L5/00
CPC Code(s): H04L27/2613
Abstract: a user terminal supporting carrier aggregation (ca) and an operating method thereof are provided. the operating method includes receiving indication information regarding a phase tracking reference signal (ptrs) component carrier (cc) group from a base station; determining whether a phase noise characteristic of the user terminal is the same with respect to ccs included in the ptrs cc group, based at least in part on the indication information; requesting the base station to transmit at least one ptrs using at least one cc included in the ptrs cc group; and receiving the at least one ptrs from the base station using the at least one cc.
Inventor(s): LUKASZ WOJCIECHOWSKI of Warsaw (PL) for samsung electronics co., ltd.
IPC Code(s): H04L47/125, H04L45/74, H04L47/24
CPC Code(s): H04L47/125
Abstract: a method for processing a packet by an electronic device is provided. the method includes identifying a first packet including a first part, a second part, and a cyclic redundancy check (crc) part, obtaining a second value by modifying a first value of the first part of the first packet, obtaining a third value by performing an exclusive or (xor) operation on the first value and the obtained second value, obtaining a fourth value which is a crc value for the obtained third value, obtaining a fifth value which is a crc value corresponding to concatenation of the third value and a number of zeros corresponding to a length of the second part of the first packet, based on the length of the second part of the first packet and the obtained fourth value, obtaining a sixth value by performing the xor operation on a value of the crc part of the first packet and the obtained fifth value, and generating a second packet including a first part having the second value, a second part which is the same as the second part of the first packet, and a crc part having the sixth value.
Inventor(s): Chandrashekhar S Byadgi of Bengaluru (IN) for samsung electronics co., ltd., Kartik Anand of Bengaluru (IN) for samsung electronics co., ltd., Praveen Naik S of Bengaluru (IN) for samsung electronics co., ltd., Ramesh Babu Venkat Dabbiru of Bengaluru (IN) for samsung electronics co., ltd., Siva Prasad Gundur of Bengaluru (IN) for samsung electronics co., ltd., Prasenjit Chakraborty of Bengaluru (IN) for samsung electronics co., ltd., Eric Ho Ching Yip of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04L67/141
CPC Code(s): H04L67/141
Abstract: an example method for communicating ai data from a sender device to a receiver device in a computing environment may include generating protocol instances of ai data; generating ai metadata description based on ai model information; sending a request comprising the ai metadata description to a receiver device for establishing a session; establishing a session by receiving a response from the receiver device based on the request; sending the ai data associated with the ai metadata description, to the receiver device based on the established session. the receiver device may receive the request and determine the compatibility of the metadata description, generate and send a response, followed by receiving the ai data associated with the ai metadata description.
Inventor(s): Seho CHANG of Suwon-si (KR) for samsung electronics co., ltd., Hyerim BAE of Suwon-si (KR) for samsung electronics co., ltd., Byounguk YOON of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04M1/02, H04M1/72436
CPC Code(s): H04M1/0243
Abstract: according to an embodiment, at least one processor of a multi-foldable electronic device, individually and/or collectively, is configured to control the electronic device to: display an execution screen of a first application on a first region, a second region and a third region of a flexible display; identify any of a second housing and a third housing being folded with respect to a first housing; display an execution screen of a first application on the second region and an execution screen of a second application on the first region and the third region, based on identifying that the second housing is folded with respect to the first housing; and display an execution screen of the first application on the first region and the second region and an execution screen of the second application on the third region, based on identifying that the third housing is folded with respect to the first housing.
Inventor(s): Il-koo KIM of Osan-si (KR) for samsung electronics co., ltd., Young-o Park of Seoul (KR) for samsung electronics co., ltd.
IPC Code(s): H04N19/136, H04N19/124, H04N19/172, H04N19/174, H04N19/463, H04N19/58, H04N19/70, H04N19/86
CPC Code(s): H04N19/136
Abstract: a method of determining a reference picture set (rps), which is a set of reference pictures used in predictive decoding of a current picture that is to be decoded includes: obtaining a flag indicating whether the rps is determined based on poc values of the current picture and a previous picture or whether the rps is determined based on an index of a reference rps, which is an identification value of the reference rps that is one of pre-defined rpss and is referred to in determining the rps, and a delta rps that is a difference value between a poc vale of a reference picture included in the reference rps and a poc value of a reference picture included in the rps; and determining the rps according to a value of the flag.
Inventor(s): Il-koo KIM of Osan-si (KR) for samsung electronics co., ltd., Young-o PARK of Seoul (KR) for samsung electronics co., ltd.
IPC Code(s): H04N19/136, H04N19/124, H04N19/172, H04N19/174, H04N19/463, H04N19/58, H04N19/70, H04N19/86
CPC Code(s): H04N19/136
Abstract: a method of determining a reference picture set (rps), which is a set of reference pictures used in predictive decoding of a current picture that is to be decoded includes: obtaining a flag indicating whether the rps is determined based on poc values of the current picture and a previous picture or whether the rps is determined based on an index of a reference rps, which is an identification value of the reference rps that is one of pre-defined rpss and is referred to in determining the rps, and a delta rps that is a difference value between a poc vale of a reference picture included in the reference rps and a poc value of a reference picture included in the rps; and determining the rps according to a value of the flag.
Inventor(s): Jin-Young LEE of Suwon-si (KR) for samsung electronics co., ltd., Yin-Ji PIAO of Yongin-si (KR) for samsung electronics co., ltd., Woong-il CHOI of Osan-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04N19/513, H04N19/139, H04N19/176
CPC Code(s): H04N19/513
Abstract: a method of decoding a motion vector includes: determining at least one prediction motion vector (pmv) candidate block used to determine a pmv of a current block; determining an availability of a motion vector of the at least one pmv candidate block; when there is a pmv candidate block determined to be unavailable, determining the pmv of the current block by using a default motion vector (mv); and obtaining a motion vector of the current block based on the determined pmv.
Inventor(s): Anant BAIJAL of Suwon-si (KR) for samsung electronics co., ltd., Seungki CHO of Suwon-si (KR) for samsung electronics co., ltd., Daeeun HYUN of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04N21/4788, H04N7/15, H04N21/431, H04N21/45
CPC Code(s): H04N21/4788
Abstract: a display device includes a display, memory storing instructions; and at least one processor to control the display. the display device displays a virtual world image including a virtual display device. based on the display device being in a first mode, the display device displays a first virtual world image including the virtual display device where content is displayed, and based on the first mode being changed to a second mode, the display device displays at least a portion of an area excluding the virtual display device in the first virtual world image through a first area of the display, and displays the content through a second area of the display
Inventor(s): Beomsoo KIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04N23/55, H04N23/51
CPC Code(s): H04N23/55
Abstract: a camera module is provided. the camera module includes a lens having an optical axis, a first structure configured to carry the lens along the optical axis, a second structure, wherein the first structure is configured to move relative to the second structure, an extension extending from any one of the first structure or the second structure, a guide tunnel positioned in the other one of the first structure or the second structure and configured to guide the extension, and a damper configured to damp a movement of the extension in a direction of the optical axis.
Inventor(s): Jaeheung Park of Suwon-si (KR) for samsung electronics co., ltd., Bongchan Kim of Suwon-si (KR) for samsung electronics co., ltd., Hyungjin Rho of Suwon-si (KR) for samsung electronics co., ltd., Jaehyoung Park of Suwon-si (KR) for samsung electronics co., ltd., Kwangseok Byon of Suwon-si (KR) for samsung electronics co., ltd., Hyosang An of Suwon-si (KR) for samsung electronics co., ltd., Jonghoon Won of Suwon-si (KR) for samsung electronics co., ltd., Jiyeon Jo of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04N23/68, H04N23/52, H04N23/55, H04N23/57
CPC Code(s): H04N23/687
Abstract: disclosed are a camera module () including a shock mitigation member () and an electronic device () including the camera module (). the camera module () according to an embodiment may include a frame (), at least one shock mitigation member (), and a lens assembly (). provided is a structure for preventing or at least partially absorbing a shock between the lens assembly () and another component while coming into contact with a fixing portion as the lens assembly () moves. in addition, various other embodiments identified through the specification are possible.
Inventor(s): Jongmin YOON of Suwon-si (KR) for samsung electronics co., ltd., Hyunseung YOON of Suwon-si (KR) for samsung electronics co., ltd., Byounghee LEE of Suwon-si (KR) for samsung electronics co., ltd., Kwangtai KIM of Suwon-si (KR) for samsung electronics co., ltd., Seungnyun KIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04N23/71, G06F3/01, G06V10/25, G06V10/60
CPC Code(s): H04N23/71
Abstract: a wearable device is provided. the wearable device identifies a region of interest (roi) in the first frame outputted through a display based on a user input. a camera region included in the first frame corresponds to at least partial region of a first camera image obtained through a camera at a first time point. the wearable device controls the image signal processor to process the second camera image obtained at the second time point after the first time point by a first processing scheme based on the region of interest (roi) overlapping the camera region. the wearable device controls the image signal processor to process the second camera image by a second processing scheme that is distinct from the first processing scheme, based on the region of interest (roi) being outside of the camera region. the wearable device displays, through the display, a second frame including the camera region corresponding to at least partial region of the processed second camera image.
Inventor(s): Ashish Kuma SINGH of Bengalaru (IN) for samsung electronics co., ltd., Abhijit DEY of Bengalaru (IN) for samsung electronics co., ltd., Akshit AGARWAL of Bengalaru (IN) for samsung electronics co., ltd., Sanjay Narasimha MURTHY of Bengalaru (IN) for samsung electronics co., ltd., Amit Kumar SONI of Bengalaru (IN) for samsung electronics co., ltd., Rohan Claude D'SOUZA of Bengalaru (IN) for samsung electronics co., ltd.
IPC Code(s): H04N23/951, G06T7/292, H04N23/68, H04N23/86
CPC Code(s): H04N23/951
Abstract: the present subject matter refers to a controlling method of an electronic apparatus for long exposure photography in a multi-camera device. the method includes receiving first image frames at a first frame rate from a first camera of the multi-camera device, detecting a presence of at least one moving object in each of the first image frames, based on the detection of the at least one moving object in each of the first image frames, utilizing a second camera for receiving second image frames at a second frame rate, performing a motion analysis on each of the first image frames for selection of one or more frames among the second image frames, based on the one or more frames being selected, identifying motion gaps in each of subsequent frames among the selected one or more frames, based on the motion gaps being identified, generating one or more in-place frames, and generating a motion dramatizer image based on the one or more in-place frames.
Inventor(s): JUNG BIN YUN of HWASEONG-SI (KR) for samsung electronics co., ltd., KYUNGHO LEE of SUWON-SI (KR) for samsung electronics co., ltd.
IPC Code(s): H04N25/704, H04N25/44, H04N25/766, H04N25/778
CPC Code(s): H04N25/704
Abstract: an electronic device includes an image sensor that generates image data, and an image processor that processes the image data. the image sensor includes a pixel array including pixels repeatedly disposed along a row direction and a column direction. each of pixels belonging to a first row of rows of the pixel array includes sub-pixels each connected to one of a first transmission metal line, a second transmission metal line, and a third transmission metal line. in response to signals respectively applied to the first to third transmission metal lines, at least a part of charges integrated at the sub-pixels of the pixels belonging to the first row from among the pixels is diffused to corresponding floating diffusion areas.
20250016498. LOW NOISE PORT TUBE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Andri Bezzola of La Canada CA (US) for samsung electronics co., ltd., Allan Devantier of Santa Paula CA (US) for samsung electronics co., ltd.
IPC Code(s): H04R1/30, G06F30/20
CPC Code(s): H04R1/30
Abstract: one embodiment provides a method that includes optimizing a shape for a port tube of a speaker device by varying a portion of multiple initial port tube design parameters and iteratively repeating an execution of a simulation computing process that simulates shear measure until the execution of the simulation computing process minimizes the simulated shear measure and outputs a final port tube design for an improved port tube having an optimized central portion and an optimized flare shape of at least one flared exit based on multiple final port tube design parameters for an improved shape for the port tube that maximally delays an onset of turbulence and flow separation for improved low frequency output for the speaker device. the improved port tube is generated using the multiple final port tube design parameters.
Inventor(s): Seonmi KIM of Suwon-Si (KR) for samsung electronics co., ltd., Sangeun Kim of Suwon-Si (KR) for samsung electronics co., ltd., Hangil Moon of Suwon-Si (KR) for samsung electronics co., ltd., Kyoungho Bang of Suwon-Si (KR) for samsung electronics co., ltd., Soonho Baek of Suwon-Si (KR) for samsung electronics co., ltd., Jaemo Yang of Suwon-Si (KR) for samsung electronics co., ltd., Junwoo Cha of Suwon-Si (KR) for samsung electronics co., ltd.
IPC Code(s): H04R3/00, G06F1/08, G06F1/3212, H04M9/08
CPC Code(s): H04R3/005
Abstract: an electronic device, includes: a sensor; a plurality of microphones; one or more processors; and memory storing instructions that, when executed by the one or more processors, cause the electronic device to: obtain a first sound signal through at least one of the plurality of microphones; obtain a second sound signal through at least one of a plurality of axes of the sensor; identify a noise level from among a plurality of noise levels based on the first sound signal and the second sound signal; control one or more of the plurality of microphones to be turned on or off based on the noise level; and control one or more of the plurality of axes to be turned on or off based on the noise level.
Inventor(s): Ashok Kumar NAYAK of Bangalore (IN) for samsung electronics co., ltd., Lalith KUMAR of Bangalore (IN) for samsung electronics co., ltd., Dongyeon KIM of Suwon-si (KR) for samsung electronics co., ltd., Narendranath Durga TANGUDU of Bangalore (IN) for samsung electronics co., ltd.
IPC Code(s): H04W12/06, H04W76/10, H04W76/30
CPC Code(s): H04W12/06
Abstract: embodiments herein disclose a method and device for performing secondary re-authentication for a ma-pdu session in a wireless communication system. the method for performing authentication for a multi-access packet data unit (ma-pdu) session by a session management function+packet data network (pdn) gateway control plane function (smf+pgw-c) in a wireless communication network is provided, the method comprises performing a procedure for secondary re-authentication of the ma-pdu session for a user equipment (ue) by selecting one of a first access type or a second access type in case that the smf+pgw-c receives a re-authentication request from a data network-authentication, authorization, and accounting (dn-aaa) server, retrying a procedure for the secondary re-authentication of the ma-pdu session for the second access type in case that the smf+pgw-c receives a failure indication for the secondary re-authentication that the ue is not reachable in the first access type, and retrying a procedure for the secondary re-authentication of the ma-pdu session for the first access type in case that the smf+pgw-c receives a failure indication of the secondary re-authentication that the ue is not reachable in the second access type.
Inventor(s): Mahmoud WATFA of Staines (GB) for samsung electronics co., ltd., Mehrdad SHARIAT of Staines (GB) for samsung electronics co., ltd.
IPC Code(s): H04W28/02, H04W28/24, H04W72/23, H04W72/53, H04W72/542, H04W76/15
CPC Code(s): H04W28/0268
Abstract: a method for supporting end-to-end (e2e) quality of service (qos) for uplink (ul) communication between a user equipment (ue) and a network via a relay node, the method performed by the relay node, are provided. the method includes receiving, from the network, a downlink (dl) packet for the ue, wherein the dl packet includes a value of a first indicator of a qos flow on a first link between the relay node and the network, and creating or updating a qos rule, wherein the qos rule is derived based on the value of the first indicator, and optionally wherein the created or updated qos rule corresponds to the ue or to a qos flow on a second link with the ue.
Inventor(s): Deepanshu GAUTAM of Bangalore (IN) for samsung electronics co., ltd., Nishant GUPTA of Bangalore (IN) for samsung electronics co., ltd.
IPC Code(s): H04W28/26, H04L41/0806, H04W4/50
CPC Code(s): H04W28/26
Abstract: various embodiments of the present disclosure disclose method and system for intent driven deployment and management of communication service at the 3gpp network edge. the principal object of the embodiments herein is to disclose methods and systems for runtime deployment and management of communication service instance(s) at the edge of the 3gpp network. another object of the embodiment herein is to provide mechanism by which a csi can be targeted at a particular location for better market penetration. another object of the embodiment herein is to provide mechanism by which a csi can be deployed with the availability criteria governing when (given time stamp) the service will be available. another object of the embodiment herein is to ease deployment of csi at the edge of the network creating new business opportunities for both service and edge provider.
Inventor(s): Aby Kanneath ABRAHAM of Bangalor (IN) for samsung electronics co., ltd., Vinay Kumar SHRIVASTAVA of Bangalor (IN) for samsung electronics co., ltd., Sriganesh RAJENDRAN of Bangalor (IN) for samsung electronics co., ltd.
IPC Code(s): H04W36/08, H04W36/00
CPC Code(s): H04W36/08
Abstract: the disclosure relates to a 5g or 6g communication system for supporting a higher data transmission rate. embodiments herein are to provide a method and system for handling lower triggered mobility (ltm) of a base station. the method includes determining whether to configure lower layer triggered mobility (ltm) for a master cell group (mcg); determining whether to configure the ltm for a secondary cell group (scg); transmitting, to a user equipment (ue), a configuration message including at least one of first ltm configuration information for the mcg and second ltm configuration information for the scg, wherein the configuration message includes information about at least one channel state information (csi) resource for configuring at least one candidate cell for the ltm.
Inventor(s): Kisuk KWEON of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04W48/18, H04M15/00, H04W76/10
CPC Code(s): H04W48/18
Abstract: the disclosure relates to a fifth generation (5g) or sixth generation (6g) communication system for supporting a higher data transmission rate. a method performed by a session management function (smf) in a wireless communication system is provided. the method includes receiving, from a united data management (udm), a list of user plane function (upf) functionality components, selecting a upf based on the list of upf functionality components, and transmitting, to the selected upf, a session establishment or modification request message.
Inventor(s): Ashok Kumar NAYAK of Bangalore (IN) for samsung electronics co., ltd., Lalith KUMAR of Bangalore (IN) for samsung electronics co., ltd., Danish Ehsan HASHMI of Bangalore (IN) for samsung electronics co., ltd., Sangjun MOON of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04W48/18, H04W8/22, H04W60/04
CPC Code(s): H04W48/18
Abstract: the disclosure relates to a 5g or 6g communication system for supporting a higher data transmission rate. a method for handling a local area data network (ladn) service area in a wireless network is provided. the method performed by an access and mobility management function (amf) entity in a wireless communication system includes receiving, from a user equipment (ue), capability information indicating that the ue supports a local area data network (ladn) per data network name (dnn) and single network slice selection assistance information (s-nssai), identifying an ladn service area for a dnn and an s-nssai, and transmitting, to the ue, information on the dnn, information on the s-nssai, and information on the ladn service area.
Inventor(s): Kundan TIWARI of Bangalore (IN) for samsung electronics co., ltd., Rajavelsamy RAJADURAI of Bangalore (IN) for samsung electronics co., ltd., Hoyeon LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04W48/18, H04W8/02, H04W36/06, H04W48/16, H04W60/04, H04W76/11
CPC Code(s): H04W48/18
Abstract: the present disclosure relates to a communication method and system for converging a 5th-generation (5g) communication system for supporting higher data rates beyond a 4th-generation (4g) system with a technology for internet of things (iot). the present disclosure may be applied to intelligent services based on the 5g communication technology and the iot-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. embodiments disclose a method and system for handling a network slice specific authentication and authorization (nssaa) process in a wireless network system.
20250016680. TDLS OPERATION WITH BROADCAST TWT_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Rubayet Shafin of Allen TX (US) for samsung electronics co., ltd., Elliot Jen of Taipei City (TW) for samsung electronics co., ltd., Yue Qi of Plano TX (US) for samsung electronics co., ltd., Boon Loong Ng of Plano TX (US) for samsung electronics co., ltd., Peshal Nayak of Plano TX (US) for samsung electronics co., ltd., Vishnu Vardhan Ratnam of Plano TX (US) for samsung electronics co., ltd.
IPC Code(s): H04W52/02, H04W72/30, H04W76/14, H04W76/40, H04W84/12
CPC Code(s): H04W52/0235
Abstract: a first tunneled direct-link setup (tdls) peer station (sta) comprises a transceiver configured to transmit and receive signals and a processor operably coupled to the transceiver. the processor is configured to transmit a tdls broadcast twt request frame to a second tdls peer sta. the processor is configured to receive a tdls broadcast twt response frame in response to the tdls broadcast twt request frame. the processor is configured to transmit one or more frames to the second tdls peer sta over a tdls direct link during a target wake time (twt) service period (sp) corresponding to a broadcast twt schedule. the first tdls peer sta is a member of the broadcast twt schedule.
20250016739. DEMAND PAGING_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Anil Agiwal of Allen TX (US) for samsung electronics co., ltd., Shiyang Leng of Allen TX (US) for samsung electronics co., ltd., Kyeongin Jeong of Allen TX (US) for samsung electronics co., ltd.
IPC Code(s): H04W68/02, H04W52/02
CPC Code(s): H04W68/02
Abstract: a user equipment (ue) includes a transceiver configured to receive, from a base station (bs), a signal. the ue further includes a processor operably coupled to the transceiver. the processor is configured to generate, based on the received signal, a paging request. the transceiver is further configured to transmit the paging request, and receive, based on the paging request, a paging.
Inventor(s): Liang HU of San Diego CA (US) for samsung electronics co., ltd., Philippe Jean Marc Michel SARTORI of Naperville IL (US) for samsung electronics co., ltd., Jung Hyun BAE of San Diego CA (US) for samsung electronics co., ltd.
IPC Code(s): H04W72/0446, H04W72/0453, H04W72/1268, H04W72/231, H04W72/25, H04W74/0833
CPC Code(s): H04W72/0446
Abstract: methods and devices of a wireless system are provided. a user equipment (ue) receives a first configuration defining a first set of time domain resources for radar sensing. the first configuration includes at least one of a frame structure comprising radar sensing slots or a slot structure comprising radar sensing symbols. the ue performs radar sensing within the first set of time domain resources and first frequency domain resources. the first set of time domain resources at least partially overlap time domain resources for communication based on one or more different beams, spatial filters, or spatial angles. the first frequency domain resources at least partially overlap second frequency domain resources for communication based on one or more different beams, spatial filters, or spatial angles.
Inventor(s): Youngwook Son of Suwon-si (KR) for samsung electronics co., ltd., Hyeonjun Kim of Suwon-si (KR) for samsung electronics co., ltd., Jung Woon Lee of Suwon-si (KR) for samsung electronics co., ltd., Hyunbae Jeon of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04W72/0453
CPC Code(s): H04W72/0453
Abstract: an operating method of a receiver includes detecting a signal received from a transmitter at a plurality of sub-bands constituting the frequency band, determining first frequency offsets for the signal at reception sub-bands at which the signal has been detected among the plurality of sub-bands, and determining second frequency offsets by calibrating carrier frequency offsets based on a distance of each of the reception sub-bands from a center frequency of the frequency band.
Inventor(s): Aris Papasakellariou of Houston TX (US) for samsung electronics co., ltd.
IPC Code(s): H04W72/1273, H04L1/1812, H04W72/23
CPC Code(s): H04W72/1273
Abstract: methods and apparatuses for transmitting and receiving information of different priorities. a method of operating a ue includes receiving a first pdcch providing a first dci format. the first dci format schedules a reception of a pdsch, includes an mcs field, and includes a priority indicator field. the method further includes determining an mcs table, from a first predetermined mcs table or a second predetermined mcs table, based on a value of the priority indicator field in the first dci format; determining a modulation order and a code rate from the mcs table based on a value of the mcs field; receiving a tb in the pdsch according to the modulation order and the code rate; and determining a priority of harq-ack information in response to the tb reception based on the value of the priority indicator field in the first dci format.
Inventor(s): Sa ZHANG of Beijing (CN) for samsung electronics co., ltd., Feifei SUN of Beijing (CN) for samsung electronics co., ltd., Jingxing FU of Beijing (CN) for samsung electronics co., ltd.
IPC Code(s): H04W72/21, H04W72/563
CPC Code(s): H04W72/21
Abstract: a method and an apparatus for uplink transmissions in a wireless communication system are provided. the method includes receiving a downlink signal including at least one of downlink data or downlink control information (dci); and determining uplink signals to be transmitted based on the downlink signal, and determining at least one of a time unit or an uplink channel for transmitting the uplink signal, wherein the uplink signal includes at least one of uplink data or uplink control information (uci), and the uplink channel includes at least one of a physical uplink control channel (pucch) or a physical uplink shared channel (pusch); and performing an uplink transmission based on the determined uplink signals, and the determined time units and/or uplink channels. the invention can improve the efficiency of the uplink transmission.
Inventor(s): Sungjin PARK of Suwon-si (KR) for samsung electronics co., ltd., Hyunseok RYU of Suwon-si (KR) for samsung electronics co., ltd., Cheolkyu SHIN of Suwon-si (KR) for samsung electronics co., ltd., Jeongho YEO of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04W72/25, H04W72/0453
CPC Code(s): H04W72/25
Abstract: the present disclosure relates to a communication technique for converging iot technology with 5g communication systems for supporting a higher data transfer rate beyond 4g systems, and a system therefor. the present disclosure may be applied to intelligent services (for example, smart homes, smart buildings, smart cities, smart cars or connected cars, healthcare, digital education, retail businesses, security-and safety-related services, etc.) on the basis of 5g communication technology and iot-related technology. in addition, the present disclosure relates to a method and a device for transmitting/receiving sidelink information in an unlicensed band.
Inventor(s): Hyunjeong KANG of Suwon-si (KR) for samsung electronics co., ltd., Anil AGIWAL of Suwon-si (KR) for samsung electronics co., ltd., Kyeongin JEONG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04W72/25, H04L1/1829, H04W72/0446, H04W76/28
CPC Code(s): H04W72/25
Abstract: the present disclosure relates to a 5g or 6g communication system for supporting a higher data transmission rate. the present disclosure relates to a method by which a terminal operates an harq rtt timer during sidelink drx operation in a wireless communication system, the method comprising steps in which: a terminal acquires a sidelink harq rtt timer configuration from a transmission terminal, an nw or preconfigured information; the terminal derives a sidelink harq rtt timer to be applied to an harq process configured to be harq feedback enabled or to an harq process configured to be harq feedback disabled; and the terminal operates the derived sidelink harq rtt timer so as to perform a sidelink drx operation.
Inventor(s): Carmela Cozzo of San Diego CA (US) for samsung electronics co., ltd., Emad Nader Farag of Flanders NJ (US) for samsung electronics co., ltd., Hongbo Si of Allen TX (US) for samsung electronics co., ltd.
IPC Code(s): H04W72/563, H04W72/40
CPC Code(s): H04W72/563
Abstract: apparatuses and methods for sidelink and uplink transmissions and receptions. a method performed by a user equipment (ue) includes receiving first information for sidelink operation on multiple sidelink carriers. the first information includes priority values associated with the multiple sidelink carriers. the method includes determining a first number of sidelink carriers from the multiple sidelink carriers based on the priority values, first simultaneous transmissions or receptions on the first number of sidelink carriers based on the first information, a first sidelink carrier from the multiple sidelink carriers, wherein the first sidelink carrier is not in the first number of sidelink carriers, and whether to postpone or drop a first transmission or reception on the first sidelink carrier based on a physical channel associated with the first transmission or reception. the method further includes transmitting or receiving the first simultaneous transmissions or receptions on the first number of sidelink carriers.
20250016828. TWT OPERATION IN WIRELESS NETWORKS_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Rubayet Shafin of Allen TX (US) for samsung electronics co., ltd., Boon Loong Ng of Plano TX (US) for samsung electronics co., ltd., Peshal Nayak of Plano TX (US) for samsung electronics co., ltd., Vishnu Vardhan Ratnam of Plano TX (US) for samsung electronics co., ltd., Yue Qi of Plano TX (US) for samsung electronics co., ltd., Elliot Jen of Taipei (TW) for samsung electronics co., ltd.
IPC Code(s): H04W74/0816, H04W74/08, H04W84/12
CPC Code(s): H04W74/0816
Abstract: an access point (ap) affiliated with a non-simultaneous transmit and receive (nstr) mobile ap multi-link device (mld) and operating on a primary link may advertise a broadcast target wake time (twt) schedule for the other ap affiliated with the same nstr mobile ap mld and operating on a nonprimary link by including a twt element comprising a corresponding broadcast twt parameter set field in the sta profile field of the per-sta profile subelement of the basic multi-link element corresponding to the ap operating on the nonprimary link carried in beacon frames and/or probe response frame that it transmits on the primary link.
Inventor(s): Sangbum KIM of Suwon-si (KR) for samsung electronics co., ltd., Soenghun KIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H04W74/0816, H04W24/10, H04W76/19
CPC Code(s): H04W74/0816
Abstract: the present disclosure relates to a communication method and system for converging a 5th-generation (5g) communication system for supporting higher data rates beyond a 4th-generation (4g) system with a technology for internet of things (iot). the present disclosure may be applied to intelligent services based on the 5g communication technology and the iot-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. disclosed are a method and a device for a terminal to indicate whether lbt has failed or not and declare a detected lbt failure, in report mechanisms such as rlf, scg failure, establishment failure, and mdt.
Inventor(s): Qi XIONG of Beijing (CN) for samsung electronics co., ltd., Feifei SUN of Beijing (CN) for samsung electronics co., ltd., Yi WANG of Beijing (CN) for samsung electronics co., ltd.
IPC Code(s): H04W74/0833, H04W72/0446, H04W72/1263, H04W72/23, H04W74/00, H04W74/08
CPC Code(s): H04W74/0841
Abstract: the application provides a method performed by a user equipment in a wireless communication system, comprising: receiving first configuration information for transmitting uplink data signals from a base station, determining uplink transmission resources based on a first downlink signal associated with uplink transmission resources indicated in the first configuration information, and transmitting the uplink data signals.
20250016856. TDLS COEXISTENCE FOR NSTR OPERATION_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Rubayet Shafin of Allen TX (US) for samsung electronics co., ltd., Boon Loong Ng of Plano TX (US) for samsung electronics co., ltd., Yue Qi of Plano TX (US) for samsung electronics co., ltd., Peshal Nayak of Plano TX (US) for samsung electronics co., ltd., Vishnu Vardhan Ratnam of Plano TX (US) for samsung electronics co., ltd., Elliot Jen of Taipei City (TW) for samsung electronics co., ltd.
IPC Code(s): H04W76/14, H04W76/15
CPC Code(s): H04W76/14
Abstract: methods and apparatuses for handling tdls coexistence for emlsr operation, emlmr operation, and nstr operation. a method for wireless communication performed by a non-access point (ap) multi-link device (mld) that comprises stations (stas), the method comprising: forming links with corresponding aps of an ap mld; determining that a coexistence operation will be caused for the non-ap mld; generating a notification frame to transmit to the ap mld, the notification frame indicating a start time and an end time, the notification frame notifying the ap mld to avoid transmission to the non-ap mld between the start time and the end time so as to avoid causing the coexistence operation for the non-ap mld; and transmitting the notification frame to the ap mld.
Inventor(s): Jungshin PARK of Gyeonggi-do (KR) for samsung electronics co., ltd., Sangsoo JEONG of Gyeonggi-do (KR) for samsung electronics co., ltd.
IPC Code(s): H04W76/20, H04L41/0894, H04W80/06
CPC Code(s): H04W76/20
Abstract: the present disclosure relates to a 5g or 6g communication system for supporting a higher data transmission rate. one embodiment of the present invention can provide a method and an apparatus for providing a network service function requested by an application server in a wireless communication system.
Inventor(s): Sangbum KIM of Gyeonggi-do (KR) for samsung electronics co., ltd., Sangyeob JUNG of Gyeonggi-do (KR) for samsung electronics co., ltd.
IPC Code(s): H04W76/30, H04W8/18, H04W24/10
CPC Code(s): H04W76/30
Abstract: the present disclosure relates to a 5g or 6g communication system for supporting a higher data transmission rate. the present invention may provide a method capable of smoothly performing a standby mode or connection mode operation in other networks by considering multi-sim user equipment.
20250016937. ELECTRONIC DEVICE INCLUDING DISPLAY_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Dooryong KIM of Suwon-si (KR) for samsung electronics co., ltd., Yunsik KIM of Suwon-si (KR) for samsung electronics co., ltd., Jaemyung CHO of Suwon-si (KR) for samsung electronics co., ltd., Jingook KIM of Suwon-si (KR) for samsung electronics co., ltd., Yonghee JANG of Suwon-si (KR) for samsung electronics co., ltd., Sinyoung PARK of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H05K5/00, H04M1/02, H04M1/18, H05K5/02
CPC Code(s): H05K5/0017
Abstract: an electronic device is provided. the electronic device includes a hinge housing extending in a direction of a rotational axis, a first housing connected to one side of the hinge housing in a direction perpendicular to the rotational axis to rotate about the rotational axis relative to the hinge housing, a second housing connected to an opposite side of the hinge housing in a direction perpendicular to the rotational axis to rotate about the rotational axis relative to the hinge housing, and a flexible display including a bending area at least partially disposed in the hinge housing and formed to be a flat surface or a curved surface, a first area extending from the bending area in one direction perpendicular to the rotational axis, and a second area extending from the bending area in an opposite direction perpendicular to the rotational axis.
Inventor(s): Hyunsuk KIM of Suwon-si (KR) for samsung electronics co., ltd., Hojin JUNG of Suwon-si (KR) for samsung electronics co., ltd., Wonho LEE of Suwon-si (KR) for samsung electronics co., ltd., Joongyeon CHO of Suwon-si (KR) for samsung electronics co., ltd., Junghyeob LEE of Suwon-si (KR) for samsung electronics co., ltd., Hyunju HONG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H05K5/02, H01Q1/24, H05K5/03, H05K7/14
CPC Code(s): H05K5/0217
Abstract: an electronic device includes: a first housing; a second housing configured to slide with respect to the first housing; a rollable display including a first display area and a second display area extending from the first display area and including a bending portion which is bent, and configured such that at least a part of the second display area moves on the basis of the sliding of the second housing; and a circuit board disposed in the first housing and including a communication circuit configured to process an rf signal, where a lower end wall of the first housing includes: a non-metal area in which at least a part of the non-metal area faces the bending portion as a non-metal area spaced a designated distance apart from the bending portion; and at least one metal sheet disposed to cover at least a part of the non-metal area.
Inventor(s): Sungkoo PARK of Suwon-si (KR) for samsung electronics co., ltd., Mincheol SEO of Suwon-si (KR) for samsung electronics co., ltd., Soonho HWANG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H05K7/14, H04M1/02, H05K1/02, H05K1/14
CPC Code(s): H05K7/1427
Abstract: an electronic device according to an embodiment comprises: an inner housing; an outer housing coupled to the inner housing such that the inner housing is configured to move along a first direction or a second direction opposite to the first direction, and includes an opening formed in a portion of a surface that faces the second direction and connected to a space formed by the coupling of the outer housing and the inner housing; a side member comprising a conductive material and including at least one conductive portion which forms at least a portion of the side surface of the outer housing facing the second direction; and a wireless communication circuit operatively connected to the at least one conductive portion, wherein the wireless communication circuit can be configured to communicate with an external electronic device in a designated frequency band through the at least one conductive portion.
Inventor(s): Daehyuk SON of Suwon-si (KR) for samsung electronics co., ltd., Sungchan Kang of Suwon-si (KR) for samsung electronics co., ltd., Seongwoo Hong of Suwon-si (KR) for samsung electronics co., ltd., Daeyoung Kong of Seoul (KR) for samsung electronics co., ltd., Kiwan Kim of Seoul (KR) for samsung electronics co., ltd., Hyoungsoon Lee of Seoul (KR) for samsung electronics co., ltd.
IPC Code(s): H05K7/20, H01L23/473
CPC Code(s): H05K7/20272
Abstract: a cooling fluid circulation module includes: a first surface having a planar form and contacting a heating portion; a second surface opposite to the first surface and having a planar form, the second surface being spaced apart from the first surface; a first cooling channel extending between the first surface and the second surface in a first direction; a cooling fluid provided in the first cooling channel; and a plurality of first protrusions arranged along a plane on the second surface on which the first cooling channel extends, wherein each of the plurality of first protrusions may include a first surface inclined from the second surface by a first angle and a second surface inclined from the second surface by a second angle that is different than the first angle.
Inventor(s): Daekyu LEE of Suwon-si (KR) for samsung electronics co., ltd., Jongwoon LEE of Suwon-si (KR) for samsung electronics co., ltd., Jongik WON of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H05K9/00, H01R4/64, H05K5/00, H05K5/02
CPC Code(s): H05K9/0067
Abstract: an electronic device is provided. the electronic device includes a housing including a main body and a cover plate, a base plate disposed on the main body, a camera flange disposed on the base plate, a cover frame configured to cover the camera flange, a plurality of lens structures including an outer lens structure connected to the cover frame and an inner lens structure connected to the camera flange, and a first conductive connector disposed between the cover frame and the camera flange.
20250016974. SEMICONDUCTOR DEVICE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Jihoon Chang of Suwon-si (KR) for samsung electronics co., ltd., Changsik Kim of Suwon-si (KR) for samsung electronics co., ltd., Jaejoon Song of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00, H01L29/78
CPC Code(s): H10B12/05
Abstract: a semiconductor device includes a substrate, a first transistor and a second transistor on the substrate, a bit line electrically connected to the first transistor, a channel layer on the bit line, a gate insulating layer on the channel layer, a word line on the gate insulating layer, a landing pad electrically connected to the channel layer, a connection pad electrically connected to the word line and the second transistor, and a division structure separating the landing pad from the connection pad. the division structure includes an intervening portion between the landing pad and the connection pad.
Inventor(s): Jung Min PARK of Suwon-si (KR) for samsung electronics co., ltd., Ji-Sung KIM of Suwon-si (KR) for samsung electronics co., ltd., Hae Ryong KIM of Suwon-si (KR) for samsung electronics co., ltd., Bo-Eun PARK of Suwon-si (KR) for samsung electronics co., ltd., Han Jin LIM of Suwon-si (KR) for samsung electronics co., ltd., Hyung Suk JUNG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: a capacitor structure is provided. the capacitor structure comprises an upper electrode, a lower electrode including a lower electrode film and a lower interface electrode film, a capacitor dielectric film between the lower electrode and the upper electrode, and an interface blocking film between the lower electrode and the capacitor dielectric film, the interface blocking film being in contact with the capacitor dielectric film and the lower interface electrode film, wherein the interface blocking film includes a first metal oxide containing a first metal element, the lower interface electrode film includes a second conductive metal oxide containing a second metal element different from the first metal element, the capacitor dielectric film does not include the first metal oxide, and a thickness of the lower interface electrode film is greater than that of the interface blocking film.
20250016979. SEMICONDUCTOR DEVICE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): JONGMIN KIM of Suwon-si (KR) for samsung electronics co., ltd., CHANSIC YOON of Suwon-si (KR) for samsung electronics co., ltd., KISEOK LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: a semiconductor device may include first and second active patterns, first and second gate structures, a source/drain layer, a bit line structure, a contact plug structure, and a capacitor. the first and second active patterns are on a cell region and a peripheral circuit region of a substrate, respectively. the first gate structure extends through an upper portion of the first active pattern. the second gate structure is on an upper surface and an upper sidewall of the second active pattern. the source/drain layer is on a portion of the second active pattern that is adjacent to the second gate structure. the bit line structure is on a central portion of the first active pattern, and overlaps the second gate structure in a horizontal direction. the contact plug structure is on opposing end portions of the first active pattern. the capacitor is on the contact plug structure.
20250016980. SEMICONDUCTOR DEVICE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Kiseok Lee of Suwon-si (KR) for samsung electronics co., ltd., Bongsoo Kim of Suwon-si (KR) for samsung electronics co., ltd., Yongkwan Kim of Suwon-si (KR) for samsung electronics co., ltd., Jongmin Kim of Suwon-si (KR) for samsung electronics co., ltd., Taejin Park of Suwon-si (KR) for samsung electronics co., ltd., Chansic Yoon of Suwon-si (KR) for samsung electronics co., ltd., Jinwoo Han of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: a semiconductor device includes an active array in which a plurality of active patterns are arranged on a substrate; a gate structure extending in a first direction and crossing central portions of the active patterns; a bit line structure contacting first portions of the active patterns adjacent to a first sidewall of the gate structure and extending in a second direction; and a capacitor electrically connected to a second portion of each of the active patterns adjacent to a second sidewall of the gate structure. in a plan view, an upper end portion of each of the active patterns and a lower end portion of each of the active patterns are arranged to be spaced apart in a third direction oblique with respect to the first direction. the active patterns arranged side by side in the second direction form an active column.
Inventor(s): Yoonhwan Choi of Suwon-si (KR) for samsung electronics co., ltd., Masayuki Terai of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: an integrated circuit memory device includes a substrate having a bit line thereon, and a channel structure extending on the bit line. the channel structure includes a horizontal portion on the bit line and a vertical channel portion extending upwardly from one end of the horizontal portion. a word line is provided, which extends opposite the horizontal portion and crosses the bit line to extend in a second horizontal direction, which intersects the first horizontal direction. a landing pad structure is provided, and is electrically connected to the vertical channel portion. the landing pad structure includes a first contact portion in contact with an upper surface of the vertical channel portion and a second contact portion protruding downwardly from a lower surface of the first contact portion.
Inventor(s): Heonjun Ha of Suwon-si (KR) for samsung electronics co., ltd., Jungun Kim of Suwon-si (KR) for samsung electronics co., ltd., Injae Bae of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/48
Abstract: an example semiconductor device includes a substrate including a cell array region and a connection region, a peripheral circuit layer, a bit line disposed on the peripheral circuit layer in the cell array region, a first upper interconnection disposed in the connection region on a same height as the bit line is from the substrate, at least one lower interconnection layer disposed between the peripheral circuit layer and the bit line and between the peripheral circuit layer and the first upper interconnection, a bit line insulating layer surrounding the bit line in the cell array region and the first upper interconnection in the connection region, an upper structure disposed on the bit line and the first upper interconnection, an information storage structure disposed on the upper structure in the cell array region, and a lower contact plug electrically connected to the at least one lower interconnection layer.
20250016987. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Jae Won NA of Suwon-si (KR) for samsung electronics co., ltd., Jul Pin PARK of Suwon-si (KR) for samsung electronics co., ltd., Jong Moo LEE of Suwon-si (KR) for samsung electronics co., ltd., Chang Sik KIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/482
Abstract: a semiconductor memory device including a bit line including a metal and extending in a first direction on a substrate; a channel structure on the bit line, including a first channel pattern extending in a second direction, and a second channel pattern spaced apart from the first channel pattern in the first direction and extending in the second direction; a liner film between the bit line and the channel structure, and including the metal; a first word line between the first and second channel patterns, and the first word line extending in the second direction; a second word line between the first and second channel patterns, and extending in the second direction, and the second word line spaced apart from the first word line in the first direction; and first and second capacitors respectively on the first and second channel patterns, and connected to the first and second channel patterns.
20250016988. SEMICONDUCTOR DEVICE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): DONG-SIK PARK of SUWON-SI (KR) for samsung electronics co., ltd., JAE WON NA of SUWON-SI (KR) for samsung electronics co., ltd., JIHEE JUN of SUWON-SI (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/482
Abstract: a semiconductor device includes a substrate including cell array and peripheral regions, a bit line positioned in the cell array region and extending in a first direction, a shielding line extending in the first direction from the cell array region to the peripheral region and positioned adjacent to the bit line in a second direction crossing the first direction, a shielding contact line positioned in the peripheral region, extending in the second direction, and connected to the shielding line, a channel pattern positioned on the bit line and extending in a direction vertical from the bit line, a word line extending in the second direction and positioned on the channel pattern, a gate insulation pattern positioned between the channel pattern and the word line, an insulation pattern positioned on the word line, a landing pad connected to the channel pattern, and a data storage pattern connected to the landing pad.
20250016990. SEMICONDUCTOR DEVICE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Choonghyun LEE of Suwon-si (KR) for samsung electronics co., ltd., Kanguk KIM of Suwon-si (KR) for samsung electronics co., ltd., Jooncheol KIM of Suwon-si (KR) for samsung electronics co., ltd., Jina KIM of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/482
Abstract: a semiconductor device is provided. the semiconductor device includes a first bit line crossing a memory cell array region in a first direction and extending into an extension region adjacent to the memory cell array region, a second bit line crossing the memory cell array region in the first direction and extending into the extension region, and adjacent to the first bit line, an insulating pattern within the extension region and contacting an end portion of the second bit line in the first direction, and an insulating spacer within the extension region and contacting an end portion of the first bit line in the first direction, the insulating spacer being different from the insulating pattern.
Inventor(s): Jaejoon Song of Suwon-si (KR) for samsung electronics co., ltd., Julpin Park of Suwon-si (KR) for samsung electronics co., ltd., Deokhwan Choi of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/482
Abstract: an integrated circuit memory device (e.g., dram) includes a substrate having a bit line thereon, and an electrically insulating region having a first opening therein, which exposes a first portion of the bit line. a first semiconductor active layer is provided, which lines first and second opposing sidewalls of the first opening and the exposed first portion of the bit line, such that a direct electrical connection is provided between the exposed first portion of the bit line and a portion of the first semiconductor active layer extending between the first and second sidewalls of the first opening. a first word line is provided on a first portion of the first semiconductor active layer extending opposite the first sidewall of the first opening, and a second word line is provided on a second portion of the first semiconductor active layer extending opposite the second sidewall of the first opening.
20250016992. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Juho Lee of Suwon-si (KR) for samsung electronics co., ltd., Mintae Ryu of Suwon-si (KR) for samsung electronics co., ltd., Youngseok Park of Suwon-si (KR) for samsung electronics co., ltd., Seongjae Byeon of Suwon-si (KR) for samsung electronics co., ltd., Younggeun Song of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/482
Abstract: a semiconductor memory device includes a substrate, a conductive line disposed on the substrate, a horizontal channel portion extending in a first direction on the conductive line and partially covering the conductive line, a separation insulating layer disposed on the horizontal channel portion, a gate insulating layer including a first portion on the conductive line and a second portion that extends in a second direction that is perpendicular to the substrate, a vertical channel portion between the gate insulating layer and the separation insulating layer, the vertical channel portion extending in the second direction, and a spacer on the first portion of the gate insulating layer. a first material included in the horizontal channel portion is different from a second material included in the vertical channel portion.
20250016993. SEMICONDUCTOR DEVICE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Sung-Hwan JANG of Suwon-si (KR) for samsung electronics co., ltd., Guifu YANG of Suwon-si (KR) for samsung electronics co., ltd., Jinbum KIM of Suwon-si (KR) for samsung electronics co., ltd., Sunguk JANG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/485
Abstract: a semiconductor device includes a substrate including a recess region; a bit line contact in the recess region; a bit line on the bit line contact, the bit line extending in a first direction; a first insulating pattern covering side surfaces of the bit line contact and an inner surface of the recess region; and a second insulating pattern on the first insulating pattern, wherein an oxygen density of the first insulating pattern is higher than an oxygen density of the second insulating pattern.
20250016994. SEMICONDUCTOR DEVICE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Heejae CHAE of Suwon-si (KR) for samsung electronics co., ltd., Hyunjin LEE of Suwon-si (KR) for samsung electronics co., ltd., Yun CHOI of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/485
Abstract: the semiconductor includes a substrate including first active patterns, the substrate defining trenches between the first active patterns; an upper silicon pattern on an upper sidewall of at least a portion of each of the first active patterns; and a first contact plug contacting an edge portion in a longitudinal direction of each of the first active patterns, a sidewall of the first contact plug contacting at least a portion of the upper silicon pattern, and the first contact plug having a bottom lower than a bottom of the upper silicon pattern.
Inventor(s): Kang Lib KIM of Suwon-si (KR) for samsung electronics co., ltd., Sungsu MOON of Suwon-si (KR) for samsung electronics co., ltd., Sea Hoon LEE of Suwon-si (KR) for samsung electronics co., ltd., Junhee LIM of Suwon-si (KR) for samsung electronics co., ltd., Seongpil CHANG of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B43/27, H01L25/065, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/35, H10B80/00
CPC Code(s): H10B43/27
Abstract: a semiconductor device includes a cell array region and a connection region. a gate stacking structure includes gate electrodes and interlayer insulation layers that are alternately stacked. the gate stacking structure extends in a first direction and is separated by separation structures in a second direction. a channel structure penetrates the gate stacking structure in the cell array region. gate contact portions penetrate the gate stacking structure in the connection region. the gate contact portions are electrically connected to the gate electrodes, respectively. an insulation layer is provided separately from the separation structure and covers at least the gate stacking structure. the insulation layer comprises a base insulation portion and a hydrogen-containing insulation portion. the hydrogen-containing insulation portion includes a hydrogen-containing portion having a different material from a material of the base insulation portion. the hydrogen-containing portion including hydrogen.
Inventor(s): Siyeong Yang of Suwon-si (KR) for samsung electronics co., ltd., Yuyeon Kim of Suwon-si (KR) for samsung electronics co., ltd., Chaeho Kim of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B43/27, H01L23/00, H01L25/065, H01L25/18, H10B41/27, H10B80/00
CPC Code(s): H10B43/27
Abstract: a semiconductor device includes a gate stacking structure, a channel structure, and a horizontal conductive layer. the gate stacking structure may include a plurality of gate electrodes and a plurality of insulation layers that are alternately stacked. the channel structure may be provided with an inner portion extending into the gate stacking structure and a protruded portion that protrudes from one surface of the gate stacking structure. the horizontal conductive layer may be connected to the protruded portion of the channel structure. in this case, the channel structure may include a semiconductor layer. the semiconductor layer may include a polycrystalline region in at least the protruded portion and including a polycrystalline semiconductor material and in a channel region positioned in the inner portion and having a crystal structure different from a crystal structure of the polycrystalline region.
Inventor(s): Seokcheon BAEK of Hwaseong-si (KR) for samsung electronics co., ltd., Miram KWON of Suwon-si (KR) for samsung electronics co., ltd., Seongjun SEO of Hwaseong-si (KR) for samsung electronics co., ltd., Younghwan SON of Hwaseong-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B43/27, H01L27/06, H10B43/40
CPC Code(s): H10B43/27
Abstract: a semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. the first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. the second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. the first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.
Inventor(s): Hoseok Heo of Suwon-si (KR) for samsung electronics co., ltd., Kyunghun Kim of Suwon-si (KR) for samsung electronics co., ltd., Sunho Kim of Suwon-si (KR) for samsung electronics co., ltd., Hyungyung Kim of Suwon-si (KR) for samsung electronics co., ltd., Minhyun Lee of Suwon-si (KR) for samsung electronics co., ltd., Seokhoon Choi of Suwon-si (KR) for samsung electronics co., ltd., Seungdam Hyun of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B43/35, H01L29/423
CPC Code(s): H10B43/35
Abstract: a vertical nand flash memory device and an electronic apparatus including the same are provided. the vertical nand flash memory device includes a plurality of cell arrays. each of the plurality of cell arrays includes a channel layer, a charge trap layer, and a plurality of gate electrodes provided on the charge trap layer. the charge trap layer includes a matrix including amorphous metal oxynitride and nanocrystals dispersed in the matrix and including nitride having semiconductor characteristics.
Inventor(s): Seongjae GO of Suwon-si (KR) for samsung electronics co., ltd., Duyoung YANG of Suwon-si (KR) for samsung electronics co., ltd., Kangmin KIM of Suwon-si (KR) for samsung electronics co., ltd., Jongseon AHN of Suwon-si (KR) for samsung electronics co., ltd., Byeongin CHOE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B43/35, H10B41/27, H10B41/35, H10B43/27
CPC Code(s): H10B43/35
Abstract: a semiconductor device includes a plate layer; gate electrodes stacked and spaced apart from each other on the plate layer and including first gate electrodes and a second gate electrode on the first gate electrodes; first channel structures extending in the first gate electrodes; and second channel structures extending in the second gate electrode and electrically connected to the first channel structures, respectively, wherein the second gate electrode includes a metal material, and wherein each of the second channel structures includes a second channel layer, a second gate dielectric layer between the second channel layer and the second gate electrode, a second channel buried insulating layer on an internal side surface of the second channel layer, a second channel pad on the second channel buried insulating layer, and a second pad oxide layer on the second channel pad and the second channel layer.
Inventor(s): Seulji SONG of Suwon-si (KR) for samsung electronics co., ltd., Suhyun BANG of Suwon-si (KR) for samsung electronics co., ltd., Hwayeong LEE of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10B53/30, H10B53/20
CPC Code(s): H10B53/30
Abstract: an integrated circuit device including first and second vertical transistors, wherein the first and second vertical transistors are apart from each other in a first direction; a common plate between the first and second vertical transistors; a first capacitor structure between the first vertical transistor and the common plate including a first lower electrode extending in the first direction, a first dielectric layer on the first lower electrode, and a first upper electrode on the first dielectric layer; and a second capacitor structure between the second vertical transistor and the common plate including a second lower electrode extending in the first direction, a second dielectric layer on the second lower electrode, and a second upper electrode on the second dielectric layer, wherein the first upper electrode is on a lower surface of the common plate, and the second upper electrode is on an upper surface of the common plate.
20250017118. MAGNETIC MEMORY DEVICE_simplified_abstract_(samsung electronics co., ltd.)
Inventor(s): Se Chung Oh of Suwon-si (KR) for samsung electronics co., ltd., JeongMok Kim of Suwon-si (KR) for samsung electronics co., ltd., Tanyoung Kim of Suwon-si (KR) for samsung electronics co., ltd., Heeju Shin of Suwon-si (KR) for samsung electronics co., ltd., YoungJun Cho of Suwon-si (KR) for samsung electronics co., ltd.
IPC Code(s): H10N50/80, H10B61/00, H10N50/01, H10N50/20
CPC Code(s): H10N50/80
Abstract: a magnetic memory device includes a reference magnetic pattern and a free magnetic pattern stacked on a substrate, a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, a first non-magnetic pattern on the free magnetic pattern, the free magnetic pattern being between the tunnel barrier pattern and the first non-magnetic pattern, a second non-magnetic pattern on the first non-magnetic pattern, the first non-magnetic pattern being between the free magnetic pattern and the second non-magnetic pattern, a metal pattern between the first non-magnetic pattern and the second non-magnetic pattern, and a conductive layer on a side surface of the first non-magnetic pattern.
Samsung Electronics Co., Ltd. patent applications on January 9th, 2025
- Samsung Electronics Co., Ltd.
- A47L9/28
- CPC A47L9/2873
- Samsung electronics co., ltd.
- A61B5/11
- A61B5/00
- G16H20/30
- CPC A61B5/1121
- A61H3/00
- CPC A61H3/00
- A63B21/00
- A63B24/00
- CPC A63B21/00069
- A63F13/537
- A63F13/22
- CPC A63F13/537
- B01D61/42
- C02F1/469
- CPC B01D61/4281
- B01J7/00
- C23C16/448
- H01L21/67
- CPC B01J7/00
- C02F1/46
- C02F1/461
- CPC C02F1/4602
- CPC C02F1/4691
- C09G1/02
- H01L21/321
- CPC C09G1/02
- C09K11/74
- B82Y20/00
- B82Y40/00
- C01G28/00
- C09K11/88
- CPC C09K11/7492
- C09K13/06
- H01L21/3213
- CPC C09K13/06
- C23C16/455
- CPC C23C16/45565
- E05F15/614
- F25D23/02
- CPC E05F15/614
- F16L59/065
- CPC F16L59/065
- F25B21/00
- CPC F25B21/00
- G01B9/02
- G01B9/02001
- G01B9/02056
- CPC G01B9/02044
- G01N21/956
- G01N21/95
- G06T7/00
- CPC G01N21/956
- G01R31/28
- CPC G01R31/2875
- G01S13/76
- G08B3/10
- G08B5/22
- CPC G01S13/767
- G02B13/00
- G02B5/00
- G02B9/62
- H04N23/55
- CPC G02B13/0045
- G02F1/13357
- CPC G02F1/133608
- G02F1/1335
- CPC G02F1/133612
- G03F1/64
- G03F1/66
- CPC G03F1/64
- G05B15/02
- G06F1/16
- G09G3/00
- CPC G05B15/02
- G05D1/229
- G01S17/89
- G05D1/224
- G05D1/24
- G06V10/764
- CPC G05D1/2295
- CPC G06F1/1681
- G06F3/0484
- G06F12/02
- CPC G06F3/0484
- G06F3/06
- CPC G06F3/0608
- CPC G06F3/0625
- G06F11/34
- CPC G06F3/0653
- G06F13/16
- CPC G06F3/0655
- CPC G06F3/0659
- G06F3/16
- G10L25/66
- G10L25/72
- CPC G06F3/165
- G06F7/58
- CPC G06F7/588
- G06F9/455
- G06F9/48
- CPC G06F9/45558
- G06F9/50
- CPC G06F9/5033
- G06F11/22
- G06F11/277
- CPC G06F11/2268
- G06F12/1009
- G06F12/1036
- G06F12/1081
- CPC G06F12/1009
- G06F13/20
- G06F1/06
- CPC G06F13/20
- G06F16/23
- CPC G06F16/2379
- G06F17/15
- CPC G06F17/15
- G06F21/56
- G06F11/10
- CPC G06F21/566
- G06N3/0464
- CPC G06N3/0464
- G06N3/063
- G06N3/082
- G06N5/046
- CPC G06N3/063
- CPC G06N3/082
- G06N3/098
- CPC G06N3/098
- G06T3/4053
- G06V10/77
- G06V10/82
- CPC G06T3/4053
- G06T5/50
- G06T3/4007
- G06T5/70
- CPC G06T5/50
- G06T5/20
- G06T7/11
- CPC G06T7/001
- G06T7/55
- G06T7/60
- CPC G06T7/55
- G06T11/60
- G06F3/01
- G06V20/20
- G06V40/20
- CPC G06T11/60
- G06V10/141
- G06T7/20
- G06V40/18
- G06V40/19
- H04N23/56
- H04N23/90
- CPC G06V10/141
- G06V10/60
- G06T5/40
- CPC G06V10/60
- G09G3/20
- H03M7/30
- CPC G09G3/2096
- G09G3/3233
- CPC G09G3/3233
- G09G3/34
- G09G3/32
- CPC G09G3/3426
- G10L15/22
- G10L15/18
- CPC G10L15/22
- G11C11/16
- CPC G11C11/1657
- CPC G11C11/1659
- G11C11/4076
- G11C11/4093
- G11C11/4099
- CPC G11C11/4076
- G11C11/408
- G11C11/4096
- CPC G11C11/4093
- G11C11/412
- G06N3/08
- G11C11/418
- G11C11/419
- CPC G11C11/412
- G11C16/04
- H01L23/522
- H01L23/528
- H10B41/10
- H10B41/27
- H10B41/35
- H10B41/41
- H10B43/10
- H10B43/27
- H10B43/35
- H10B43/40
- CPC G11C16/0483
- G11C16/08
- G11C5/06
- CPC G11C16/08
- G11C16/10
- G11C11/56
- G11C16/34
- H01L29/788
- CPC G11C16/10
- CPC G11C16/102
- G11C16/16
- G11C16/28
- CPC G11C16/3495
- G11C29/12
- G11C29/42
- CPC G11C29/12005
- G11C29/52
- CPC G11C29/52
- H01G4/232
- H01G4/30
- H05K1/18
- CPC H01G4/232
- H01J37/32
- H01L21/683
- CPC H01J37/32568
- G03F7/16
- H01L21/66
- CPC H01L21/67051
- H01L23/13
- H01L21/48
- H01L21/78
- H01L23/498
- CPC H01L23/13
- H01L23/31
- H01L23/00
- H01L23/14
- H01L23/26
- H01L23/29
- H01L23/49
- H01L25/00
- H01L25/10
- CPC H01L23/3107
- CPC H01L23/3114
- H01L23/367
- H01L25/18
- CPC H01L23/3675
- H01L23/48
- CPC H01L23/481
- H01L23/485
- H01L23/538
- CPC H01L23/49816
- H01L25/065
- CPC H01L23/5223
- H01L29/06
- H01L29/417
- H01L29/423
- H01L29/66
- H01L29/775
- H01L29/786
- CPC H01L23/5283
- H01L21/768
- H01L23/532
- H10B80/00
- CPC H01L23/5382
- CPC H01L23/5389
- H01L23/64
- CPC H01L23/642
- CPC H01L24/05
- H01L21/56
- CPC H01L24/06
- CPC H01L24/81
- CPC H01L24/82
- CPC H01L25/0652
- CPC H01L25/0657
- H01L23/15
- CPC H01L25/105
- H01L25/16
- CPC H01L25/16
- CPC H01L25/162
- H01L27/146
- CPC H01L27/14603
- CPC H01L27/14627
- G02B5/20
- H04N25/11
- CPC H01L27/1463
- H01L29/08
- H01L29/78
- CPC H01L29/0847
- H01L29/24
- H10B12/00
- H01L27/088
- CPC H01L29/42364
- CPC H01L29/7827
- H01L29/51
- CPC H01L29/78391
- H01M50/105
- H01M10/42
- H01M50/184
- H01M50/186
- H02H7/18
- CPC H01M50/105
- H01M50/536
- H01M10/04
- H01M50/247
- H01M50/528
- CPC H01M50/536
- H01Q1/22
- H01Q1/48
- H01Q9/04
- H01Q9/40
- CPC H01Q1/22
- H01Q1/38
- CPC H01Q1/2266
- H01Q21/28
- H04L25/02
- CPC H01Q21/28
- H03B5/12
- CPC H03B5/1212
- H04L5/00
- H04L47/28
- H04W84/12
- CPC H04L5/0078
- H04L9/00
- G06F21/62
- CPC H04L9/008
- H04L12/28
- CPC H04L12/282
- A61B5/01
- A61B5/0205
- A61B5/024
- A61B5/08
- H04L27/26
- CPC H04L27/2613
- H04L47/125
- H04L45/74
- H04L47/24
- CPC H04L47/125
- H04L67/141
- CPC H04L67/141
- H04M1/02
- H04M1/72436
- CPC H04M1/0243
- H04N19/136
- H04N19/124
- H04N19/172
- H04N19/174
- H04N19/463
- H04N19/58
- H04N19/70
- H04N19/86
- CPC H04N19/136
- H04N19/513
- H04N19/139
- H04N19/176
- CPC H04N19/513
- H04N21/4788
- H04N7/15
- H04N21/431
- H04N21/45
- CPC H04N21/4788
- H04N23/51
- CPC H04N23/55
- H04N23/68
- H04N23/52
- H04N23/57
- CPC H04N23/687
- H04N23/71
- G06V10/25
- CPC H04N23/71
- H04N23/951
- G06T7/292
- H04N23/86
- CPC H04N23/951
- H04N25/704
- H04N25/44
- H04N25/766
- H04N25/778
- CPC H04N25/704
- H04R1/30
- G06F30/20
- CPC H04R1/30
- H04R3/00
- G06F1/08
- G06F1/3212
- H04M9/08
- CPC H04R3/005
- H04W12/06
- H04W76/10
- H04W76/30
- CPC H04W12/06
- H04W28/02
- H04W28/24
- H04W72/23
- H04W72/53
- H04W72/542
- H04W76/15
- CPC H04W28/0268
- H04W28/26
- H04L41/0806
- H04W4/50
- CPC H04W28/26
- H04W36/08
- H04W36/00
- CPC H04W36/08
- H04W48/18
- H04M15/00
- CPC H04W48/18
- H04W8/22
- H04W60/04
- H04W8/02
- H04W36/06
- H04W48/16
- H04W76/11
- H04W52/02
- H04W72/30
- H04W76/14
- H04W76/40
- CPC H04W52/0235
- H04W68/02
- CPC H04W68/02
- H04W72/0446
- H04W72/0453
- H04W72/1268
- H04W72/231
- H04W72/25
- H04W74/0833
- CPC H04W72/0446
- CPC H04W72/0453
- H04W72/1273
- H04L1/1812
- CPC H04W72/1273
- H04W72/21
- H04W72/563
- CPC H04W72/21
- CPC H04W72/25
- H04L1/1829
- H04W76/28
- H04W72/40
- CPC H04W72/563
- H04W74/0816
- H04W74/08
- CPC H04W74/0816
- H04W24/10
- H04W76/19
- H04W72/1263
- H04W74/00
- CPC H04W74/0841
- CPC H04W76/14
- H04W76/20
- H04L41/0894
- H04W80/06
- CPC H04W76/20
- H04W8/18
- CPC H04W76/30
- H05K5/00
- H04M1/18
- H05K5/02
- CPC H05K5/0017
- H01Q1/24
- H05K5/03
- H05K7/14
- CPC H05K5/0217
- H05K1/02
- H05K1/14
- CPC H05K7/1427
- H05K7/20
- H01L23/473
- CPC H05K7/20272
- H05K9/00
- H01R4/64
- CPC H05K9/0067
- CPC H10B12/05
- CPC H10B12/315
- CPC H10B12/48
- CPC H10B12/482
- CPC H10B12/485
- CPC H10B43/27
- H01L27/06
- CPC H10B43/35
- H10B53/30
- H10B53/20
- CPC H10B53/30
- H10N50/80
- H10B61/00
- H10N50/01
- H10N50/20
- CPC H10N50/80
