SK hynix Inc. patent applications on September 12th, 2024
Patent Applications by SK hynix Inc. on September 12th, 2024
SK hynix Inc.: 22 patent applications
SK hynix Inc. has applied for patents in the areas of G06F3/06 (6), H01L23/528 (2), H10B43/27 (2), G11C16/34 (2), G01K7/18 (1) H10B43/27 (2), G06F3/064 (2), G11C7/1006 (1), H03M13/1177 (1), H01L23/5226 (1)
With keywords such as: memory, data, device, circuit, value, configured, signal, based, structure, and program in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Hyun Mo SUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Yoon Jae SHIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G01K7/18, G01K7/20
CPC Code(s): G01K7/183
Abstract: a temperature sensor includes a first trimming resistor having a first resistance value that is trimmed based on a first trimming code and configured to adjust a gate voltage, a mos transistor turned on based on the gate voltage and configured to drive a variable voltage having a voltage level set for each sensing temperature, and a second trimming resistor connected to the mos transistor, the second trimming resistor having a second resistance value that is trimmed based on a second trimming code.
Inventor(s): Alexander Zapotylok of Minsk (BY) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: disclosed are methods and systems that can perform a loopback operation during a power loss protection (plp) procedure. in some implementations, a method includes identifying, upon issuance of a command abort signal for aborting a command queued in the memory system, a current state of the command, receiving, by the memory system, one or more input/output (io) packets corresponding to the current state of the command, and performing operations corresponding to the command on the one or more io packets.
Inventor(s): Seon Ha PARK of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0632
Abstract: in some embodiments of the disclosed technology, a memory controller may include a data strobe signal (dqs) calibration circuit configured to calibrate timing of a data strobe signal (dqs) for a plurality of memory dies by performing n unit dqs calibration operations, wherein n is a natural number, wherein performing the n unit dqs calibration operations includes: performing m unit dqs calibration operations in a normal mode on the plurality of memory dies, wherein m is a natural number smaller than n; upon failure of calibration during the m unit dqs calibration operations in the normal mode, determining a representative memory die of the plurality of memory dies that causes the failure of calibration; and performing n−m unit dqs calibration operations in a conditional mode on the plurality of memory dies by varying parameters associated with the representative memory die of the plurality of memory dies.
Inventor(s): Tae Yeon HWANG of Icheon-si (KR) for sk hynix inc., Kyung Hoon LEE of Icheon (KR) for sk hynix inc., Sung Hun JEON of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a storage device may search for a target page among pages included in a first memory block of a plurality of memory blocks each including a plurality of pages, and when an uncorrectable error occurs while reading data stored in the target page, may overwrite dummy data into the target page and then store address information indicating a location of the target page in a second memory block among the plurality of memory blocks.
Inventor(s): Jae Woong KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a semiconductor memory device, and a method of operation, includes a memory block including a plurality of memory strings. the semiconductor memory device also includes a peripheral circuit performing a main program operation on drain select transistors included in the memory block, and a test program operation and a threshold voltage monitoring operation on memory cells included in the memory block. the semiconductor memory device further includes control logic controlling the peripheral circuit to detect a disturb susceptible memory string, among the plurality of memory strings, based on a result of performing the threshold voltage monitoring operation on the memory cells, and to perform an additional program operation on a drain select transistor included in the disturb susceptible memory string.
Inventor(s): Hyeok Chan SOHN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Kang Wook JO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hyeon Cheon SEOL of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Byung Ryul KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jae Young LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a storage device may include: a memory device for extracting bits having a first logic value among bits included in data received from outside the memory device, generating a plurality of compressed data chunks including the bits comprising the first logic value and position information representing positions of the bits having the first logic value in the data, and outputting the plurality of compressed data chunks in response to a data output command; and a memory controller for receiving the plurality of compressed data chunks from the memory device, and recovering the data, based on the bits having the first logic value, which are included in the plurality of compressed data, and the position information.
Inventor(s): Dong Sop LEE of Icheon (KR) for sk hynix inc., Ie Ryung PARK of Icheon (KR) for sk hynix inc., Tae Ho LIM of Icheon (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0656
Abstract: according to an embodiment of the present disclosure, a storage device may include a memory device including a plurality of zones, a memory device including a plurality of zones; a buffer memory device including a plurality of slots; and a memory controller including a plurality of zone buffers respectively corresponding to the plurality of zones. the memory controller may store write data in one or more of the plurality of slots, store map data corresponding to the write data in a zone buffer that corresponds to a zone in which the write data is to be stored, and then store the write data, which is stored in the one or more slots, in the zone corresponding to the zone buffer based on the map data stored in the zone buffer.
20240303035. SORTING CIRCUIT AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Joo Young KIM of Gyeonggi-do (KR) for sk hynix inc., Tae Young Ahn of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F7/24, G06F7/02
CPC Code(s): G06F7/24
Abstract: a sorting circuit includes an input buffer, a sorting buffer, a comparing circuit and a processing circuit. the input buffer sequentially receives values and sequentially store therein the values. the sorting buffer stores therein selected ones from among the values as each of the values is inserted thereto or discarded. the comparing circuit compares an input value currently received from among the values with each of a previous value and sorted values and output an input value comparison result. the previous value is a value that the input buffer receives immediately before receiving the input value, from among the values, and the sorted values are values stored in the sorting buffer immediately before the previous value is discarded or inserted into the sorting buffer. the processing circuit selectively inserts, based on the input value comparison result, the input value into the sorting buffer.
Inventor(s): Yeohyeon PARK of Seoul (KR) for sk hynix inc., Seungjin LEE of Seoul (KR) for sk hynix inc., Changgyu LEE of Seoul (KR) for sk hynix inc., Youngjae KIM of Seoul (KR) for sk hynix inc., Inhyuk PARK of Icheon (KR) for sk hynix inc., Soonyeal YANG of Icheon (KR) for sk hynix inc., Woo Suk CHUNG of Icheon (KR) for sk hynix inc.
IPC Code(s): G06F9/48
CPC Code(s): G06F9/4881
Abstract: a computational storage device includes a storage device and a computation control circuit. the computation control circuit includes multi-core processor and is configured to generate an input/output (i/o) task according to an i/o command, generate a background task according to the i/o command, select an idle core among a plurality of cores in the multi-core processor to perform the background task, and control the storage device. the computation control circuit may include a task control module configured to select the idle core.
Inventor(s): Eun Jae OCK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F11/07
CPC Code(s): G06F11/076
Abstract: an electronic device includes a communication interface for, when a predetermined event occurs, transmitting a data signal generated based on data and a signal processing characteristic value to a memory system, and receiving eye diagram information corresponding to the data signal from the memory system; and a signal processing controller for controlling the signal processing characteristic value, based on an interval change value of the eye diagram information.
Inventor(s): Aliaksandr Zapatylak of Minsk (BY) for sk hynix inc., Aleksei Popov of Minsk (BY) for sk hynix inc., Leonid Zaliubovskyi of Minsk (BY) for sk hynix inc., Leanid Kavaliou of Minsk (BY) for sk hynix inc.
IPC Code(s): G06F12/0804
CPC Code(s): G06F12/0804
Abstract: disclosed is a power loss protection method. in some implementations, the method includes initiating a timer to indicate a progress of a power loss protection procedure that performs a data transfer upon occurrence of a power loss interrupt event, initiating a first data transfer operation to transfer a first amount of data to a memory device, and upon an indication by the timer that the power loss protection procedure has reached a predetermined progress level, continuing the first data transfer operation until the first amount of data is transferred to the memory device, or upon an indication by the timer that the power loss protection procedure has failed to reach the predetermined progress level, discontinuing the first data transfer operation and performing a second data transfer operation to transfer a second amount of data to the memory device, wherein the second amount is less than the first amount.
Inventor(s): Byoung Min JIN of Gyeonggi-do (KR) for sk hynix inc., Ku Ik KWON of Gyeonggi-do (KR) for sk hynix inc., Hyun Jin CHUNG of Gyeonggi-do (KR) for sk hynix inc., Gyu Yeul HONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F12/0806
CPC Code(s): G06F12/0806
Abstract: a controller includes at least one register configured to store a doorbell regarding a submission queue storing at least one request generated by a host, a first cache configured to store data corresponding to a first result of an operation performed in response to the at least one request, a second cache configured to store data corresponding to a second result of an operation performed in response to a read look ahead (rla) request generated based on the at least one request, and a cache size manager configured to adjust a size of the second cache based on an update cycle of the doorbell and a change of a number of the at least one request corresponding to the doorbell.
Inventor(s): Tae Hun PARK of Gyeonggi-do (KR) for sk hynix inc., Kyu Nam LIM of Gyeonggi-do (KR) for sk hynix inc., Dong Hun KWAK of Gyeonggi-do (KR) for sk hynix inc., Hyung Jin CHOI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/10, G11C11/56
CPC Code(s): G11C7/1006
Abstract: the present technology relates to a semiconductor device. according to the present technology, a memory device capable of dividing and storing a plurality of data bits in a plurality of memory cells may include a plurality of memory cells each configured to have a state among a plurality of states, a code table generator configured to generate, based on a plurality of data bits, a code table indicating the plurality of states as code patterns formed by parts of the data bits, the parts corresponding to the respective memory cells, and an internal operation controller configured to divide and store a plurality of target data bits in the plurality of memory cells based on the code table during a program operation.
20240304249. MEMORY DEVICE AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Hyung Jin CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Se Chun PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chan Hui JEONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/34
CPC Code(s): G11C16/10
Abstract: a memory device may include memory cells connected to a selected word line, and a peripheral circuit configured to store information regarding a foggy program pass loop in which a target program state is determined as foggy program pass during a foggy program operation on the selected word line, calculate a fine program pass loop based on the foggy program pass loop, and determine the target program state as fine program pass in the fine program pass loop of a fine program operation on the selected word line.
Inventor(s): Sung Hun KIM of Gyeonggi-do (KR) for sk hynix inc., Hyo Jae LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/26, G11C5/14, G11C16/08, G11C16/34
CPC Code(s): G11C16/26
Abstract: disclosed are a non-volatile memory device, a memory system including the same and a read method of the memory system, in which the non-volatile memory device includes a first storage in which a basic offset level for a read retry operation is stored, a second storage in which an additional offset level for the read retry operation is stored, and a voltage generator suitable for adjusting, when the read retry operation is performed, a read voltage by using the basic offset level and further by selectively using the additional offset level depending on a read operation.
Inventor(s): Yoon Jae SHIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Doo Hyun SON of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/46, G11C7/02, G11C29/12
CPC Code(s): G11C29/46
Abstract: an electronic device includes a monitoring signal generation circuit configured to receive an internal voltage to generate a monitoring signal, based on a voltage selection signal in a test mode, and an internal voltage drive circuit configured to receive the internal voltage and monitoring signal from the monitoring signal generation circuit and drive the internal voltage to compensate for the monitoring signal when the monitoring signal is distorted according to a leakage current in the test mode.
20240304454. MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Pil Hoon JUNG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H01L21/311, H01L21/033
CPC Code(s): H01L21/31144
Abstract: a manufacturing method of a semiconductor device may include: forming a stack including first material layers and second material layers that are alternately stacked; forming, on the stack, an inorganic material-containing polymer mask including a first stepped structure; and forming a second stepped structure in the stack by etching the stack using the polymer mask as an etching barrier.
Inventor(s): Kyung Beom SEO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jong Kyu MOON of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L21/56, H01L23/00, H01L25/065
CPC Code(s): H01L21/566
Abstract: a method of manufacturing a semiconductor package includes disposing semiconductor chips over a substrate. the method also includes forming a dam surrounding the semiconductor chips, the dam providing a reservoir in a perimeter region of the substrate. the method further includes forming a molding layer encapsulating the semiconductor chips on the substrate. the extrusion flowing out from the molding layer is contained in the reservoir while being blocked by the dam.
Inventor(s): Nam Jae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528, H01L23/532
CPC Code(s): H01L23/5226
Abstract: a semiconductor device includes: a first interconnection structure; and a second interconnection structure including a first wiring part electrically connected to the first interconnection structure, a first hard mask pattern on the first wiring part, and a first via part connected to the first wiring part through the first hard mask pattern.
20240305312. CODING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Minseo KIM of Seoul (KR) for sk hynix inc., Jongsun Park of Seoul (KR) for sk hynix inc., Jinho Jeong of Icheon (KR) for sk hynix inc.
IPC Code(s): H03M13/11, H03M13/15
CPC Code(s): H03M13/1177
Abstract: a coding circuit includes an encoder circuit configured to generate an input codeword by concatenating an input data and a parity generated by processing the input data using an odd parity generator matrix; and a decoder circuit configured to correct a double error from an output codeword, and to detect a triple error using a syndrome generated by processing the output codeword using the odd parity generator matrix, wherein each column of the odd parity generator matrix has a respective odd number of 1's.
Inventor(s): Won Geun CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Seok Min CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Rho Gyu KWAK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., In Su PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H01L23/528, H10B41/10, H10B41/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: a semiconductor device may include: a gate structure including conductive layers and insulating layers that are alternately stacked. tapered supports formed in the gate structure layers have a first width at a first level of the layers and a second width smaller than the first width at a second level of the layers. a tapered contact structure is located between the tapered supports in the gate structure having a third width at the first level and a fourth width larger than the third width at the second level. the gate structure taper and the contact structure taper are “mirror images” of each other.
20240306387. MEMORY DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Hye Yeong JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jae Taek KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B43/40
CPC Code(s): H10B43/27
Abstract: a memory device, and a method of manufacturing the memory device, includes a source structure and a contact plug spaced apart from the source structure. a portion of the source structure facing the contact plug is formed to be concave.
- SK hynix Inc.
- G01K7/18
- G01K7/20
- CPC G01K7/183
- Sk hynix inc.
- G06F3/06
- CPC G06F3/0619
- CPC G06F3/0632
- CPC G06F3/064
- CPC G06F3/0655
- CPC G06F3/0656
- G06F7/24
- G06F7/02
- CPC G06F7/24
- G06F9/48
- CPC G06F9/4881
- G06F11/07
- CPC G06F11/076
- G06F12/0804
- CPC G06F12/0804
- G06F12/0806
- CPC G06F12/0806
- G11C7/10
- G11C11/56
- CPC G11C7/1006
- G11C16/10
- G11C16/04
- G11C16/34
- CPC G11C16/10
- G11C16/26
- G11C5/14
- G11C16/08
- CPC G11C16/26
- G11C29/46
- G11C7/02
- G11C29/12
- CPC G11C29/46
- H01L21/311
- H01L21/033
- CPC H01L21/31144
- H01L21/56
- H01L23/00
- H01L25/065
- CPC H01L21/566
- H01L23/522
- H01L21/768
- H01L23/528
- H01L23/532
- CPC H01L23/5226
- H03M13/11
- H03M13/15
- CPC H03M13/1177
- H10B43/27
- H10B41/10
- H10B41/27
- H10B43/10
- CPC H10B43/27
- H10B43/40
