SK hynix Inc. patent applications on October 17th, 2024
Patent Applications by SK hynix Inc. on October 17th, 2024
SK hynix Inc.: 23 patent applications
SK hynix Inc. has applied for patents in the areas of G06F3/06 (6), H10B43/27 (4), G06F12/02 (2), G11C7/10 (2), G11C7/22 (2) H10B43/27 (2), G06F1/3275 (1), G11C11/40618 (1), H10B61/00 (1), H10B43/35 (1)
With keywords such as: memory, device, structure, circuit, layer, data, including, gate, configured, and source in patent application abstracts.
Patent Applications by SK hynix Inc.
20240345648. STORAGE DEVICE AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Woo Sick CHOI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F1/3234, G06F1/3225, G11C5/14
CPC Code(s): G06F1/3275
Abstract: a storage device can decrease a leakage current. the storage device includes: a plurality of power switch cells for controlling power supplied to a memory device and a memory controller for controlling the memory device; a power management circuit for providing the plurality of power switch cells with a power voltage corresponding to the power; and a power management circuit controller for controlling the power management circuit to determine a magnitude of the power voltage according to whether the plurality of power switch cells supply the power to the memory device and the memory controller.
Inventor(s): Seung Kyu HONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0608
Abstract: a storage device may include: a nonvolatile memory device including a plurality of memory blocks; and a memory controller for providing an external device with block count information including bitmap information representing whether an erase number of each of the plurality of memory blocks is equal to or greater than a reference value, performing an erase operation on a memory block in which data corresponding to a write command received from the external device is to be stored before the write command is executed, storing the data in the nonvolatile memory device, updating the block count information, and providing the updated block count information to the external device.
Inventor(s): Byoung Min JIN of Gyeonggi-do (KR) for sk hynix inc., Ku Ik KWON of Gyeonggi-do (KR) for sk hynix inc., Gyu Yeul HONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06, G06F12/12
CPC Code(s): G06F3/0617
Abstract: the storage device may receive a condition for a down-time mode from the host. the storage device may cache, when the condition for the down-time mode is determined as satisfied, at least a part of update data units in the update cache. the storage device may process a read command received from the host in the down-time mode based on update data units cached in the update cache.
20240345749. MEMORY SYSTEM AND OPERATION METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Jung Hyun KWON of Gyeonggi-do (KR) for sk hynix inc., Dong Gun KIM of Gyeonggi-do (KR) for sk hynix inc., Min Seob LEE of Gyeonggi-do (KR) for sk hynix inc., Kwang Hyo JEONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0634
Abstract: a memory system includes a memory device comprising plural memory groups, and a controller configured to independently set or adjust a page close time or a page open time for a row or a page in each of the plural memory groups based on whether there is a request to be transferred into each of the plural memory groups.
Inventor(s): Chan Hee LEE of Icheon (KR) for sk hynix inc., Jin Su Park of Icheon (KR) for sk hynix inc., Myeong Jae Kim of Icheon (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: embodiments of the present disclosure may provide measures for performing tuning of signals transmitted and received by a storage device, by providing a test signal provided by a test signal generator included in the storage device to a loopback path between a transmission block and a reception block of the storage device. by easily performing signal tuning of the storage device and preventing or reducing distortion of signals transmitted and received by the storage device, operational performance of the storage device may be improved.
Inventor(s): Yoon Jae SHIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Min Jeong KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a semiconductor device includes an internal voltage control circuit including an amplifier circuit and a plurality of drivers. the internal voltage control circuit is configured to drive an internal voltage through the sharing of the amplifier circuit and a driver that is activated, among the plurality of drivers, after the start of a standby operation and an active operation. the semiconductor device also includes a core circuit including a plurality of banks. the core circuit is configured to perform an operation of a bank that is activated, among the plurality of banks, by receiving the internal voltage.
20240345771. CONTROLLER, STORAGE DEVICE AND COMPUTING SYSTEM_simplified_abstract_(sk hynix inc.)
Inventor(s): Chi Je PARK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: according to embodiments of the present disclosure, a storage device may externally provide device information according to a memory state associated with a memory operation performed by an internal command during an idle period, and operate in an idle mode according to an idle period set according to the memory state.
Inventor(s): Joo Young LEE of Icheon (KR) for sk hynix inc., Hoe Seung Jung of Icheon (KR) for sk hynix inc.
IPC Code(s): G06F12/0877
CPC Code(s): G06F12/0877
Abstract: according to embodiments of the present disclosure, if write operations for a memory block with efficient write operations according to a cache program mode and a memory block with a different property are mixed, the write operation is performed by switching the cache program mode to a normal program mode. accordingly, it is possible to prevent or reduce performance degradation of the cache program mode due to a workload in which write operations of different property are mixed, thereby improving write operation efficiency.
Inventor(s): Andrey Kuyel of Minsk (BY) for sk hynix inc.
IPC Code(s): G06F12/0882, G06F16/22
CPC Code(s): G06F12/0882
Abstract: a system for searching for pages of a memory device based on a b+ tree node structure. the system includes a memory device and a controller including a cache memory and a search accelerator. the search accelerator receives a key-value pair associated with a target page among a plurality of pages; and searches for the target page from the cache memory based on the key-value pair, using a tree structure including b+ tree nodes mapped to the plurality of pages. the key-value pair includes a searched key and a value indicating a pointer to a tree node mapped to the target page, among the b+ tree nodes.
Inventor(s): Chan Keun KWON of Gyeonggi-do (KR) for sk hynix inc., Hyeon Cheon SEOL of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/10, G11C7/22
CPC Code(s): G11C7/1069
Abstract: a memory system comprising a first memory device configured to compress, into first compression data, data read from a first memory region included therein, and output the first compression data through first selection lines among first output lines in response to a first clock, a second memory device configured to compress, into second compression data, data read from a second memory region included therein, and output the second compression data through second selection lines among second output lines in response to a second clock; and a first parallel transmission unit configured to simultaneously connect the first and second selection lines to third output lines, select, as a selection clock, one having a lagging phase to the other between the first clock and the second clock, and transmit the first and second compression data in parallel through the third output lines in response to the selection clock.
Inventor(s): Chan Keun KWON of Gyeonggi-do (KR) for sk hynix inc., Se Jin KANG of Gyeonggi-do (KR) for sk hynix inc., In Seok KONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/22, G11C7/10
CPC Code(s): G11C7/222
Abstract: a signal transmission circuit comprising: a first data transmission circuit configured to output, through a first data output node thereof and in response to a first operation clock applied to a first clock input node thereof, first output data obtained by sensing and amplifying a first input data pair applied to a first differential input node pair thereof, a clock transmission circuit configured to output through a second data output node thereof, a second operation clock generated in response to the first operation clock applied to a second clock input node thereof while a power supply voltage and a ground voltage are applied to a second differential input node pair thereof, and a first data output circuit configured to output the first output data in synchronization with the second operation clock, wherein the first data transmission circuit is modeled on the clock transmission circuit.
Inventor(s): Hyun Seung KIM of Gyeonggi-do (KR) for sk hynix inc., Sung Je ROH of Gyeonggi-do (KR) for sk hynix inc., Kang Seol LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/406, G11C11/408
CPC Code(s): G11C11/40603
Abstract: a memory device includes an active control circuit configured to generate an internal active signal and an internal precharge signal according to one of an active command and a precharge command, and generate a row active signal according to the active command, the internal active signal, the precharge command, and the internal precharge signal; an address control circuit configured to generate a row address corresponding to an active address and an adjacent address adjacent to the active address; and a row control circuit configured to activate at least one word line corresponding to the row address according to the row active signal.
Inventor(s): Young Ook SONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/406, G11C11/4078
CPC Code(s): G11C11/40618
Abstract: a memory system includes a memory device including banks each including a plurality of rows, and configured to select, within a selected bank of the banks, at least one row from the plurality of rows based on a target address; and a row-hammer tracking module configured to: select the selected bank based on a pattern of accesses to each of the banks, and select the target address according to an access number for each of a plurality of groups of the rows within the selected bank.
Inventor(s): Byung Woo SONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Ki Cheol SON of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/22, G11C16/04
CPC Code(s): G11C16/22
Abstract: a memory may include: a cell string including memory cells connected between a bit line and a source line; a watchdog circuit detecting a failing of a reset operation as a fail; and a reset control circuit controlling an operation that protects data of the memory cells in response to the detection of the fail by the watchdog circuit and activating a reset signal.
Inventor(s): Byung Ho LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/544, H01L21/68
CPC Code(s): H01L23/544
Abstract: a bonding structure may include a first wafer, a second wafer, at least one first alignment key and a second alignment key. the first wafer may include first bonding pads. the second wafer may include second bonding wafers bonded to the first bonding pads. the first alignment key may be provided to the first wafer. the first alignment key may have a temporary magnetism by an induced current. the second alignment key may be provided to the second wafer. the second alignment key may correspond to the first alignment key.
Inventor(s): Young Gwang YOON of Gyeonggi-do (KR) for sk hynix inc., Yun Ik SON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/40, H01L29/51, H01L29/66, H01L29/78
CPC Code(s): H01L27/0922
Abstract: a semiconductor device includes a first gate structure including a first n-type high-k gate dielectric layer, a second gate structure comprising a first p-type high-k gate dielectric layer, a third gate structure including a second n-type high-k gate dielectric layer, and a fourth gate structure including a second p-type high-k gate dielectric layer. the first n-type high-k gate dielectric layer includes an n-type dipole material with a first concentration. the first p-type high-k gate dielectric layer includes a p-type dipole material with a second concentration. the second n-type high-k gate dielectric layer includes the n-type dipole material with a third concentration. the second p-type high-k gate dielectric layer includes the p-type dipole material with a fourth concentration. the first concentration is higher than the third concentration, and the second concentration is higher than the fourth concentration.
Inventor(s): Ji Hyo KANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hyun Bae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H03K19/00, H03K17/687
CPC Code(s): H03K19/0005
Abstract: a buffer circuit may include a buffer unit including a first resistor connected between a power source terminal and a first node, a first inductor set connected between the first node and a first input terminal, a second resistor connected between the power source terminal and a second node, and a second inductor set connected between the second node and a second input terminal, and a first variable capacitance circuit connected between the first node and the second node, and configured to adjust a first capacitance value according to a plurality of first adjustment signals.
20240349488. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Seung Wook RYU of Gyeonggi-do (KR) for sk hynix inc., Wan Sup SHIN of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/36
Abstract: a semiconductor memory device includes: a conductive line stack including a plurality of first conductive lines that are stacked over a substrate in a direction perpendicular to a surface of the substrate; conductive pads extending laterally from edge portions of the first conductive lines, respectively; and contact plugs coupled to the conductive pads, respectively.
20240349502. MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Seok Min JEON of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Min Ho LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Seong Man JEON of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Tae Hong GWON of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Sung Soon KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Ji Seong KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Ki Gab YEON of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Sang Seob LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: a memory device includes first and second material layers alternately stacked; a vertical hole passing through the first and second material layers; first insulating patterns protruding from a side surface of the first material layers exposed through the vertical hole; a blocking layer formed along a surface of the second material layers exposed between the first insulating patterns, the blocking layer comprising a plurality of concave portions, each of which is between the first insulating patterns; and charge trap patterns formed in the concave portions, wherein portions of the blocking layer exposed between the charge trap patterns, wherein a tunnel insulating layer, a channel layer, and a core pillar, are formed in an area that is substantially surrounded by the charge trap patterns.
20240349503. MEMORY DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Won Geun CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Rho Gyu KWAK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Seok Min CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27
CPC Code(s): H10B43/27
Abstract: there are provided a memory device and a manufacturing method of a memory device. the memory device includes a plurality of conductive layers, support structures penetrating the plurality of conductive layers, a contact hole exposing any one of the plurality of conductive layers and any one of the plurality of support structures, and a contact disposed in the contact hole.
Inventor(s): Nam Jae LEE of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10B43/35, H01L23/00, H01L25/00, H01L25/065, H01L25/18, H10B41/27, H10B41/35, H10B43/27, H10B80/00
CPC Code(s): H10B43/35
Abstract: a semiconductor device includes a gate structure located between a bit line and a source structure, the gate structure including stacked word lines. the semiconductor device also includes a select line structure located between the gate structure and the source structure, the select line structure including an epitaxial pattern and a silicide layer. the semiconductor device further includes a channel structure extending through the gate structure and the select line structure, the channel structure connected between the source structure and the bit line.
Inventor(s): Tae Jung HA of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10B61/00
CPC Code(s): H10B61/00
Abstract: a semiconductor device includes: a first contact plug disposed over the substrate; two or more insulating patterns disposed on a side surface of the first contact plug and sequentially along a direction away from the first contact plug; and a memory pattern connected to the first contact plug, wherein an upper surface of the first contact plug and upper surfaces of the insulating patterns form an inclined surface whose height decreases as a distance from a center of the first contact plug increases, the inclined surface includes a first inclined surface disposed on a first side of the center of the first contact plug and a second inclined surface disposed on second side of the center of the first contact plug, the second side opposite to the first side, and the memory pattern has a lower surface in contact with the first inclined surface.
20240349517. SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Ki Hong LEE of Suwon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B69/00, H01L23/522, H01L23/528, H10B41/27, H10B41/41, H10B41/50, H10B43/27, H10B43/40, H10B43/50
CPC Code(s): H10B69/00
Abstract: a semiconductor device may include a source layer, a stack structure, a channel layer, a slit, and a source pick-up line. the source layer may include at least one groove in an upper surface thereof. the stack structure may be formed over the source layer. the channel layer may pass through the stack structure. the channel layer may be in contact with the source layer. the slit may pass through the stack structure. the slit may expose the groove of the source layer therethrough. the source pick-up line may be formed in the slit and the groove. the source pick-up line may be contacted with the source layer.
- SK hynix Inc.
- G06F1/3234
- G06F1/3225
- G11C5/14
- CPC G06F1/3275
- Sk hynix inc.
- G06F3/06
- G06F12/02
- CPC G06F3/0608
- G06F12/12
- CPC G06F3/0617
- CPC G06F3/0634
- CPC G06F3/0653
- CPC G06F3/0655
- CPC G06F3/0659
- G06F12/0877
- CPC G06F12/0877
- G06F12/0882
- G06F16/22
- CPC G06F12/0882
- G11C7/10
- G11C7/22
- CPC G11C7/1069
- CPC G11C7/222
- G11C11/406
- G11C11/408
- CPC G11C11/40603
- G11C11/4078
- CPC G11C11/40618
- G11C16/22
- G11C16/04
- CPC G11C16/22
- H01L23/544
- H01L21/68
- CPC H01L23/544
- H01L27/092
- H01L21/8238
- H01L29/40
- H01L29/51
- H01L29/66
- H01L29/78
- CPC H01L27/0922
- H03K19/00
- H03K17/687
- CPC H03K19/0005
- H10B12/00
- CPC H10B12/36
- H10B43/27
- H10B43/10
- CPC H10B43/27
- H10B43/35
- H01L23/00
- H01L25/00
- H01L25/065
- H01L25/18
- H10B41/27
- H10B41/35
- H10B80/00
- CPC H10B43/35
- H10B61/00
- CPC H10B61/00
- H10B69/00
- H01L23/522
- H01L23/528
- H10B41/41
- H10B41/50
- H10B43/40
- H10B43/50
- CPC H10B69/00
