SK hynix Inc. patent applications on October 10th, 2024
Patent Applications by SK hynix Inc. on October 10th, 2024
SK hynix Inc.: 26 patent applications
SK hynix Inc. has applied for patents in the areas of H01L25/065 (5), H10B63/00 (4), H01L23/00 (3), G06F13/16 (3), H01L25/18 (3) H01L25/0657 (3), H10B43/27 (2), G06F3/061 (1), H10B63/845 (1), H10B63/80 (1)
With keywords such as: memory, layer, data, device, signal, semiconductor, conductive, including, circuit, and refresh in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): In Hyuk PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/061
Abstract: a storage device may group a plurality of zone clusters, each cluster including at least one zone. the storage device may then store target data in a target zone cluster. for example, the storage device may determine a target zone for storing target data, using the sum of a write count and a seed value for the target zone cluster.
Inventor(s): Seung Soo KIM of Gyeonggi-do (KR) for sk hynix inc., Hyeong Jae CHOI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a storage device may receive a write command which requests to write target data and includes an identifier for the target data, a size of the target data, and a flag indicating that the target data is cold data. the storage device may write the target data to one or more consecutive target memory blocks among the plurality of memory blocks.
Inventor(s): Dong Uk LEE of Seoul (KR) for sk hynix inc., Seung Gyu JEONG of Gwangmyeong (KR) for sk hynix inc., Dong Ha JUNG of Yongin (KR) for sk hynix inc.
IPC Code(s): G06F9/30, G06F9/48, G06F12/02, G06F12/0882, G06F13/16, G11C5/02, G11C11/4093, G11C29/42, G11C29/44
CPC Code(s): G06F9/30047
Abstract: a data processing system includes a compute blade generating a write command to store data and a read command to read the data, and a memory blade. the compute blade has a memory that stores information about performance characteristics of each of a plurality of memories, and determines priority information through which eviction of a cache line is carried out based on the stored information.
20240338314. MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): In Sung SONG of Icheon-si (KR) for sk hynix inc., Dong Hwan KOO of Icheon-si (KR) for sk hynix inc., Ki Tae KIM of Icheon-si (KR) for sk hynix inc., Chan Sik KIM of Icheon-si (KR) for sk hynix inc., Dong Young SEO of Icheon-si (KR) for sk hynix inc., Woong Sik SHIN of Icheon-si (KR) for sk hynix inc., In Ho JUNG of Icheon-si (KR) for sk hynix inc., Jae Hoon HEO of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F12/02, G06F13/16
CPC Code(s): G06F12/0253
Abstract: the present technology relates to an electronic device. according to the present technology, a memory controller may include a garbage collection controller and a sustain detector. the garbage collection controller may generate garbage collection information including valid page count values of victim memory blocks on which garbage collection is to be performed among a plurality of memory blocks included in a memory device. the sustain detector in communication with the garbage collection controller may generate sustain information indicating whether random write performance for the memory device is in a sustain state in which a random write performance value related to a capability of the random write performance is greater than or equal to a threshold value based on the garbage collection information.
Inventor(s): Sung Hyun HONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F13/16, G06F13/42
CPC Code(s): G06F13/1673
Abstract: a data processing system includes a plurality of memory devices including a first memory device and a second memory device, and a fabric instance including a buffer. the fabric instance is configured to receive write data including first data and second data from the at least one host; store the second data in the buffer; transfer the first data to the first memory device; and transfer the second data from the buffer to the second memory device at a preset timing after transferring the first data.
20240339134. STACKED SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Jae Hyung PARK of Gyeonggi-do (KR) for sk hynix inc., Seung Geun BAEK of Gyeonggi-do (KR) for sk hynix inc., Dong Uk LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C5/02, G11C8/10, H01L25/065, H01L25/18
CPC Code(s): G11C5/02
Abstract: a stacked semiconductor device includes at least one upper chip including a plurality of channels each including first and second pseudo-channels; and a plurality of transfer control circuits respectively corresponding to the channels and each configured to output channel commands according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel of the channels, and transmit first and second data words between the corresponding channel and a lower chip according to the channel commands.
Inventor(s): Yong Jin JEONG of Icheon (KR) for sk hynix inc., Sang Gu YEO of Icheon (KR) for sk hynix inc.
IPC Code(s): G11C5/06, H10B63/00, H10N70/00
CPC Code(s): G11C5/063
Abstract: a semiconductor device may include a first contact plug, a word line electrically connected to the first contact plug and extending in a first direction, a second contact plug, a bit line extending in a second direction that intersects the first direction, and a memory cell disposed between the word line and the bit line and including a variable resistance layer. the bit line may include a first protruding part that protrudes into the memory cell, a second protruding part that is connected to the second contact plug, and a connection part that connects the first protruding part and the second protruding part and that extends in the second direction.
Inventor(s): Saeng Hwan KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/406, G11C11/4096
CPC Code(s): G11C11/40615
Abstract: a memory system includes: a memory controller configured to: issue a normal refresh command and a refresh management command, and adjust, based on a replacement counting value, an issuance frequency of at least one of the normal refresh command and the refresh management command; and a memory device configured to: perform a first refresh operation corresponding to the normal refresh h command and a second refresh operation corresponding to the refresh management command, and replace the second refresh operation with the first refresh operation according to a memory information signal, count a number of times of the replacing to generate the replacement counting value, and provide the replacement counting value.
Inventor(s): Saeng Hwan KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/406, G11C11/4072
CPC Code(s): G11C11/40618
Abstract: a memory device includes a memory cell array including row-hammer cells configured to store a number of accesses of a corresponding row of a plurality of rows; an address control circuit configured to generate consecutive first and second refresh addresses according to a normal refresh command, wherein the first refresh address indicates an odd-numbered row during a first refresh cycle and an even-numbered row during a second refresh cycle; and a refresh control circuit configured to refresh, according to the normal refresh command, first and second rows respectively corresponding to the first and second refresh addresses and selectively initialize the row-hammer cells of the first row while refreshing the first row.
20240339155. SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Jeong Hwan SONG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/003
Abstract: in one embodiment, a semiconductor device includes: a memory cell array including a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, and a plurality of memory cells disposed at intersections between the first conductive lines and the second conductive lines; a first driver coupled to the first conductive lines and configured to drive the first conductive lines; a second driver coupled to the second conductive lines and configured to drive the second conductive lines; a first resistor coupled in series to each of the first conductive lines and between the first driver and the first conductive lines; and a first switching element coupled in a conductive path that is in parallel to the first resistor and is between the first driver and the first conductive lines and operable to turn on or off the conductive path.
Inventor(s): Jeong Ho JEON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/08, G11C16/04, G11C16/08
CPC Code(s): G11C29/08
Abstract: a method of operating a host device according to the present technology includes determining an area to be tested among a mapped area and an unmapped area included in a storage area of a storage device, generating a test request corresponding to the determined area, and transmitting the generated test request to the storage device.
Inventor(s): Dong Sop LEE of Icheon-si (KR) for sk hynix inc., Tae Ho LIM of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G11C29/52, H03M13/00, H03M13/11
CPC Code(s): G11C29/52
Abstract: a phase-change memory controller controls a phase-change memory device. the phase-change memory controller includes a write control circuit configured to receive first write data of “n” bits (where “n” is a natural number greater than 2) to be written to the phase-change memory device to generate second write data composed of compressed data compressed with “m” bits (where “n” is a natural number smaller than “n”) and “0” padding data in which the rest “n-m” bits are filled with “0”.
Inventor(s): Ki Yong LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L25/065, H01L23/00, H01L25/18
CPC Code(s): H01L25/0657
Abstract: a semiconductor package includes a package substrate, a plurality of memory chips stacked over the package substrate, and a control chip disposed over the package substrate to be spaced apart from the plurality of memory chips. the control chip includes a plurality of first chip enable signal control pads transmitting chip enable signals to and from the plurality of memory chips, a plurality of second chip enable signal control pads transmitting the chip enable signals to and from an external electronic device external to the semiconductor package, a chip enable signal control circuit configured to control transmission paths of the chip enable signals between the plurality of first chip enable signal control pads and the plurality of second chip enable signal control pads, and a third chip enable signal control pad receiving a path control signal from the external electronic device for controlling the chip enable signal control circuit.
20240339436. STACK PACKAGES_simplified_abstract_(sk hynix inc.)
Inventor(s): Eun Hye DO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chang Shik JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L25/065, H01L23/00, H10B80/00
CPC Code(s): H01L25/0657
Abstract: a stack package is provided. the stack package includes a package substrate on which a first bond finger and a second bond finger are spaced apart from each other, and a second semiconductor die stacked over a first semiconductor die. a first connector connects the first semiconductor die to the first bond finger. a second connector connects the second semiconductor die to the second bond finger and extends to have substantially the same length as the first connector.
20240339438. STACKED SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Jae Hyung PARK of Gyeonggi-do (KR) for sk hynix inc., Seung Geun BAEK of Gyeonggi-do (KR) for sk hynix inc., Dong Uk LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L25/065, G11C11/408, G11C11/4093, G11C11/4096, H10B80/00
CPC Code(s): H01L25/0657
Abstract: a stacked semiconductor device includes at least one upper chip including first and second channels, each including first and second pseudo-channels; and first and second transfer control circuits respectively corresponding to the first and second channels, each configured to select one of the first and second pseudo-channels according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel, and transfer a data word between the selected pseudo-channel and a lower chip, wherein the first transfer control circuit transfers the data word in a first order in units of bytes, and the second transfer control circuit transfers the data word in a second order in units of bytes, opposite to the first order.
Inventor(s): Nam Jae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L29/417, H01L29/10
CPC Code(s): H01L29/41741
Abstract: a semiconductor device includes a stacked structure with first conductive layers and insulating layers that are stacked alternately with each other, second conductive layers located on the stacked structure, first openings passing through the second conductive layers and the stacked structure and having a first width, second conductive patterns formed in the first openings and located on the stacked structure to be electrically coupled to the second conductive layers, data storage patterns formed in the first openings and located under the second conductive patterns, and channel layers formed in the data storage patterns and the second conductive patterns.
Inventor(s): Ji Hyo KANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Kyung Hoon KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H03K19/0185, G06F1/06, G06F1/10, G06F1/12, H03K17/687
CPC Code(s): H03K19/018521
Abstract: a semiconductor apparatus includes a clock distribution network, a data output circuit, and a data input circuit. the clock distribution network receives a system clock signal and drives the system clock signal to a cmos level and a cml level to signal in different manners. the data output circuit outputs data based on the clock signal driven to the cmos level. the data input circuit receives data based on the clock signal driven to the cml level.
Inventor(s): Seung Tak RYU of Daejeon (KR) for sk hynix inc., Chang Yeop LEE of Daejeon (KR) for sk hynix inc., Jun Ho CHEON of Icheon-si (KR) for sk hynix inc., Woo Yeong CHO of Icheon-si (KR) for sk hynix inc., GEON KO of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H03M3/00, G06N3/08, G11C11/54, G11C13/00
CPC Code(s): H03M3/322
Abstract: disclosed are a sigma-delta modulator that directly converts a current signal into digital data, an adc utilizing the sigma-delta modulator, and a neural network computing system utilizing the adc. the sigma-delta modulator includes: a delta circuit to generate a differential current between an analog current signal output from a resistive memory and a first current included in the analog current signal, the first current having an amount of current determined by a digital modulation signal; an integration circuit to generate an integration current by integrating the differential current; and a quantization circuit to generate the digital modulation signal corresponding to the integration current. the sigma-delta modulator can minimize the generation of noise by using no capacitor that performs a function by a switch, and can increase a signal processing speed for conversion by allowing the signal processing speed to be determined by a signal processing speed of one element.
Inventor(s): Junghan LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N25/709, H03K5/24, H04N25/77
CPC Code(s): H04N25/709
Abstract: a comparison circuit and an image sensing device including the same are disclosed. the comparison circuit includes a comparison block configured to include a comparator that compares signals of input nodes with each other within a first period and outputs a signal corresponding to a result of the comparison to an output node and configured to initialize the comparator by allowing a voltage of the output node to be fed back to an input terminal of the comparator within a second period, and a stabilization circuit configured to supply a first voltage to the output node within the second period. in the second period, the stabilization circuit is connected to the output node to supply the first voltage. in the first period, connection between the stabilization circuit and the output node is cut off.
Inventor(s): Seung Hwan KIM of Gyeonggi-do (KR) for sk hynix inc., Seok Pyo SONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/033
Abstract: a method for fabricating a semiconductor device includes: forming a stack body including first sacrificial layer structures, preliminary horizontal layers, and second sacrificial layer structures over a lower structure; forming a main hard mask layer over the stack body; forming a mesh-shaped hard mask pattern over the main hard mask layer; forming a main hard mask pattern by etching the main hard mask layer using the mesh-shaped hard mask pattern as an etch barrier; forming a plurality of isolation openings by etching the stack body using the main hard mask pattern as an etch barrier; and forming a plurality of isolation layers that fill the isolation openings.
Inventor(s): Gil Seop KIM of Gyeonggi-do (KR) for sk hynix inc., Seung Hwan KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/30
Abstract: a semiconductor device includes: a lower structure; a first cell isolation layer and a second cell isolation layer stacked in a direction perpendicular to the lower structure and each including a void; a horizontal layer disposed between the first cell isolation layer and the second cell isolation layer; a first horizontal conductive line disposed between the first cell isolation layer and the horizontal layer, and a second horizontal conductive line disposed between the second cell isolation layer and the horizontal layer; a vertical conductive line coupled to a first side of the horizontal layer; and a data storage element including a first electrode coupled to a second side of the horizontal layer, and disposed between the first cell isolation layer and the second cell isolation layer.
Inventor(s): Nam Jae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H01L23/522, H10B41/27, H10B41/40, H10B43/40
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stacked body, an insulating layer overlapping the gate stacked body, a first source layer including a horizontal portion between the gate stacked body and the insulating layer and a protrusion extending from the horizontal portion so as to penetrate the insulating layer, a channel layer penetrating the gate stacked body and extending into the horizontal portion of the first source layer, a first memory pattern between the channel layer and the gate stacked body, and a second source layer disposed between the gate stacked body and the first source layer and coming in contact with the channel layer.
Inventor(s): Dong Hwan LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Seo Hyun KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Eun Seok CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H01L23/00, H01L25/00, H01L25/065, H01L25/18, H10B41/27, H10B41/41, H10B43/40
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. the semiconductor memory device includes a channel layer with a first portion and a second portion, the first portion and the second portion extending in a longitudinal direction, a gate stacked structure surrounding the first portion of the channel layer, a first semiconductor layer of a first conductivity type that contacts the second portion of the channel layer, and a second semiconductor layer of a second conductivity type.
Inventor(s): Woo Tae LEE of Icheon (KR) for sk hynix inc.
IPC Code(s): H10B63/00
CPC Code(s): H10B63/80
Abstract: a semiconductor device may include a word line that extends in a first direction, a bit line that extends in a second direction that intersects the first direction, a variable resistance pattern that is disposed between the word line and the bit line and that has a first width in the first direction and a second width in the second direction, wherein the first width and the second width are different from each other, and an electrode pattern that is disposed between the variable resistance pattern and the bit line and that has a third width in the first direction and a fourth width in the second direction, wherein the third width and the fourth width are different from each other.
Inventor(s): Yoon Mo Koo of Icheon (KR) for sk hynix inc., Hyung Dong Lee of Icheon (KR) for sk hynix inc.
IPC Code(s): H10B63/00, H10B63/10
CPC Code(s): H10B63/845
Abstract: a semiconductor device may include: a first access line extending in a first direction; a second access line extending in a second direction intersecting the first direction; and a memory cell connected between the first access line and the second access line and including an electrode including a dielectric barrier therein.
Inventor(s): Tae Jung HA of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10N70/00, H10B63/00
CPC Code(s): H10N70/826
Abstract: semiconductor devices and fabrication methods of semiconductor devices are disclosed. in an embodiment, a semiconductor device may include a plurality of memory cells, and each of the plurality of memory cells may include: a resistive layer including a material having a specific resistance and including a lower portion and an upper portion disposed over the lower portion, wherein a width of the lower portion is smaller than a width of an uppermost surface of the upper portion; a selector layer disposed over the resistive layer and structured to perform a threshold switching by exhibiting different electrically conductive states in response to an applied voltage relative to a threshold voltage; and a memory layer disposed over the selector layer and structured to store data.
- SK hynix Inc.
- G06F3/06
- CPC G06F3/061
- Sk hynix inc.
- CPC G06F3/064
- G06F9/30
- G06F9/48
- G06F12/02
- G06F12/0882
- G06F13/16
- G11C5/02
- G11C11/4093
- G11C29/42
- G11C29/44
- CPC G06F9/30047
- CPC G06F12/0253
- G06F13/42
- CPC G06F13/1673
- G11C8/10
- H01L25/065
- H01L25/18
- CPC G11C5/02
- G11C5/06
- H10B63/00
- H10N70/00
- CPC G11C5/063
- G11C11/406
- G11C11/4096
- CPC G11C11/40615
- G11C11/4072
- CPC G11C11/40618
- G11C13/00
- CPC G11C13/003
- G11C29/08
- G11C16/04
- G11C16/08
- CPC G11C29/08
- G11C29/52
- H03M13/00
- H03M13/11
- CPC G11C29/52
- H01L23/00
- CPC H01L25/0657
- H10B80/00
- G11C11/408
- H01L29/417
- H01L29/10
- CPC H01L29/41741
- H03K19/0185
- G06F1/06
- G06F1/10
- G06F1/12
- H03K17/687
- CPC H03K19/018521
- H03M3/00
- G06N3/08
- G11C11/54
- CPC H03M3/322
- H04N25/709
- H03K5/24
- H04N25/77
- CPC H04N25/709
- H10B12/00
- CPC H10B12/033
- CPC H10B12/30
- H10B43/27
- H01L23/522
- H10B41/27
- H10B41/40
- H10B43/40
- CPC H10B43/27
- H01L25/00
- H10B41/41
- CPC H10B63/80
- H10B63/10
- CPC H10B63/845
- CPC H10N70/826
