SK hynix Inc. patent applications on May 30th, 2024
Patent Applications by SK hynix Inc. on May 30th, 2024
SK hynix Inc.: 38 patent applications
SK hynix Inc. has applied for patents in the areas of G06F3/06 (8), G06F3/0679 (7), G11C16/10 (7), G06F3/0659 (7), G11C16/08 (6)
With keywords such as: memory, device, voltage, circuit, program, configured, cells, data, semiconductor, and layer in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Suk Won PARK of Gyeonggi-do (KR) for sk hynix inc., Chan Ha PARK of Gyeonggi-do (KR) for sk hynix inc., Sang Ho LEE of Gyeonggi-do (KR) for sk hynix inc., Chang Moon LIM of Gyeonggi-do (KR) for sk hynix inc., Tae Kwon JEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G03F1/24, G03F1/48, G03F1/54
Abstract: an extreme ultraviolet (euv) mask includes: a reflective layer over a substrate; a capping layer including a porous hydrogen trapping layer over the reflective layer; and an absorption layer over the capping layer.
[[20240176339.METHOD OF PREDICTING AN OPTIMAL PROCESS CONDITION MODEL TO IMPROVE A YIELD OF A SEMICONDUCTOR FABRICATION PROCESS AND METHOD OF CONTROLLING A SEMICONDUCTOR FABRICATION PROCESS BASED ON AN OPTIMAL PROCESS CONDITION MODEL_simplified_abstract_(sk hynix inc.)]]
Inventor(s): Jin Hee HAN of Icheon-si (KR) for sk hynix inc., Seong Min MA of Icheon-si (KR) for sk hynix inc., Deuk Nyeon LEE of Icheon-si (KR) for sk hynix inc., Chang Hwan LEE of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G05B19/418
Abstract: in a method of predicting an optimal process condition model for a semiconductor fabrication process, process parameter information of a unit process in the semiconductor fabrication process may be collected. first characteristics information of objects to be processed before the unit process and second characteristic information of processed objects after the unit process may be extracted. process global uniformity (pgu) may be calculated using the first characteristic information and the second characteristic information. a data set of the unit process may be created using the process parameter information and the pgu. a virtual process environment function of the unit process may be created using the data set. the optimal process condition model of the unit process may be created using the virtual process environment function.
20240176372.VOLTAGE REGULATOR_simplified_abstract_(sk hynix inc.)
Inventor(s): Jung Han LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G05F1/46, G05F1/575
Abstract: a voltage regulator includes a voltage generator configured to receive a reference voltage and a feedback voltage and configured to generate an output voltage corresponding to the feedback voltage, a voltage divider configured to divide the output voltage to generate the feedback voltage, and a controller configured to control a voltage division value of the voltage divider in response to a program enable signal and a charge-pump enable signal during an activation period of an enable signal.
Inventor(s): In Jong JANG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F1/3225, G06F1/3296
Abstract: a storage device may enter a plurality of intermediate power states sequentially while entering from a first power state to a second power state. the storage device may check background flag information while entering each of the plurality of intermediate power states, and execute a target background operation, executable in a first intermediate power state, based on the background flag information.
Inventor(s): Hyo Jin CHOI of Icheon-si (KR) for sk hynix inc., Kwan Su LEE of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: a first processor manages state information of a buffer area of a buffer memory used as a parity area in a parity operation mode and outputs a control signal according to the state information, and a second processor which performs a parity operation using the buffer area performs the parity operation according to the control signal of the first processor.
Inventor(s): Jae Yeop JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Dong Hun KWAK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: a memory device includes a memory cell array comprising a plurality of regions. each region is a segment or portion of a page. each region is connected to dummy word lines and word lines. a voltage generator provides a read voltage for reading a memory cell connected to a selected word line, and provides a pass voltage for turning on a dummy memory cell included in a region corresponding to the selected region. a read operation controller controls the voltage generator to apply the pass voltage to the dummy word lines and apply the read voltage to the selected word line.
Inventor(s): Dong Hun KWAK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: according to the present disclosure, a memory device includes a memory cell, a delay information storage configured to store delay information associated with a time at which data stored in the memory cell is output, and an operation controller configured to output the data to an external device after delaying a time corresponding to the delay information from a time of discharging a voltage provided to the memory cell.
Inventor(s): Hyung Jin CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Gwi Han KO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chan Hui JEONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Se Chun PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: a memory device includes: a plurality of memory cells; a peripheral circuit configured to perform a plurality of program loops each including a program voltage apply operation of applying a program voltage to selected memory cells, and a verify operation of verifying a program state of the selected memory cells; and a control logic configured to control the peripheral circuit to apply program voltages increasing in a step-wise manner by a first step voltage in program loops in a first state, and increasing by a second step voltage that is lower than the first step voltage in program loops in a second state that occur after the program loops in the first state. the first state and the second state of the program loops are determined based on when a verify operation on a program state having a highest threshold voltage is performed.
Inventor(s): Jin Woo Kim of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: a storage device may store performance information of the storage device in a target memory area including one or more of a plurality of memory blocks on determination that a set target condition is satisfied. and the storage device may control a target operation based on the stored performance information.
Inventor(s): In Jong JANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: the present disclosure relates to a memory controller which supports an interworking method for a test between an external device and a storage device, and a host. the memory controller proposed in the present disclosure may include a first interface configured to communicate with an external device, a second interface configured to communicate with a memory, a command queue configured to store commands received from the external device and a processor configured to perform a control operation according to a command stored in the command queue, and suspend the performance of the control operation according to the command for a waiting time corresponding to a value of a mutex counter for the command, when a mutex flag for the command is activated.
Inventor(s): Jae Hwan SEO of Icheon-si (KR) for sk hynix inc., Chul Moon JUNG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: a fuse latch of a semiconductor device including pmos transistors and nmos transistors includes a data transmission circuit configured to transmit data to a first node and a second node in response to a first control signal, a latch circuit configured to latch the data received from the data transmission circuit through the first node and the second node, and a data output circuit configured to output the data latched by the latch circuit in response to a second control signal. nmos transistors contained in the data transmission circuit, the latch circuit, and the data output circuit may be formed in first, fourth, and fifth active regions, pmos transistors are formed in second and third active regions, and the first to fifth active regions are sequentially arranged in a first direction.
Inventor(s): Tae Ha KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Ae KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F9/54, G06F1/3296
Abstract: an automotive system includes a memory device and a controller. the memory device is installed in an automobile. the controller controls the memory device and an electronic device in the automobile. the controller controls the memory device to process a background operation during a time limit when a background operation trigger event may be detected.
Inventor(s): Do Hun KIM of Icheon (KR) for sk hynix inc., Kwang Sun LEE of Icheon (KR) for sk hynix inc., Gi Jo JEONG of Icheon (KR) for sk hynix inc.
IPC Code(s): G06F12/0802, G06F3/06, G06F11/10
Abstract: the present technology relates to an electronic device. according to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. the main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.
Inventor(s): Hoe Seung JUNG of Icheon-si (KR) for sk hynix inc., Do Hyung KIM of Icheon-si (KR) for sk hynix inc., Chi Heon KIM of Icheon-si (KR) for sk hynix inc., Joo Young LEE of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F12/10
Abstract: a storage device may load, between a first time point at which information on candidate memory regions among a plurality of memory regions is started to be sent to an external device and a second time point at which a command requesting a map segment for a target memory region among the plurality of memory regions is received from the external device, all or a part of map segments corresponding to the candidate memory regions into a buffer.
Inventor(s): Byung Goo CHO of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/10
Abstract: a semiconductor device includes a chip selection signal receiver configured to receive, from an external memory controller, a chip selection signal activating to a state in which communication is possible with the external memory controller. the semiconductor device also includes a data signal receiver configured to receive a command and an address from the external memory controller. the semiconductor device further includes an operation controller configured to perform an internal operation according to the command and the address received through the data signal receiver while the chip selection signal is input. the semiconductor device additionally includes an internal signal generator configured to output an inactivated internal chip selection signal blocking transferal of the chip selection signal to the operation controller when a command other than a command requesting an output of data is received while the internal operation is performed.
20240177751.STORAGE DEVICE AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Seok Min LEE of Icheon-si, (KR) for sk hynix inc.
IPC Code(s): G11C7/10, G11C7/16
Abstract: a storage device includes: an embedding vector manager for determining an estimated access frequency of each of a plurality of embedding vectors, based on a learning data set, and dividing the plurality of embedding vectors into a plurality of embedding vector groups, based on an order of the estimated access frequencies; and a plurality of memory cell arrays for each storing embedding vectors included in any one embedding vector group among the plurality of embedding vector groups.
Inventor(s): Chang Kyun PARK of Gyeonggi-do (KR) for sk hynix inc., Young Sik KOH of Gyeonggi-do (KR) for sk hynix inc., Seung Jin PARK of Gyeonggi-do (KR) for sk hynix inc., Dong Hyun LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C8/18, G11C7/10, G11C7/22, G11C11/4076, G11C16/32
Abstract: a memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. the interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. the internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a zq calibration operation, or a driving force control operation.
20240177766.MEMORY DEVICE AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Hee Youl LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/4096, G11C11/4076, G11C11/4099
Abstract: a memory device, and a method of operating the same, includes checking a first elapsed time between an end time of a program operation performed on a first page and a selection time when a second page is selected after the end time, comparing the first elapsed time with a reference time interval, and performing a dummy program operation on the second page when the first elapsed time is equal to or longer than the reference time interval.
Inventor(s): Hyung Jin CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Gwi Han KO of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/34
Abstract: a memory device comprising: a memory cell array comprising multiple memory cells, and a controller configured to repeatedly perform a program loop comprising a voltage application interval and a verification interval until a program operation for cells that have been connected to a word line that have been selected as a program target reach a threshold voltage level and configured to adjust an increase in a level of a program voltage that is applied to the selected word line in the voltage application interval of a second program loop following a first program loop, based on a result of a comparison between a threshold voltage level of each of cells that have been selected as a verification target, among the cells that have been connected to the selected word line, and a pre-target level in the verification interval of the first program loop, among the program loops that are repeated.
Inventor(s): Jae Hyeon SHIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chang Han SON of Icheon-si Gyeonggi-do (KR) for sk hynix inc., In Gon YANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Sung Hyun HWANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/08, G11C16/34
Abstract: the present technology relates to an electronic device. a memory device including a plurality of memory cells connected to a plurality of word lines arranged between a plurality of source select lines and a plurality of drain select lines, a peripheral circuit configured to perform a program operation of programming data in selected memory cells among the plurality of memory cells, and a program operation controller configured to control the peripheral circuit to apply a voltage, for turning on or off source select transistors connected to the plurality of source select lines, to the plurality of source select lines, while applying a pass voltage to the plurality of word lines after applying a program voltage to selected word lines connected to the selected memory cells.
20240177776.MEMORY DEVICE AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Hyun Seob SHIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Dong Hun KWAK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/24
Abstract: the present technology relates to an electronic device. according to the present technology, a memory device may include a plurality of memory cells, a read and write circuit, and a program controller. the plurality of memory cells may be connected to a plurality of channels passing through a plurality of word lines. the program controller may control the read and write circuit to perform a sensing operation on first memory cells and second memory cells among the plurality of memory cells during differently set sensing time periods. the first memory cells may be connected to first channels adjacent to a plurality of slits, among a plurality of channels separated by the plurality of slits. the second memory cells may be connected to second channels farther from the plurality of slits than the first channels.
Inventor(s): Hyung Jin CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chan Sik PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/26, G11C16/24
Abstract: a memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers respectively connected to the plurality of memory cells; a sensing circuit connected to the plurality of page buffers respectively, the sensing circuit: performing a sensing operation on the page buffers in units of a plurality of chunks, each chunk including two or more page buffers, among the plurality of page buffers, and outputting a sensing result of each of the plurality of chunks; a verification result output circuit for outputting a final verification result of a target program state, among a plurality of program states to which the memory cells are to be programmed, based on the sensing results of the plurality of chunks; and a control logic for controlling the sensing circuit and the peripheral circuit, based on the final verification result.
Inventor(s): Hee Youl LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/26, G11C16/04, G11C16/08, G11C16/24
Abstract: there are provided a memory device and an operating method of the memory device. the memory device includes: a plurality of pages each comprising a plurality of memory cells; a peripheral circuit for, in a read operation of a selected page among the pages, applying a read voltage to a selected word line connected to the selected page, sequentially applying sub-pass voltages and target pass voltages higher than the sub-pass voltages to adjacent word lines adjacent to the selected word line, and applying the target pass voltages to the other unselected word lines; and a control circuit for controlling the peripheral circuit. before the read voltage is applied to the selected word line, the control circuit controls the peripheral circuit to apply the sub-pass voltages to the adjacent word lines, and apply the target pass voltages to the other unselected word lines.
Inventor(s): Hyung Jin CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/16
Abstract: in a semiconductor memory device, a program voltage is applied to select lines, which are coupled to corresponding select transistors included in a plurality of string groups. a verify operation on the select transistors is then performed, which simultaneously checks the operation of first select transistors included in a first string group and second select transistors included in a second string group.
Inventor(s): Hyung Jin CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Se Chun PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/08, G11C16/10
Abstract: a method of operating a semiconductor device includes: starting a program operation on selected memory cells among a plurality of memory cells in response to a program command; suspending the program operation in response to a program suspend command; and performing a pre-verify operation by using a modified verify voltage in response to a program resume command.
20240177785.MEMORY DEVICE AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Chan Hui JEONG of Gyeonggi-do (KR) for sk hynix inc., Dong Hun KWAK of Gyeonggi-do (KR) for sk hynix inc., Se Chun PARK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10, G11C16/14, G11C16/32
Abstract: the present technology relates to an electronic device. according to the present technology, a memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. the peripheral circuit may perform a fail bit detection operation on memory cells selected from among the plurality of memory cells. the control logic may control the peripheral circuit to set target parameters related to a main operation based on a comparison result between a fail bit detection time measured in the fail bit detection operation and a reference time, and perform the main operation on the selected memory cells based on the target parameters.
Inventor(s): Kang Woo PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/10, G11C16/26
Abstract: a memory device including a page buffer is part of a memory system. the memory device includes first memory cells, each configured to be programmed to have a threshold voltage corresponding to any one of a plurality of program states. the memory device also includes data latches configured to respectively store a plurality of pieces of first logical page data to be stored in the first memory cells. the memory device further includes a pre-sensing latch configured to store data sensed through a pre-verify operation. the pre-sensing latch stores second logical page data to be stored in second memory cells when a main verify operation for a threshold program state, among the plurality of program states, has passed.
Inventor(s): Jun Hyuk LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/44, G11C29/12, G11C29/18
Abstract: provided herein is a semiconductor device and a method of testing the semiconductor device. the method of operating a semiconductor device includes initializing a latch included in a page buffer, applying a read pass voltage to a plurality of word lines, allowing at least one of the plurality of word lines to float, and performing a sensing operation on the page buffer.
20240177793.MEMORY DEVICE INCLUDING ERROR CORRECTION DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Jin Ho JEONG of Gyeonggi-do (KR) for sk hynix inc., Dae Suk KIM of Gyeonggi-do (KR) for sk hynix inc., Sang Woo YOON of Gyeonggi-do (KR) for sk hynix inc., A Ram RIM of Gyeonggi-do (KR) for sk hynix inc., Mun Seon JANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/52, G11C29/00, G11C29/44
Abstract: a memory device includes a memory cell area including a plurality of cell blocks divided into a plurality of normal cell blocks, at least one ecc cell block, and at least one redundancy cell block, the plurality of cell blocks being configured to output data and error correction codes; an error correction circuit configured to generate error-corrected data by correcting errors in the data using the error correction codes; a first switch group configured to output the error-corrected data while performing, according to first repair control information, a shifting operation on the error-corrected data; and a second switch group configured to transfer the data from the memory cell area to the error correction circuit while performing, according to second repair control information, a zero-padding operation on the data output from one of the cell blocks.
Inventor(s): Jong Seok JUNG of Gyeonggi-do (KR) for sk hynix inc., Chan Keun KWON of Gyeonggi-do (KR) for sk hynix inc., Jong Seok KIM of Gyeonggi-do (KR) for sk hynix inc., Young Kwan LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L21/66
Abstract: a test circuit of a semiconductor apparatus includes a first resistor, a second resistor and a feed-back loop circuit. the first resistor is coupled between a pad and a test element. the second resistor is coupled to the first resistor in a parallel manner. the feed-back loop circuit is configured to feed a result back to the second resistor, the result being one of comparing a first voltage and a second voltage with each other, the first voltage and the second voltage being applied respectively to the first resistor and the second resistor.
20240178169.SEMICONDUCTOR DEVICE INCLUDING BONDING PAD_simplified_abstract_(sk hynix inc.)
Inventor(s): Byung Ho LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/00
Abstract: a semiconductor device includes: a lower semiconductor structure including a plurality of first lower electrode bonding pads, a plurality of second lower electrode bonding pads, and a lower connection pattern connecting the plurality of first lower electrode bonding pads to each other while being connected to a first voltage; and an upper semiconductor structure disposed over the lower semiconductor structure and including a plurality of first upper electrode bonding pads, a plurality of second upper electrode bonding pads, and an upper connection pattern connecting the plurality of second upper electrode bonding pads to each other while being connected to a second voltage different from the first voltage, wherein the plurality of first lower electrode bonding pads are bonded to the plurality of first upper electrode bonding pads, respectively, and the plurality of second lower electrode bonding pads are bonded to the plurality of second upper electrode bonding pads, respectively.
20240178172.SEMICONDUCTOR DEVICE INCLUDING RESISTOR ELEMENT_simplified_abstract_(sk hynix inc.)
Inventor(s): Chan Ho YOON of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H01L23/00, H01L23/522, H01L25/065, H01L25/18
Abstract: a semiconductor device includes a first pad defined on one surface of a first chip; a second pad defined on one surface of a second chip which is stacked on the first chip, and bonded to the first pad; a first resistor element defined in the first chip, and coupled to the first pad; and a second resistor element defined in the second chip, and coupled to the second pad.
Inventor(s): Wan Sup SHIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Yoon Ho KANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Ji Seong KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L29/10, H01L21/02, H01L21/8234, H01L29/49, H01L29/68
Abstract: a semiconductor device includes a gate structure including insulating layers and conductive layers that are alternately stacked, a channel layer located in the gate structure, a silicide layer located in the channel layer, and a memory layer surrounding the channel layer. at least one of the channel layer, the silicide layer, and the memory layer includes a halogen element.
20240179263.IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD_simplified_abstract_(sk hynix inc.)
Inventor(s): Jun Hyeok CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N1/60, G06V10/56, G06V10/75, H04N25/11
Abstract: an image processing device may include: a target pixel set determiner for determining a target pixel set, among a plurality of phase detection auto focus (pdaf) pixel sets, based on average values and variance values of pixel values output from a plurality of pixels corresponding to a kernel set based on each of the plurality of pdaf pixel sets, wherein the average values and the variance values respectively correspond to colors of color filters included in the plurality of pixels; and a pixel value corrector for converting pixel values of the target pixel set into first pixel values corresponding to a predetermined color and correcting the first pixel values to second pixel values corresponding to an arrangement pattern of the plurality of pixels based on pixel values of a plurality of adjacent pixels adjacent to the target pixel set.
Inventor(s): Jeong Eun SONG of Gyeonggi-do (KR) for sk hynix inc., Min Seok SHIN of Gyeonggi-do (KR) for sk hynix inc., Yu Jin PARK of Gyeonggi-do (KR) for sk hynix inc., Sung Uk SEO of Gyeonggi-do (KR) for sk hynix inc., Sun Young LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N25/71, H04N25/677
Abstract: disclosed is an image sensing device including a first clock distributor suitable for receiving a first input clock signal through a first input terminal, and outputting a plurality of first output clock signals through a plurality of first output terminals, and a first conductive line coupled in common to the plurality of first output terminals.
Inventor(s): Go Hyun LEE of Icheon-si (KR) for sk hynix inc., Jae Taek KIM of Icheon-si (KR) for sk hynix inc., Hye Yeong JUNG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10B43/40, H01L23/00, H01L23/522, H01L23/535, H10B43/27
Abstract: the semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.
Inventor(s): Gwang Sun JUNG of Icheon (KR) for sk hynix inc., Jun Ku AHN of Icheon (KR) for sk hynix inc., Sung Lae CHO of Icheon (KR) for sk hynix inc., Uk HWANG of Icheon (KR) for sk hynix inc.
IPC Code(s): H10B63/00, C04B35/547, H10B63/10
Abstract: disclosed is a chalcogenide material including germanium (ge), selenium (se), arsenic (as), silicon (si) and indium (in). in the chalcogenide material, a content of selenium (se) is 49 at % to 56 at %, a content of indium (in) is 1.1 at % or less, and a sum of contents of germanium (ge) and silicon (si) is 18 at % to 21 at %.
Inventor(s): Won Tae KOO of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10K10/50, G11C13/00, H10B63/00, H10K10/82
Abstract: a semiconductor device includes a first electrode and a second electrode that are spaced apart from each other, and a resistance change layer disposed between the first and second electrodes and including a metal-organic framework having cavities. the resistance change layer includes channels disposed in the cavities, receiving metal ions provided from one electrode of the first and second electrodes.
- SK hynix Inc.
- G03F1/24
- G03F1/48
- G03F1/54
- Sk hynix inc.
- G05B19/418
- G05F1/46
- G05F1/575
- G06F1/3225
- G06F1/3296
- G06F3/06
- G06F9/54
- G06F12/0802
- G06F11/10
- G06F12/10
- G11C7/10
- G11C7/16
- G11C8/18
- G11C7/22
- G11C11/4076
- G11C16/32
- G11C11/4096
- G11C11/4099
- G11C16/10
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