SK hynix Inc. patent applications on May 16th, 2024
Patent Applications by SK hynix Inc. on May 16th, 2024
SK hynix Inc.: 42 patent applications
SK hynix Inc. has applied for patents in the areas of G06F3/06 (6), G11C16/08 (6), G11C16/10 (6), H01L23/528 (5), H10B43/27 (5)
With keywords such as: memory, device, data, configured, voltage, circuit, layer, program, line, and semiconductor in patent application abstracts.
Patent Applications by SK hynix Inc.
20240159802.SEMICONDUCTOR DEVICE HAVING SHIELDING STRUCTURE_simplified_abstract_(sk hynix inc.)
Inventor(s): Suk Hwan CHOI of Icheon-si (KR) for sk hynix inc., Sun Beom LEE of Icheon-si (KR) for sk hynix inc., Jong Seok JUNG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G01R19/00, H03K3/01
Abstract: a semiconductor device includes a sensing voltage line disposed between a first circuit area and a second circuit area, and configured to transfer a sensing voltage detected in the second circuit area to the first circuit area; and a first internal voltage line disposed between the first circuit area and the second circuit area, configured to transfer an internal voltage, generated by a voltage driver of the first circuit area using the sensing voltage provided through the sensing voltage line, to the second circuit area and configured to shield the sensing voltage line.
Inventor(s): Xiaofang CHEN of Milpitas CA (US) for sk hynix inc., Wenwei WANG of Morgan Hill CA (US) for sk hynix inc.
IPC Code(s): G01R21/06, G06F3/06
Abstract: devices, systems, and methods for measuring a power consumption of a hot pluggable solid-state drives are described. an example method for measuring a power consumption of a solid-state drive communicatively coupled to a server backplane within a server chassis includes performing, by an adaptor, a power measurement to generate a value corresponding to the power consumption of the solid-state drive, and transmitting, using a wireless transceiver of the adaptor, the value to a recording unit, where a first end of the adaptor is coupled to the solid-state drive and a second end of the adaptor is coupled to the server backplane, and where the wireless transceiver, communicatively coupled to an antenna, is configured to operate using at least one wireless protocol.
Inventor(s): Nam Cheol JEON of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hea Jong YANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Tae Un YOUN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G01R31/26, G11C29/12
Abstract: a reliability measuring apparatus includes an oxide-nitride-oxide-alumina (onoa) current measuring circuit configured to measure an onoa current by applying an onoa current measuring voltage to a selected word line coupled to a selected memory cell in a flash memory and a reliability indicator generator configured to a reliability indicator using the onoa current measured through the measuring circuit.
20240159823.SEMICONDUCTOR DEVICE HAVING DEFECT DETECTION CIRCUIT_simplified_abstract_(sk hynix inc.)
Inventor(s): Young Ock HONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G01R31/28, H01L23/00, H01L23/522, H01L23/528, H01L25/065, H10B80/00
Abstract: there is provided a semiconductor device having a defect detection circuit. the semiconductor device includes a plurality of upper bonding pads, a plurality of lower bonding pads adhered to the plurality of upper bonding pads, a first upper line electrically connecting upper bonding pads, among the plurality of upper bonding pads, to each other; a plurality of lower lines electrically connected to the plurality of lower bonding pads; and a first defect detection circuit including an input terminal connected to a lower line, among the plurality of lower lines and an output terminal connected to another lower line, among the plurality of lower lines.
Inventor(s): Jin Suk OH of Gyeonggi-do (KR) for sk hynix inc., Young Jae AN of Gyeonggi-do (KR) for sk hynix inc., Bok Rim KO of Gyeonggi-do (KR) for sk hynix inc., Jae Heung KIM of Gyeonggi-do (KR) for sk hynix inc., Min Wook OH of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G01R31/317, G01R31/3183
Abstract: a test mode control circuit includes an encryption circuit and a test mode generating circuit. the encryption circuit encrypts, based on an encryption code, an access code set to generate an encrypted access code set. the test mode generating circuit generates a test mode signal based on the encrypted access code set.
20240159947.IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Dong Ha KIM of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G02B5/20, G02B5/22, H04N23/75
Abstract: an image sensing device includes first color filters having a first color, second color filters having a second color, third color filters having a third color, fourth color filters having a fourth color, and a grid structure disposed between adjacent color filters of the first to fourth color filters and configured to prevent crosstalk between the adjacent color filters. the grid structure includes a first grid region disposed on sides of some of the fourth color filters and a second grid region different from the first grid region, and the grid structure has different structures in the first grid region and the second grid region.
20240160235.SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Se Won LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G05F1/46, G11C5/14, H03K19/00
Abstract: a semiconductor device includes a voltage supply circuit including a first pad to which a first source voltage that is generated from an external power source is applied and a second pad to which a second source voltage that is generated from the external power source is applied and configured to generate an internal voltage based on at least one of the first source voltage and the second source voltage and an internal voltage supply circuit configured to generate the internal voltage by supplying less than all of the second source voltage to the first source voltage when a level of the second source voltage is a set voltage level or higher, when generating the internal voltage based on the first source voltage.
Inventor(s): Eun Jae OCK of lcheon (KR) for sk hynix inc.
IPC Code(s): G06F1/20, G06F11/30
Abstract: a method for operating an electronic device includes predicting a temperature rise of the electronic device when the application is started, predicting a temperature of the electronic device based on the predicted temperature rise and a current temperature of the electronic device, and lowering the temperature of the electronic device when the predicted temperature of the electronic device is higher than a preset threshold temperature.
Inventor(s): In Jong JANG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: a storage device may comprise a memory including a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a controller. the controller may assess an external environmental state when a read operation on the memory fails and control a read retry operation using at least one of at least two read retry tables that are set for each of at least two attributes of a first sampling factor and each of at least two attributes of a second sampling factor according to the external environmental stat.
20240160358.MEMORY DEVICE AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Gil Bok CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Dae Hwan YUN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: a memory device performs a detrap operation on a selected memory block when the number of program/erase cycles of the selected memory block equals or exceeds a predetermined set number. a circuit included in the memory device applies a heating current to a heating layer, thermally coupled to the channel of each of the plurality of strings included in the selected memory block in the detrap operation.
20240160371.STORAGE DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Lee Hyun KWON of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: a storage device includes a memory device including a plurality of memory blocks, and a controller configured to move first data from a single level cell (slc) memory block to a first memory block having a target density lower than a maximum density based on a waiting time and to move second data from the slc memory block to a memory block having the maximum density based on the waiting time.
Inventor(s): Ki Tae KIM of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: a storage device according to the present technology may include a memory device for storing data, a buffer memory configured to temporarily store data to be stored in the memory device, and a memory controller configured to determine a delay time based on a plurality of parameters upon receipt of a write request from a host, and transmit a data request to the host after the delay time has elapsed.
Inventor(s): Youn Won PARK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06, G06F12/02
Abstract: a controller includes a clock frequency determiner configured to determine a type of a read operation corresponding to a read request based on the read request received from a host, and to determine a clock frequency according to the type, a clock generator configured to generate a clock according to the determined clock frequency, and a command generator configured to generate a read command corresponding to the read request using the clock.
20240160523.SEMICONDUCTOR SYSTEM_simplified_abstract_(sk hynix inc.)
Inventor(s): Won Ha CHOI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F11/10, G06F12/02
Abstract: a semiconductor system includes a controller configured to output a command and multiple addresses for performing a read modify write operation when the multiple addresses for performing a read operation have a logic level combination for selecting contiguous regions and configured to output first data for performing a write operation, and a semiconductor device configured to store the first data for performing the write operation as write data based on the command, configured to output internal data from a core circuit as the read operation is consecutively performed based on the command and the addresses, configured to generate parities by performing an error correction code (ecc) operation based on the internal data and the write data, and configured to store the write data and the parities in the core circuit.
Inventor(s): Jin Ho BAEK of Icheon-si (KR) for sk hynix inc., Young Pyo JOO of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F11/10, G06F11/07
Abstract: a computing system comprises a memory and a controller, and the controller is configured to store a first type of data and a second type of data in the memory, to divide the first type of data into a first part and a second part, to generate parity information on the first part and to store the parity information in the memory, and a refresh interval of a region of the memory where the first type of data is stored is larger than a refresh interval of a region of the memory where the second type of data is stored.
Inventor(s): Wan KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F12/02
Abstract: a method of operating a controller includes sensing power-on of a memory system including a semiconductor memory device, determining whether to delay a garbage collection operation performed during an initial operation of the memory system, based on a sudden-power off (spo) count value, and controlling the semiconductor memory device to perform the garbage collection operation based on the determination result.
Inventor(s): Yun Jeong MUN of Gyeonggi-do (KR) for sk hynix inc., Rak Kie KIM of Gyeonggi-do (KR) for sk hynix inc., Ho Kyoon LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F12/0891
Abstract: a computer system may include a processor; a first memory device; a second memory device; a cache memory including a plurality of cache entries and a cache controller. the cache controller is configured to manage a source indicating whether a caching data is provided from the first memory device or the second memory device, and determine a cache entry to be evicted from the cache entries based on a cache miss ratio of request data by the source which the request data is read when the request data of the processor do not exist in the cache memory and a cache occupancy ratio by the source.
Inventor(s): Hong Ki MOON of Gyeonggi-do (KR) for sk hynix inc., Seok Bo SHIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F13/42
Abstract: the present technology may include a first latch circuit configured to store, as first data, data that is transmitted through a first signal line, a second latch circuit configured to store, as a plurality of second data, the data that is transmitted through the first signal line by sorting the data by a plurality of second signal lines that are connected to the first signal line in common, and a data bus inversion engine configured to selectively perform a first mode in which the data bus inversion engine generates a data bus inversion flag by comparing the first data with current input data and a second mode in which the data bus inversion engine generates the data bus inversion flag by comparing the plurality of second data with the current input data.
Inventor(s): Sein PARK of Daegu (KR) for sk hynix inc., Eunhyeok PARK of Pohang (KR) for sk hynix inc.
IPC Code(s): G06N3/08
Abstract: a learning method of a neural network system includes preparing a second neural network having the same weights as a first neural network which is pre-trained; adding noise to weights of the first neural network; generating a first output data of the first neural network and generating a second output data of the second neural network by providing input data to the first neural network and the second neural network; and calculating a loss function using the first output data, the second output data, and a true value corresponding to the input data.
Inventor(s): Heon Ki KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Kyeong Min CHAE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/10, G11C7/22
Abstract: a pipe register includes: a plurality of register units configured to output data in response to control signals; and a pipe control circuit configured to generate a reference timing signal by dividing a clock signal, the clock signal activated during an activation time of a read enable signal, and generate the control signals based on the read enable signal and the reference timing signal.
Inventor(s): Sang Hyun KU of Gyeonggi-do (KR) for sk hynix inc., Do Hong Kim of Gyeonggi-do (KR) for sk hynix inc., Min Ho Seok of Gyeonggi-do (KR) for sk hynix inc., Duck Hwa Hong of Gyeonggi-do (KR) for sk hynix inc., So Yoon Kim of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/406, G11C11/408
Abstract: a memory includes: a plurality of word lines; and a row circuit configured to: activate at least one word line among the word lines to an active voltage level during an active operation and discharge the activated word line during a precharge operation; and discharge the word line from the active voltage level to a precharge voltage level in different manners during the precharge operation in response to a precharge command and during the precharge operation during a refresh operation.
Inventor(s): Hyung Jin CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Gwi Han KO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chan Sik PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C11/56, G11C16/08, G11C16/24, G11C16/34
Abstract: provided herein is a memory device for performing a program operation, a method of operating the memory device, and a storage device having the memory device. the method of operating a memory device includes receiving a first data bit among a plurality of data bits to be stored in each of a plurality of memory cells from a memory controller, performing a program voltage apply operation on the plurality of memory cells based on the first data bit, and receiving a second data bit among the plurality of data bits from the memory controller while performing the program voltage apply operation.
Inventor(s): Jae Yeop JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Dong Hun KWAK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Yeong Jo MUN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hyun Seob SHIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G06F13/16, G11C16/04, G11C16/08, G11C16/34
Abstract: provided herein is a memory device for performing a foggy-fine program operation and a method of operating the memory device. the memory device includes a memory block including a plurality of memory cells, a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of cells, and a control logic configured to control the program operation by the peripheral circuit. the control logic is configured to control the peripheral circuit to perform a foggy program operation on first memory cells coupled to a first word line, among the plurality of memory cells, perform a foggy program operation on second memory cells coupled to a second word line adjacent to the first word line, among the memory cells, and perform a fine program operation on the first memory cells by decreasing a verify pass voltage to be applied to the second word line.
Inventor(s): Hyung Jin CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chan Hui JEONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/08, G11C16/28
Abstract: provided herein is a semiconductor device and a method of operating the same. the semiconductor device includes first to n-th memory cell string groups, each including a plurality of memory cell strings, a peripheral circuit configured to sequentially perform program operations, each including a plurality of program loops, on the first to n-th memory cell string groups, and a program operation controller configured to control the peripheral circuit to apply a precharge voltage to a common source line and apply a turn-on voltage to one or more of a plurality of source select lines coupled to the first to n-th memory cell string groups in any one of the plurality of program loops, wherein a number of one or more source select lines to which the turn-on voltage is to be applied is determined based on a program loop count corresponding to of the one program loop.
Inventor(s): Hye Eun HEO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hyun Seung YOO of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/30, G11C16/04
Abstract: the present technology includes a memory device and a method of operating the same. the memory device includes a string including a first select transistor, memory cells, and a second select transistor connected between a source line and a bit line, and a voltage generator configured to supply a precharge voltage to the source line and selectively apply a turn on voltage or a negative voltage to a first select line connected to a gate of the first select transistor. the voltage generator is configured to apply the precharge voltage to the source line, apply the turn on voltage to the first select line during a first time in which a channel layer of the string is precharged, and apply the negative voltage to the first select line during a second time in which the channel layer of the string is precharged, while precharging the channel layer of the string.
Inventor(s): Hyung Jin CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Gwi Han KO of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/10, G11C16/12
Abstract: a memory device, and a method of operating the same, includes a plurality of memory cells configured to be programmed to any one of a plurality of program states, a peripheral circuit configured to perform a plurality of program loops on the plurality of memory cells, and a program operation controller. the program operation controller is configured to control the peripheral circuit such that a verify operation for a second program state is performed from a second program loop after a verify operation for a first program state performed from a first program loop passes, wherein the first program loop is performed before the second program loop.
20240161841.MEMORY DEVICE AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Seung Geun JEONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/12, G11C16/24
Abstract: the present technology includes a memory device and a method of operating the same. the memory device includes a memory block, page buffers connected to memory cells through bit lines and configured to apply a program allowable voltage or a program inhibit voltage to the bit lines, a current measurer configured to output a total current value of the bit lines according to a sensing voltage measured from the bit lines, and a logic circuit configured to control the voltage generator and the page buffers to calculate the number of inhibit cells according to the total current value and omit a verify operation of a program loop or perform the verify operation of the program loop according to the number of the inhibit cells.
Inventor(s): Sang Ah HYUN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Yong Ho SEO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Woo Sik JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jun Phyo LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Bong Hwa JEONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/38, G11C29/12, G11C29/18
Abstract: a test system includes a test device configured to output a command address and a test dock for performing a test mode and to receive a comparison signal, and a memory device configured to enter the test mode, based on the command address, to set an initial value by the command address, to perform a calculation operation on the initial value according to a logic level combination of the command address to generate a row address and a command address during a pre-charge operation, and to compress and compare internal data output based on the row address and the column address to output the internal data as the comparison signal to the test device.
Inventor(s): Hong Ki MOON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/42, G11C29/18, G11C29/46
Abstract: a semiconductor memory device includes a command address control circuit configured to generate an error correction command and selection address for executing an error correction operation by receiving an external control signal, an error flag generation circuit configured to correct an error of data corresponding to the selection address and configured to generate a target error flag based on a pattern of the error of the data, and an error information processing circuit configured to generate a target address that is used as the selection address based on the target error flag in a target error correction operation that is executed based on the error correction operation.
Inventor(s): Jung Taek YOU of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/00, G11C29/44
Abstract: a memory device includes: a memory cell region including normal cells coupled to normal column selection lines, and row-hammer cells and redundancy cells respectively coupled to redundancy column selection lines; a repair control circuit configured to provide repair addresses and row-hammer flag signals, corresponding to repair information, according to a row address; and a column control circuit configured to activate at least one of the redundancy column selection lines according to the row-hammer flag signals or a comparison result of a column address and the repair addresses.
Inventor(s): Nam Jae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/528, H01L23/00, H01L29/417, H10B43/27
Abstract: provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. the semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.
Inventor(s): Ji Seong KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Yoon Ho KANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Wan Sup SHIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Seok Min JEON of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/528, H01L23/522, H10B41/27, H10B43/27
Abstract: a semiconductor device including: a gate structure in which conductive layers and insulating layers are alternately stacked; contact plug extending in a stacking direction of the insulating layers through the gate structure; first spacer layers each located between the conductive layer and the contact plug; and second spacer layers each located between the contact plug and the first spacer layer.
20240162170.SEMICONDUCTOR DEVICE INCLUDING GUARD RING_simplified_abstract_(sk hynix inc.)
Inventor(s): Bin WOO of Icheon (KR) for sk hynix inc., Seung In SHIN of Icheon (KR) for sk hynix inc.
IPC Code(s): H01L23/58
Abstract: a semiconductor device includes: a semiconductor substrate; and a guard ring including a plurality of conductive patterns stacked over the semiconductor substrate in a first direction to be spaced apart from each other, and a conductive plug disposed between two adjacent conductive patterns among the plurality of conductive patterns, the first direction being perpendicular to a top surface of the semiconductor substrate, wherein the conductive plug includes a plurality of long patterns and a plurality of short patterns.
Inventor(s): Kang Hun KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Si Yun KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jun Yong SONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/00
Abstract: a semiconductor package includes a bump interconnection structure. the semiconductor package includes a first lead and a second lead spaced apart from each other on a first substrate, a bump disposed to face the first lead in a second substrate, and a solder layer configured to connect the bump and the first lead. the first lead has a stair shape that ascends toward the second lead.
Inventor(s): Jun Sik KIM of Gyeonggi-do (KR) for sk hynix inc., Sung Hwan HWANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L29/40, H01L21/28, H01L29/423, H01L29/51
Abstract: a semiconductor device includes a gate trench formed in a substrate, a gate dielectric layer formed along profile of sidewalls and a bottom surface of the gate trench, first and second gate electrodes that are stacked over the gate dielectric layer to gap-fill a portion of the gate trench, a dipole inducing portion positioned between the second gate electrode and the gate dielectric layer and including a dipole bond and a non-dipole bond, and a capping layer suitable for gap-filling a remaining portion of the gate trench over the dipole inducing portion and the second gate electrode.
Inventor(s): Nam Jae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L29/45, H01L29/78
Abstract: the present technology provides a semiconductor device. the semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.
Inventor(s): Young Gwang YOON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L29/78, H01L29/423, H01L29/51, H01L29/66
Abstract: a semiconductor device includes a gate structure crossing an active region of a substrate, and spacers formed on both side surfaces of the gate structure. the gate structure includes an interfacial insulating layer formed on the substrate, a gate dielectric layer formed on the interfacial insulating layer, a gate barrier layer and gate side insulating layers formed on the gate dielectric layer, and a gate electrode on the gate barrier layer. the gate dielectric layer is in contact with inner side surfaces of the spacers, and has a u-shaped longitudinal cross-sectional shape to surround a lower surface and some portions of side surfaces of the gate barrier layer. the gate side insulating layers surround outer side surfaces of the gate barrier layer.
Inventor(s): Seok Man HONG of Icheon (KR) for sk hynix inc.
IPC Code(s): H01L29/86, H01L21/443, H01L27/02, H01L29/66
Abstract: a semiconductor device may include a first electrode including carbon, an anti-oxidation layer located on the first electrode, a barrier layer located on the anti-oxidation layer and including oxide, a variable resistance layer located on the barrier layer, and a second electrode located on the variable resistance layer. one or both of the anti-oxidation layer and the barrier layer may each have a thickness of 0.1 nm to 2 nm.
20240162913.SAMPLE AND HOLD CIRCUIT_simplified_abstract_(sk hynix inc.)
Inventor(s): Se Won LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H03M1/12, H03M1/18
Abstract: a sample and hold circuit includes a sampling circuit including a first amplifier configured to amplify an input voltage to generate an amplification voltage, the sampling circuit configured to perform a sampling operation of sampling the amplification voltage. the sample and hold circuit also includes a holding circuit configured to perform a holding operation of setting an output voltage to a voltage level of the input voltage, based on the sampling operation and an amplification operation of a second amplifier.
Inventor(s): WEN JYH LIN of Zhubei City Hsinchu County (TW) for sk hynix inc.
IPC Code(s): H04L1/00, H04L25/49
Abstract: electronic device and operation method for an electronic device are provided. in the electronic device, a plurality of protocol data unit (pdu) blocks is generated to be transmitted on one or more lanes of a link. an advanced line encoding (ale) frame is further generated based on an ale scheme. the ale scheme has an effective data rate larger than an effective data rate of 8b/10b coding scheme, and the ale frame includes the plurality of pdu blocks, an error detection portion corresponding to the plurality of pdu blocks, and an error correction portion corresponding to the plurality of pdu blocks and the error detection portion. the ale frame is transmitted on the one or more lanes of the link to another electronic device.
Inventor(s): In Jong JANG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H04L9/08, H04L9/14
Abstract: a storage device included in a computing device which provides merkle tree-based credibility certification may generate a random hash value by hashing an erase count and a seed of each of a plurality of super blocks, may generate a merkle tree in which the random hash value is a leaf node, for each of the plurality of super blocks, may generate a plurality of private keys corresponding to the plurality of super blocks, respectively, on the basis of root nodes of merkle trees of the plurality of respective super blocks, and may transmit private key information including the plurality of private keys to a host device. the host device may use the private key information in credibility certification of the storage device.
20240163562.AMBIENT LIGHT SENSING USING IMAGE SENSOR_simplified_abstract_(sk hynix inc.)
Inventor(s): Ji Hee HAN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N5/235, G09G5/10
Abstract: an ambient light intensity is measured without a dedicated light intensity sensor and is determined instead using only an image sensor, image data from the image sensor, the luminance values obtained from the image data image sensor setup conditions, and determining when a setup condition sensor is changed or needs to be changed because of ambient brightness in the vicinity of the image sensor.
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