SK hynix Inc. patent applications on March 6th, 2025
Patent Applications by SK hynix Inc. on March 6th, 2025
SK hynix Inc.: 34 patent applications
SK hynix Inc. has applied for patents in the areas of H10B12/00 (4), G06F3/06 (3), H01L27/146 (3), H10B63/00 (2), H01L23/00 (2) G03F1/62 (2), H10F39/807 (2), H10B12/482 (2), H10B12/315 (2), H01L24/05 (1)
With keywords such as: memory, data, layer, device, structure, configured, semiconductor, pixel, including, and image in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Tae Joong HA of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G03F1/62
CPC Code(s): G03F1/62
Abstract: a pellicle assembly may include a pellicle membrane and a pellicle border. the pellicle membrane may include at least one recess and at least one opening. the at least one recess may extend from an upper surface or a lower surface of the pellicle membrane. the at least one opening may penetrate from the upper surface to the lower surface of the pellicle membrane. the pellicle border may support the pellicle membrane.
20250076751. PELLICLE STRUCTURE_simplified_abstract_(sk hynix inc.)
Inventor(s): Tae Joong HA of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G03F1/62
CPC Code(s): G03F1/62
Abstract: a pellicle structure may include a membrane border and a pellicle membrane. the membrane border defines an open region. the membrane is in contact with the membrane border and extending over the open region. thus, the membrane is capable of maintaining a thin film having a uniform thickness to prevent pattern errors.
Inventor(s): Jae Il LIM of Gyeonggi-do (KR) for sk hynix inc., Jae Won CHUNG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: a memory controller includes a command/address generation module; and a row-hammer tracking module configured to track a row-hammer address based on an active command and an address for a target bank and a target row indicated by the active command, the active command and the address being received from the command/address generation module, wherein the row-hammer tracking module includes: a plurality of storage devices each including fields corresponding to banks, each of the fields storing candidate addresses and access counting values for the candidate addresses; and at least one search controller configured to sequentially search, according to a clock, fields of the plurality of storage devices corresponding to the target bank when the active command is input, and search, during one clock, fields of the plurality of storage devices corresponding to different banks based on active commands indicating the different banks.
Inventor(s): In Hyuk PARK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/062
Abstract: a data storage device includes: a memory device including a plurality of first storage areas and a plurality of second storage areas, each of which stores a primary index corresponding to a primary key provided from a host and a primary value corresponding to the primary index, and a memory controller for controlling the memory device. the memory controller is configured to generate, according to a request from the host, the primary index including the primary key and address information of a target second storage area in which a primary value corresponding to the primary key is stored, among the plurality of second storage areas, generate, according to an additional request from the host, a secondary key corresponding to a secondary value including a portion of the primary value, and generate a secondary index including the secondary key and the address information of the target second storage area.
20250077105. MEMORY CONTROLLER AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Hyun Sub KIM of Seongnam (KR) for sk hynix inc., le Ryung PARK of Suwon (KR) for sk hynix inc., Dong Sop LEE of Yongin (KR) for sk hynix inc., Sung Yeob CHO of Yongin (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0647
Abstract: a memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. a memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.
20250077183. NORMALIZER FOR OPERATING ON FLOATING-POINT DATA_simplified_abstract_(sk hynix inc.)
Inventor(s): Seong Ju LEE of San Jose CA (US) for sk hynix inc.
IPC Code(s): G06F7/556, G06F5/01, G06F7/499
CPC Code(s): G06F7/556
Abstract: a normalizer for performing normalization on floating-point data includes a search circuit configured to receive selected mantissa data and to output reference exponent data and shift data, the selected mantissa data being either mantissa data of the floating-point data or 2's complement data of the mantissa data, an exponent adder configured to output normalized exponent data by adding exponent data of the floating-point data and the reference exponent data, and a unidirectional mantissa shifter configured to output normalized mantissa data by performing a unidirectional shift on the selected mantissa data based on a value of the shift data.
Inventor(s): Woong Ju JANG of Gyeonggi-do (KR) for sk hynix inc., Hoiju CHUNG of San Jose CA (US) for sk hynix inc., Yong Jun LEE of San Jose CA (US) for sk hynix inc., Dong Hee HAN of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/106
Abstract: a memory controller includes a scrub control circuit configured to generate a scrub command for instructing a scrub operation; and an address generation circuit configured to generate a scrub address having an address sequence in which a first column bit group of a column address, a row address, and a second column bit group of the column address are sequentially allocated from a least significant bit (lsb) to a most significant bit (msb), and change a value of the scrub address according to the scrub command.
Inventor(s): Ga Eul GO of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: a memory device includes an open memory block and control circuitry. the open memory block includes at least one first page having an erased state. the control circuitry is configured to perform a read operation for a page included in the open memory block, and apply a weight determined based on a ratio of the at least one first page in the open memory block to calculate a read count subject to the read operation.
Inventor(s): Ji Seong MUN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chan Keun KWON of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Ja Yoon GOO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hyeon Cheon SEOL of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Sung Hwa OK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Young Seung YOO of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F12/0802
CPC Code(s): G06F12/0802
Abstract: a memory device includes a plurality of memory planes, each including a plurality of memory banks; one or more plane groups, each comprising at least two memory planes sharing at least one peripheral circuit; a plurality of compressing circuits, each connected to a corresponding memory bank and outputting compressed data by compressing data read from the corresponding memory bank; a plurality of merge circuits, each receiving compressed data and at least one output control signal corresponding to a merge group of a plurality of merge groups, each merge circuit outputting, in response to at least one output control signal, merged data obtained by merging compressed data corresponding to memory banks grouped in the merge group; and an output buffer circuit latching and outputting the merged data in response to at least one output control signal. the merge group comprises at least two memory banks in a same plane group.
Inventor(s): In Ho JUNG of Gyeonggi-do (KR) for sk hynix inc., Jun Rye RHO of Gyeonggi-do (KR) for sk hynix inc., Jae Yong PARK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F13/18, G06F13/16
CPC Code(s): G06F13/18
Abstract: provided herein may be a memory controller. the memory controller may include a shared memory configured to store data, a hardware group configured to generate entry data including result data of an operation corresponding to a command, and output an interrupt signal generated in response to storage of the entry data, and a processor group configured to receive the entry data from the shared memory, wherein the processor group includes an interface converter configured to manage first index information of the entry data in response to the interrupt signal, and generate a first address for the entry data based on the first index information, and a data transmitter configured to receive, based on a first address, the entry data through a first interface using a data input/output scheme, and transfer the received entry data to a processor through a second interface using a fixed data input/output scheme.
Inventor(s): Ki Sung KIM of Gyeonggi-do (KR) for sk hynix inc., Wun Mo YANG of Gyeonggi-do (KR) for sk hynix inc., Gun Woo YEON of Gyeonggi-do (KR) for sk hynix inc., Dong Kyu LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F13/28, G06F13/42
CPC Code(s): G06F13/28
Abstract: a peripheral component interconnect express (pcie) device includes a direct memory access (dma) device including a plurality of functions; and a pcie interface device for performing communication between a host and the dma device. the pcie interface device includes a reset operation controller for, when a plurality of reset signals are received from the host, grouping operations, which are the same as one another among reset operations respectively corresponding to the plurality of reset signals, determining a processing order of the reset operations, and performing the reset operations according to the processing order.
Inventor(s): Kazuhiro YAHATA of Tokyo (JP) for sk hynix inc.
IPC Code(s): G06T5/70, G06T3/4038, G06V10/54
CPC Code(s): G06T5/70
Abstract: an image signal processor capable of processing image signals and an image signal processing method for the same are disclosed. the image signal processor includes a remosaic processor configured to by perform remosaic processing on an input image to generate a converted image, a noise-amount estimator configured to estimate an amount of noise of the converted image based on preset noise-amount parameters and the input image, a noise-reduction-degree determiner configured to determine a degree of noise reduction and generate noise-reduction-degree information, and a noise suppression processor configured to generate an output image in which the degree of noise reduction is controlled based on the noise-reduction-degree information.
Inventor(s): Ji Hee HAN of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06T7/00, G06T7/11, G06T7/13, H04N25/60
CPC Code(s): G06T7/0002
Abstract: disclosed is an image processor and an image processing system including the same. the image processor includes an analyzer configured to generate quantified characteristic values of noise reflected in a captured image based on image values corresponding to the captured image, and a discriminator configured to determine whether the noise has occurred in the captured image based on the characteristic values.
Inventor(s): In Seok KONG of Gyeonggi-do (KR) for sk hynix inc., Gwan Woo KIM of Gyeonggi-do (KR) for sk hynix inc., Keun Seon AHN of Gyeonggi-do (KR) for sk hynix inc., Eun Ho YANG of Gyeonggi-do (KR) for sk hynix inc., Sung Hwa OK of Gyeonggi-do (KR) for sk hynix inc., Eun Ji CHOI of Gyeonggi-do (KR) for sk hynix inc., Jun Ho HONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/10
CPC Code(s): G11C7/1048
Abstract: disclosed is an interface circuit and a semiconductor device including the same. the interface circuit may include a data pad, a first driving circuit connected between the data pad and a first supply node, and configured to adjust a first resistance value applied between the data pad and the first supply node according to termination modes and selectively drive the data pad with a first supply voltage, and a first tuning circuit connected between the first supply node and a first voltage supply terminal, and configured to tune the first resistance value according to the termination modes.
Inventor(s): Geon KO of Gyeonggi-do (KR) for sk hynix inc., Choung Ki SONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/4093, H01L25/065, H01L25/18, H10B80/00
CPC Code(s): G11C11/4093
Abstract: an operation method of a buffer chip may include receiving first control signals for setting a first memory chip; buffering the first control signals and transmitting the buffered signals to the first memory chip; storing a setting value of the first memory chip in response to the first control signals; receiving second control signals for setting a second memory chip; buffering the second control signals and transmitting the buffered second control signals to the second memory chip; storing a setting value of the second memory chip in response to the second control signals; receiving third control signals for applying the setting value of the first memory chip; buffering the third control signals and transmitting the buffered third control signals to the first memory chip; and applying the stored setting value of the first memory chip as a setting value of a buffer chip in response to the third control signals.
Inventor(s): In Ku KANG of Icheon-si (KR) for sk hynix inc., Kyung Hoon Min of Icheon-si (KR) for sk hynix inc., Sung In Hong of Icheon-si (KR) for sk hynix inc., Yun Heub Song of Seoul (KR) for sk hynix inc., Jae Min Sim of Seoul (KR) for sk hynix inc., Ji Ho Song of Seoul (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10, G11C16/26
CPC Code(s): G11C16/3459
Abstract: a method of programming a three-dimensional semiconductor memory device includes applying a first word line programming voltage to a selected word line among the word lines, floating unselected word lines among the word lines, and applying a back-gate pass voltage to the back-gate electrode; applying a first word line verification voltage to the selected word line, applying a word line pass voltage to the unselected word lines, and applying a first back-gate verification voltage to the back-gate electrode; applying a second word line programming voltage to the selected word line, floating the unselected word lines, and applying the back-gate pass voltage to the back-gate electrode; and applying a second word line verification voltage to the selected word line, applying the word line pass voltage to the unselected word lines, and applying a second back-gate verification voltage to the back-gate electrode.
Inventor(s): Sung Kun PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L21/02, H01L21/304, H01L21/8234
CPC Code(s): H01L21/02362
Abstract: a method of manufacturing a semiconductor device may include forming a polishing stop layer on a substrate, forming a stack on the polishing stop layer, forming channel structures extending through the stack and the polishing stop layer and having different heights, polishing the substrate and the channel structures to expose the polishing stop layer, and removing the polishing stop layer.
Inventor(s): Woo Sung MOON of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Joon Seuk LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/00, H01L23/544
CPC Code(s): H01L24/05
Abstract: provided herein may be a semiconductor device and a method of manufacturing the same. the semiconductor device may include a first structure including a first chip area and a first scribe lane area, a second structure provided on the first structure, a first alignment key disposed in the first scribe lane area, at least one first bonding pad provided between the first alignment key and the first chip area, the first bonding pad bordering an upper surface of the first structure, and a second bonding pad bordering a lower surface of the second structure to contact the at least one first bonding pad.
Inventor(s): Yang Ho SUR of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Sun Ki CHO of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/06
Abstract: an external connection pad apparatus includes a first pad and a second pad. the first pad has a first surface area. the second pad has a second surface area larger than the first surface area.
Inventor(s): Han Sol PARK of Gyeonggi-do (KR) for sk hynix inc., Shin Hoo KIM of Gyeonggi-do (KR) for sk hynix inc., Jong Hyun RA of Gyeonggi-do (KR) for sk hynix inc., Gun Hee YUN of Gyeonggi-do (KR) for sk hynix inc., Seung Hwan LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N25/60, H04N25/704, H04N25/77
CPC Code(s): H04N25/60
Abstract: disclosed is an image sensor and an image processing system including the same, and the image sensor includes a first pixel pair arranged in a first row, and configured to generate, during a first single readout time, first and second pixel signals according to a first order, a second pixel pair arranged in the first row, and configured to generate, during the first single readout time, third and fourth pixel signals according to a second order which is different from the first order, and a row controller configured to control, during the first single readout time, the first pixel pair according to the first order and the second pixel pair according to the second order.
20250080877. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Hajime SUZUKI of Tokyo (JP) for sk hynix inc.
IPC Code(s): H04N25/77, H04N25/706, H04N25/711
CPC Code(s): H04N25/77
Abstract: an image sensing device includes a counter configured to generate first count data by counting pulses corresponding to photocharges, a shift register configured to store second count data corresponding to upper digits of the first count data, and an adder configured to sum the second count data and an overflow value indicating whether the first count data has overflowed.
Inventor(s): Wha Young KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: a semiconductor device and a method for fabricating the same are provided. the semiconductor device includes a substrate; a lower portion of a first conductive pattern disposed over the substrate and extending in a second direction; a stacked structure disposed over the lower portion of the first conductive pattern and having a pillar shape, the stacked structure including an upper portion of the first conductive pattern, an oxide semiconductor channel, and a second conductive pattern; and a word line extending in a first direction intersecting the second direction and facing at least a portion of a sidewall of the oxide semiconductor channel with a gate insulating layer therebetween, wherein the first conductive pattern includes a first conductive metal oxide, and the lower portion of the first conductive pattern corresponds to a bit line, and the upper portion of the first conductive pattern corresponds to a drain electrode.
Inventor(s): Min Chul SUNG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00, H01L29/423, H01L29/786
CPC Code(s): H10B12/315
Abstract: a method for fabricating a semiconductor device includes forming a cell mold including a dummy channel pattern and a plurality of mold layers over a lower structure; forming a horizontal conductive line that intersects with the dummy channel pattern; forming a dummy channel layer by trimming the dummy channel pattern; forming a data storage element that is coupled to a first side of the dummy channel layer; replacing the dummy channel layer with a channel layer; and forming a vertical conductive line that is coupled to a second side of the channel layer.
Inventor(s): Seung Hwan KIM of Gyeonggi-do (KR) for sk hynix inc., Kang Sik CHOI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/482
Abstract: a semiconductor device includes a common conductive line extending in a first direction; a memory cell array including a plurality of horizontal layers stacked in the first direction while sharing the common conductive line; and a selector structure operatively coupled to the common conductive line, wherein the selector structure includes, a plurality of select transistors stacked in the first direction; and a selector commonly coupled to the select transistors.
Inventor(s): Min Chul SUNG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/482
Abstract: a method for fabricating a semiconductor device includes: forming an isolation layer that defines a plurality of active regions over a substrate; forming a bit line stack over the substrate; forming a main hard mask layer over the bit line stack; forming a plurality of first sacrificial mask layers over the main hard mask layer; forming a plurality of second sacrificial mask layers overlapping with both side ends of the first sacrificial mask layers over the first sacrificial mask layers; forming a main hard mask layer pattern by using the first and second sacrificial mask layers as barriers and etching the main hard mask layer; and forming a bit line structure by using the main hard mask layer pattern as a barrier and etching the bit line stack.
Inventor(s): Hee Do NA of Gyeonggi-do (KR) for sk hynix inc., Hee Soo KIM of Gyeonggi-do (KR) for sk hynix inc., Yoon Soo OH of Gyeonggi-do (KR) for sk hynix inc., Chang Soo LEE of Gyeonggi-do (KR) for sk hynix inc., Chul Young HAM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B41/27, H10B43/27, H10B63/00
CPC Code(s): H10B41/27
Abstract: a semiconductor device may include a gate structure including insulating layers and conductive layers alternately stacked, a channel layer passing through the gate structure, an insulating core disposed in the channel layer, and a capping layer including a capping pattern disposed in the channel layer and a capping liner disposed between the capping pattern and the insulating core and extending between the channel layer and the capping pattern, wherein the capping liner and the capping pattern may include impurities having different concentrations.
Inventor(s): Na Yeong YANG of Gyeonggi-do (KR) for sk hynix inc., Ki Jun YUN of Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Gyeonggi-do (KR) for sk hynix inc., In Su PARK of Gyeonggi-do (KR) for sk hynix inc., Seok Min CHOI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B41/30, H10B41/23
CPC Code(s): H10B41/30
Abstract: a semiconductor device may include: a first gate structure; a second gate structure disposed over the first gate structure; and a channel structure including a first portion extending through the first gate structure, the first portion having a tapered cross section, a second portion having a tapered cross section, and a third portion connecting the first portion with the second portion, wherein the third portion has a vertical profile, and wherein the second portion and the third portion extends through the second gate structure.
20250081466. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Sung Wook JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/40, G11C16/08, H10B43/27
CPC Code(s): H10B43/40
Abstract: provided herein are a semiconductor memory device and a method of manufacturing the semiconductor memory device. the semiconductor memory device includes a transistor, a cell array structure, a molded insulating structure including a first area disposed between the transistor and the cell array structure and overlapping with the transistor and a second area extending sideways from the first area, a pass gate disposed in the second area of the molded insulating structure, an active pillar penetrating the pass gate, and a pass gate insulating layer disposed between the active pillar and the pass gate.
Inventor(s): Jae Hyuk PARK of Icheon (KR) for sk hynix inc.
IPC Code(s): H10B63/10, H10B63/00, H10N70/00, H10N70/20
CPC Code(s): H10B63/10
Abstract: a semiconductor device may include a first electrode, a second electrode, a variable resistance layer positioned between the first electrode and the second electrode and maintaining a phase before and after a program operation, a non-conductive sealing layer positioned between the first electrode and the variable resistance layer, and a nanostructure positioned inside the non-conductive sealing layer and spaced apart from the variable resistance layer.
Inventor(s): Kwan Woo DO of Gyeonggi-do (KR) for sk hynix inc., Wan Joo MAENG of Gyeonggi-do (KR) for sk hynix inc., Jeong Yeop LEE of Gyeonggi-do (KR) for sk hynix inc., Ki Vin IM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01G4/10, H01G4/008
CPC Code(s): H10D1/696
Abstract: embodiments of the present invention provide a semiconductor device capable of improving current leakage property and a method for fabricating the same. according to an embodiment of the present invention, a capacitor comprises: a lower electrode; a dielectric layer over the lower electrode; and an upper electrode over the dielectric layer, the upper electrode including a conductive carbon-containing layer, wherein a carbon content in the conductive carbon-containing layer is more than 5 at % and equal to or less than 10 at %.
20250081637. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Jong Hwan SHIN of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/802
Abstract: an image sensing device includes a semiconductor substrate, a first pixel region, and a second gate. the semiconductor substrate includes a first pixel region configured to include at least one first photoelectric conversion region and at least one first floating diffusion region, a second pixel region located adjacent to the first pixel region in a first direction and configured to include at least one second photoelectric conversion region and at least one second floating diffusion region, and a first inter-pixel isolation structure disposed between the first pixel region and the second pixel region. the first gate disposed over the semiconductor substrate extends to overlap the first pixel region, the first inter-pixel isolation structure, and the second pixel region. the second gate disposed at one side of the first gate on the semiconductor substrate extends to overlap the first pixel region, the first inter-pixel isolation structure, and the second pixel region.
Inventor(s): Jong Eun KIM of Icheon-si (KR) for sk hynix inc., Kyung Do KIM of Icheon-si (KR) for sk hynix inc., Hyung June YOON of Icheon-si (KR) for sk hynix inc., Jae Hyung JANG of Icheon-si (KR) for sk hynix inc., Hoon Moo CHOI of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/807
Abstract: an image sensing device includes a substrate extending in a first direction and a second direction and including a first surface and a second surface; a plurality of unit pixel regions supported by the substrate to generate signal carriers through conversion of incident light; a plurality of circuit structures arranged to be spaced apart from each other in the first direction to generate a current in the substrate and capture the signal carriers carried by the current; a first isolation structure disposed between adjacent unit pixel regions in the substrate and extending vertically in a depth direction of the substrate while extending in the second direction; and a plurality of second isolation structures located on two opposite sides of the plurality of circuit structures in the second direction within the substrate, and arranged to extend obliquely in a depth direction in the substrate while extending in the first direction.
20250081652. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Sang Jin PARK of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/807
Abstract: an image sensing device includes a semiconductor substrate; unit pixels supported by the semiconductor substrate to detect light incident to the unit pixels and to convert detected light into pixel signal, and an inter-pixel isolation structure disposed between adjacent unit pixels to physically isolate the adjacent unit pixel from each other. each unit pixel includes photoelectric conversion elements, an inner-pixel isolation structure disposed between adjacent photoelectric conversion elements within the unit pixel and at least one overflow path configured to interconnect the photoelectric conversion elements within the unit pixel, and wherein each unit pixel is shaped in a triangular shape when viewed in a plane.
Inventor(s): Soo Man SEO of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10N50/10, H10B61/00, H10N50/01, H10N59/00
CPC Code(s): H10N50/10
Abstract: a semiconductor device and a method for fabricating the same are provided. the semiconductor device includes: a substrate; a first magnetic tunnel junction structure disposed over a portion of the substrate and including a first free layer; a first hard mask layer disposed over the first free layer; a second magnetic tunnel junction structure disposed over another portion of the substrate and including a second free layer having a thickness smaller than a thickness of the first free layer; a second hard mask layer disposed over the second free layer; and a doped layer interposed between the second free layer and the second hard mask layer and having conductivity.
- SK hynix Inc.
- G03F1/62
- CPC G03F1/62
- Sk hynix inc.
- G06F3/06
- CPC G06F3/0619
- CPC G06F3/062
- CPC G06F3/0647
- G06F7/556
- G06F5/01
- G06F7/499
- CPC G06F7/556
- G06F11/10
- CPC G06F11/106
- G06F12/02
- CPC G06F12/0246
- G06F12/0802
- CPC G06F12/0802
- G06F13/18
- G06F13/16
- CPC G06F13/18
- G06F13/28
- G06F13/42
- CPC G06F13/28
- G06T5/70
- G06T3/4038
- G06V10/54
- CPC G06T5/70
- G06T7/00
- G06T7/11
- G06T7/13
- H04N25/60
- CPC G06T7/0002
- G11C7/10
- CPC G11C7/1048
- G11C11/4093
- H01L25/065
- H01L25/18
- H10B80/00
- CPC G11C11/4093
- G11C16/34
- G11C16/04
- G11C16/10
- G11C16/26
- CPC G11C16/3459
- H01L21/02
- H01L21/304
- H01L21/8234
- CPC H01L21/02362
- H01L23/00
- H01L23/544
- CPC H01L24/05
- CPC H01L24/06
- H04N25/704
- H04N25/77
- CPC H04N25/60
- H04N25/706
- H04N25/711
- CPC H04N25/77
- H10B12/00
- CPC H10B12/315
- H01L29/423
- H01L29/786
- CPC H10B12/482
- H10B41/27
- H10B43/27
- H10B63/00
- CPC H10B41/27
- H10B41/30
- H10B41/23
- CPC H10B41/30
- H10B43/40
- G11C16/08
- CPC H10B43/40
- H10B63/10
- H10N70/00
- H10N70/20
- CPC H10B63/10
- H01G4/10
- H01G4/008
- CPC H10D1/696
- H01L27/146
- CPC H10F39/802
- CPC H10F39/807
- H10N50/10
- H10B61/00
- H10N50/01
- H10N59/00
- CPC H10N50/10
