SK hynix Inc. patent applications on March 13th, 2025
Patent Applications by SK hynix Inc. on March 13th, 2025
SK hynix Inc.: 25 patent applications
SK hynix Inc. has applied for patents in the areas of H10B43/27 (6), H10B41/27 (6), H10B43/40 (3), G06F3/06 (3), H10B41/10 (3) H10B41/41 (2), G03F7/2022 (1), H03L7/095 (1), H10D30/6728 (1), H10D1/20 (1)
With keywords such as: signal, layer, memory, device, circuit, configured, pattern, output, semiconductor, and voltage in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Jong Hoon KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G03F7/20, H01L21/027, H01L21/033
CPC Code(s): G03F7/2022
Abstract: an exposure mask for forming a pattern having a first width includes a first line, a second line, and at least one bridge line. the first line may be extended in a first direction. the first line has a second width narrower than the first width. the second line may be extended parallel to and spaced apart from the first line. the second line is formed having the second width. the bridge line may be connected between the first line and the second line.
Inventor(s): Yeon Ho LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Yong Suk CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F1/08, G06F1/10, G06F1/12
CPC Code(s): G06F1/08
Abstract: a clock generating circuit includes a buffer circuit and a phase compensating circuit. the buffer circuit buffers an input clock signal to generate an output clock signal. the phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.
20250085879. MEMORY SYSTEM AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): In Mo KWAK of Icheon-si (KR) for sk hynix inc., Jeong Su PARK of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: memory systems and methods of operating the memory systems are disclosed. a memory system including a plurality of data storage zones may comprise a memory device including a plurality of zones for storing data, and a memory controller configured to control the memory device in performing a write operation in the memory device. the memory controller is configured to, upon performing a write operation corresponding to a write request received from a host, update a logical write pointer and a physical write pointer associated with a zone that is targeted to perform the write operation corresponding to the write request received from the host, and upon performing a write operation corresponding an internal write command internally issued by the memory controller, update a physical write pointer associated with the zone that is targeted to perform the write operation corresponding to an internal write command issued by the memory controller.
Inventor(s): Kyu Ho CHOI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0658
Abstract: a storage device may update, when executing a recovery operation for a sudden power-off, zone information for a target zone among a plurality of zones, and may transmit, after updating the zone information, an exception event alert message to a host. further, the storage device may receive, after transmitting the exception event alert message, a command from the host, and may transmit updated zone information to the host as a response to the command.
20250085894. CONTROLLER, STORAGE DEVICE AND COMPUTING SYSTEM_simplified_abstract_(sk hynix inc.)
Inventor(s): Jung Ho LEE of Icheon-si (KR) for sk hynix inc., Min Su SON of Icheon-si (KR) for sk hynix inc., Sung Ju YOO of Icheon-si (KR) for sk hynix inc., Ji Hun CHOI of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a storage device manages memory use data, such as map data which the storage device manages using a host memory, as journal data in a buffer memory located inside the storage device in a low power mode. the memory use data may be managed by updating journal data during the low power mode, and a command of a host device may be processed by updated journal data after switching from a low power mode to an active mode.
Inventor(s): Hyeong Soo KIM of Icheon-si (KR) for sk hynix inc., Dong Kyun KIM of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F11/14, G06F9/50
CPC Code(s): G06F11/1451
Abstract: in an embodiment of the disclosed technology, a data storage device includes at least one memory device including a plurality of memory regions configured to store data, a first controller configured to allocate the plurality of memory regions according to a memory allocation request of one or more host devices, and a second controller configured to: generate, in response to a snapshot request of a first host device among the one or more host devices, snapshot data corresponding to at least part of the data stored in at least part of the plurality of memory regions allocated to the first host device; and store the snapshot data into an auxiliary storage device coupled to the second controller.
20250086105. STORAGE DEVICE FOR CHANGING MAP UPDATE MODE_simplified_abstract_(sk hynix inc.)
Inventor(s): Sung Jin PARK of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F12/02, G06F12/0891
CPC Code(s): G06F12/0246
Abstract: a storage device includes a memory apparatus configured to store logical to physical (l2p) information, and a controller coupled to be in communications with the memory apparatus and configured to selectively change a map update mode based on a map update history after performing a map management operation on the l2p information.
Inventor(s): Ji Hee HAN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06T7/593, G06T3/40, G06T5/20, G06T5/70, H04N13/00, H04N13/207, H04N23/81
CPC Code(s): G06T7/593
Abstract: the present technology relates to an image signal processor. according to the present technology, an image signal processor may include a depth map generator configured to generate, based on a target resolution of an output image, a downsized left image and a downsized right image based on an input image received from an external device, and generate a depth map image indicating depth values corresponding to pixels included in the output image based on the downsized left image and the downsized right image, and a noise remover configured to perform guide filtering on the depth map image using the input image as a guide image and generate the output image.
Inventor(s): Woo Cheol LEE of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G11C5/06, G11C16/10, G11C16/26, H10B41/27, H10B43/27
CPC Code(s): G11C5/063
Abstract: a semiconductor device may include first and second transistors on a substrate. the first transistor may include first and second source/drain regions; a first channel region between the first and second source/drain regions; a first gate electrode over the first channel region; and a charge retention node between the first channel region and the first gate electrode. the second transistor may include third and fourth source/drain regions, a portion of the third source/drain region being connected to the charge retention node; a second channel region between the third and fourth source/drain regions; and a second gate electrode over the second channel region.
Inventor(s): Hee Youl LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/16
CPC Code(s): G11C16/102
Abstract: provided herein is a semiconductor memory device and a method of operating the same. the semiconductor memory device includes a first string group including at least one first memory string and a second string group including at least one second memory string, each string connected in parallel between the bit line and the source line, wherein the at least one first memory string and the at least one second memory string each include at least one down source select transistor, at least one first up source select transistor, and at least one second up source select transistor, and the at least one first up source select transistor of the at least one first memory string is programmed to a first state, and the at least one first up source select transistor of the at least one second memory string is programmed to a second state different from the first state.
20250087488. METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Ji Hoon KIM of Gyeonggi-do (KR) for sk hynix inc., Jae Han PARK of Gyeonggi-do (KR) for sk hynix inc., Chang Hun LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L21/033, H01L21/311
CPC Code(s): H01L21/0337
Abstract: the present invention is related to a method for fabricating a semiconductor device capable of forming fine patterns. the method for fabricating the semiconductor device according to the present invention may comprise forming an etch mask layer on an etch target layer; forming a spacer structure in which first spacers and second spacers are alternately disposed and spaced apart from each other on the etch mask layer; forming first spacer lines through selective etching of the first spacers; forming second spacer lines through selective etching of the second spacers; and etching the etch target layer to form a plurality of fine line patterns using the first and second spacer lines.
Inventor(s): Hyun Su PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H03K3/011, H03K3/037, H03K19/20, H03K5/00, H03K5/01
CPC Code(s): H03K3/011
Abstract: a signal driver circuit includes a pre-driving circuit, a driving signal generating circuit, a main driving circuit, and an output control circuit. the pre-driving circuit is configured to generate a first pre-driving signal and a second pre-driving signal based on an input signal and a clock signal. the driving signal generating circuit is configured to generate a pull-up driving signal and a pull-down driving signal based on the first pre-driving signal, the second pre-driving signal, and a complementary delayed output signal. the main driving circuit is configured to generate an output signal based on the pull-up driving signal and the pull-down driving signal. the complementary delayed output signal is generated by delaying the output signal. the output control circuit is configured to latch the output signal and configured to delay the output signal to generate a delayed output signal and the complementary delayed output signal.
Inventor(s): Junghan LEE of Gyeonggi-do (KR) for sk hynix inc., Jin Seok LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H03K19/0185, H02M3/07
CPC Code(s): H03K19/018521
Abstract: a pull-down circuit and a pull-up circuit for using various voltages, and a voltage supply circuit including the pull-down circuit and the pull-up circuit are disclosed. the pull-up circuit includes a sink circuit configured to receive a charge pump voltage from a charge pump circuit and pull up the charge pump voltage of the charge pump circuit to a ground voltage, wherein the charge pump voltage is less than the ground voltage, and a level shifter configured to generate a level shifter output voltage and a one-shot signal in response to a charge pump enable signal controlling the charge pump circuit wherein the level shifter output voltage controls the sink circuit, and the one-shot signal prevents floating of a node through which the level shifter output voltage is output.
20250088195. ELECTRONIC DEVICES INCLUDING LOCK DETECTING CIRCUIT_simplified_abstract_(sk hynix inc.)
Inventor(s): Jae Min SHIM of Icheon (KR) for sk hynix inc.
IPC Code(s): H03L7/095, G11C11/4076, H03K3/037
CPC Code(s): H03L7/095
Abstract: a lock detecting circuit includes a pre-clock detection signal generating circuit configured to detect phases of a first clock and a second clock to generate a first pre-clock detection signal and a second pre-clock detection signal based on the detected phases, a first clock detection signal generating circuit configured to generate a first clock detection signal by adjusting a pulse width of the first pre-clock detection signal, a second clock detection signal generating circuit configured to generate a second clock detection signal by adjusting a pulse width of the second pre-clock detection signal, and a lock control circuit configured to detect a phase difference between the first clock and the second clock, based on the first clock detection signal and the second clock detection signal to generate a lock signal.
Inventor(s): Yusuke YATA of Tokyo (JP) for sk hynix inc.
IPC Code(s): H04N23/76, G01S17/36, H04N25/703
CPC Code(s): H04N23/76
Abstract: an image sensing device includes a phase difference calculator configured to calculate a phase difference between a modulated light signal and reflected light based on a plurality of captured data generated by a plurality of modulation control signals, each of which has a predetermined modulation phase difference with respect to the modulated light signal; a phase difference corrector configured to calculate a contrast, which is a ratio of an amplitude component of the reflected light to an intensity component of the reflected light, using the plurality of captured data, and determine an aliasing value corresponding to the contrast; and a distance calculator configured to calculate a distance to a target object using a corrected phase difference obtained by correcting the phase difference according to the aliasing value.
20250088768. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Seung Hwan LEE of Gyeonggi-do (KR) for sk hynix inc., Gun Hee YUN of Gyeonggi-do (KR) for sk hynix inc., Min Kyu KIM of Gyeonggi-do (KR) for sk hynix inc., Han Sol PARK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N25/77, H04N25/709, H04N25/76, H04N25/78
CPC Code(s): H04N25/77
Abstract: an image sensing device for obtaining an image of a scene by sensing light is disclosed. the image sensing device includes a pixel circuit configured to output a pixel signal based on a voltage level of a floating diffusion node at which charges generated corresponding to an intensity of incident light are accumulated, a voltage controller configured to control a voltage level of an output node where the pixel signal is output in response to a voltage control signal, a conversion circuit configured to convert the pixel signal into a digital signal, and a voltage trimming circuit configured to control the voltage control signal based on the digital signal.
Inventor(s): Han Sol PARK of Gyeonggi-do (KR) for sk hynix inc., Shin Hoo KIM of Gyeonggi-do (KR) for sk hynix inc., Yu Jin PARK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N25/78, H04N25/77
CPC Code(s): H04N25/78
Abstract: a ramp generation circuit includes a ramping voltage generator configured to generate a ramping voltage that changes depending on a first slope or a second slope, a blocking capacitor configured to transmit the ramping voltage to a transfer node, a signal output unit configured to amplify a voltage of the transfer node and to output a ramp output signal to an output node, and a ramp switch configured to selectively connect the transfer node to the output node.
Inventor(s): Nam Jae LEE of Cheongju-si Chungcheongbuk-do (KR) for sk hynix inc.
IPC Code(s): H10B41/27, H01L21/225, H01L21/324, H10B43/20, H10B43/27, H10B63/00
CPC Code(s): H10B41/27
Abstract: a method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening.
Inventor(s): Jae Young OH of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Nam Jae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B41/41, H10B41/10, H10B41/27, H10B43/10, H10B43/27, H10B43/40
CPC Code(s): H10B41/41
Abstract: there are provided a semiconductor memory device and a method of manufacturing a semiconductor memory device. the semiconductor memory device includes a conductive pattern, an etch stop layer on the conductive pattern, a conductive bonding pattern including a contact portion connected to the conductive pattern, and a pad portion extending from the contact portion, a first dielectric layer disposed on the etch stop layer and spaced apart from the conductive bonding pattern, and a second dielectric layer including a first portion surrounding a sidewall of the contact portion of the conductive bonding pattern between the pad portion of the conductive bonding pattern and the etch stop layer, and a second portion extending from the first portion to cover an upper surface of the first dielectric layer.
Inventor(s): Jae Young OH of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Nam Jae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B41/41, H10B41/10, H10B41/27, H10B43/10, H10B43/27, H10B43/40
CPC Code(s): H10B41/41
Abstract: there are provided a semiconductor memory device and a method of manufacturing a semiconductor memory device. the semiconductor memory device includes a conductive pattern, an etch stop layer on the conductive pattern, a conductive bonding pattern including a contact portion connected to the conductive pattern, and a pad portion extending from the contact portion, a first dielectric layer disposed on the etch stop layer and spaced apart from the conductive bonding pattern, and a second dielectric layer including a first portion surrounding a sidewall of the contact portion of the conductive bonding pattern between the pad portion of the conductive bonding pattern and the etch stop layer, and a second portion extending from the first portion to cover an upper surface of the first dielectric layer.
Inventor(s): Byung Wook BAE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H01L23/00, H01L25/00, H01L25/065, H01L25/18, H10B41/27
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device includes a bit line, a common source pattern above the bit line, a channel layer in contact with the common source pattern, the channel layer extending toward the bit line, and a filling insulating layer disposed between the bit line and the common source pattern, the filling insulating layer surrounding a first part of the channel layer. the semiconductor memory device also includes a gate stack structure disposed between the bit line and the filling insulating layer, the gate stack structure surrounding a second part of the channel layer. the semiconductor memory device further includes a first etch stop pattern on a sidewall of the filling insulating layer, a second etch stop pattern between the first etch stop pattern and the filling insulating layer, and a memory pattern between the gate stack structure and the channel layer.
Inventor(s): Byung Wook BAE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Eun Seok CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/40, H10B41/10, H10B41/27, H10B41/40, H10B43/10, H10B43/27
CPC Code(s): H10B43/40
Abstract: there are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. the semiconductor memory device includes a gate stack comprising a plurality of first interlayer insulating patterns and a plurality of conductive patterns alternately stacked, a dummy stack comprising a plurality of second interlayer insulating patterns and a plurality of sacrificial insulating layers, a plurality of step-shaped grooves defined at different depths in the gate stack, a plurality of openings passing through the dummy stack and spaced apart from each other, a first gap-fill insulating pattern filling the plurality of step-shaped grooves, a second gap-fill insulating pattern filling the plurality of openings, a plurality of conductive gate contacts passing through the first gap-fill insulating pattern and connected to the plurality of conductive patterns, and a plurality of conductive peripheral circuit contacts passing through the second gap-fill insulating pattern.
20250089274. SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Hyeong Yeol PARK of Gyeonggi-do (KR) for sk hynix inc., Hye Min IM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01F17/00, H01L23/522
CPC Code(s): H10D1/20
Abstract: in an embodiment, a semiconductor device may include a t-coil transferring a signal from the outside to an internal circuit, a plurality of power lines transferring power from the outside to the internal circuit and disposed below the t-coil and at least one capacitor connected between the plurality of power lines.
20250089296. SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR_simplified_abstract_(sk hynix inc.)
Inventor(s): Dong Jin KO of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L29/786, H10B12/00
CPC Code(s): H10D30/6728
Abstract: a semiconductor device includes a substrate; a first electrode layer disposed over the substrate; an interlayer insulating layer having an opening that exposes the first electrode layer; an oxide semiconductor layer formed along a surface of the opening and connected to the first electrode layer; a gate insulating layer formed along a surface of the oxide semiconductor layer; a stacked structure including a first gate electrode layer, a first insulating layer, a second gate electrode layer, and a second insulating layer stacked in a vertical direction while filling a remaining space of the opening in which the oxide semiconductor layer and the gate insulating layer are formed; and a second electrode layer disposed over the stacked structure and the oxide semiconductor layer and connected to the oxide semiconductor layer.
Inventor(s): Cha Deok DONG of Icheon-si (KR) for sk hynix inc., Jeong Myeong KIM of Icheon-si (KR) for sk hynix inc., Keo Rock CHOI of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10N70/00, H10B63/00
CPC Code(s): H10N70/841
Abstract: a semiconductor device and a method for fabricating the same are provided. the semiconductor device includes a selector pattern including an insulating material doped with a dopant to exhibit different electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage, wherein the selector pattern includes a first region that is formed in an edge extending from a sidewall of the selector pattern and a second region that has a sidewall in contact with the first region, and a concentration of the dopant in the first region is different from a concentration of the dopant in the second region.
- SK hynix Inc.
- G03F7/20
- H01L21/027
- H01L21/033
- CPC G03F7/2022
- Sk hynix inc.
- G06F1/08
- G06F1/10
- G06F1/12
- CPC G06F1/08
- G06F3/06
- CPC G06F3/064
- CPC G06F3/0658
- CPC G06F3/0659
- G06F11/14
- G06F9/50
- CPC G06F11/1451
- G06F12/02
- G06F12/0891
- CPC G06F12/0246
- G06T7/593
- G06T3/40
- G06T5/20
- G06T5/70
- H04N13/00
- H04N13/207
- H04N23/81
- CPC G06T7/593
- G11C5/06
- G11C16/10
- G11C16/26
- H10B41/27
- H10B43/27
- CPC G11C5/063
- G11C16/04
- G11C16/16
- CPC G11C16/102
- H01L21/311
- CPC H01L21/0337
- H03K3/011
- H03K3/037
- H03K19/20
- H03K5/00
- H03K5/01
- CPC H03K3/011
- H03K19/0185
- H02M3/07
- CPC H03K19/018521
- H03L7/095
- G11C11/4076
- CPC H03L7/095
- H04N23/76
- G01S17/36
- H04N25/703
- CPC H04N23/76
- H04N25/77
- H04N25/709
- H04N25/76
- H04N25/78
- CPC H04N25/77
- CPC H04N25/78
- H01L21/225
- H01L21/324
- H10B43/20
- H10B63/00
- CPC H10B41/27
- H10B41/41
- H10B41/10
- H10B43/10
- H10B43/40
- CPC H10B41/41
- H01L23/00
- H01L25/00
- H01L25/065
- H01L25/18
- CPC H10B43/27
- H10B41/40
- CPC H10B43/40
- H01F17/00
- H01L23/522
- CPC H10D1/20
- H01L29/786
- H10B12/00
- CPC H10D30/6728
- H10N70/00
- CPC H10N70/841
