SK hynix Inc. patent applications on July 25th, 2024
Patent Applications by SK hynix Inc. on July 25th, 2024
SK hynix Inc.: 18 patent applications
SK hynix Inc. has applied for patents in the areas of H10B63/00 (4), G11C7/10 (3), G11C7/22 (3), H10B43/27 (2), H10N70/00 (2) G01S7/487 (1), G11C16/10 (1), H10B63/845 (1), H10B63/80 (1), H10B43/35 (1)
With keywords such as: memory, device, configured, data, region, circuit, signals, layer, chip, and pattern in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Min Hyuk KIM of Daejeon (KR) for sk hynix inc., Daniel S. Jeon of Daejeon (KR) for sk hynix inc.
IPC Code(s): G01S7/487, G01S7/4865, G01S17/894
CPC Code(s): G01S7/487
Abstract: detecting a multi-path interference component in a time-of-flight (tof) camera may be performed by generating a confidence map in which a distortion area attributable to a multi-path interference component included in a reflection modulation signals is specified, where the reflection modulation signals is generated when two modulation signals emitted from a light source to a subject return to the tof camera after being reflected by the subject. correcting the multi-path interference component corrects distortion attributable to a multi-path interference component, which may include correcting only the distortion area specified in the confidence map. detecting the multi-path interference component in a tof camera includes collecting the reflection modulation signal at a plurality of different times, calculating amplitudes and offsets of the collected reflection modulation signals, determining whether a multi-path interference component is included in the reflection modulation signal, and generating the confidence map.
Inventor(s): Munseon JANG of Gyeonggi-do (KR) for sk hynix inc., Hoiju CHUNG of San Jose CA (US) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: a method for operating a memory includes: a first region error checking operation of reading data of n memory cells from each of k, rows, where k is an integer equal to or greater than 2, by using n first bit line sense amplifiers, where n is an integer equal to or greater than 2 and checking errors; processing first region error information based on the number of errors detected in the first region error checking operation; a second region error checking operation of reading data of n memory cells in each of k rows by using n second bit line sense amplifiers and checking errors; and processing second region error information based on the number of errors detected in the second region error checking operation.
Inventor(s): Yong Tae JEON of Icheon-si (KR) for sk hynix inc., Dae Sik PARK of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F11/20, G06F13/42
CPC Code(s): G06F11/2005
Abstract: a peripheral component interconnect express (pcie) device includes a plurality of lanes comprising a plurality of ports, a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes the remaining of lanes, except for a fail lane from among the plurality of lanes, and an eq controller performing an equalization operation for determining a transmitter or receiver setting of each of the remaining lanes, wherein the eq controller determining a final eq coefficient using a log information and an error information.
20240248823. CONTROLLER, STORAGE DEVICE AND TEST SYSTEM_simplified_abstract_(sk hynix inc.)
Inventor(s): Seung Hwa BAEK of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F11/263, G06F11/27
CPC Code(s): G06F11/2635
Abstract: a storage device operates in host mode or device mode, and the storage device operating in host mode may transmit and receive various information units with the storage device operating in device mode to perform tests on the storage device operating in device mode, thereby performing the test of a storage device in development.
Inventor(s): Gun Wook LEE of Seoul (KR) for sk hynix inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0253
Abstract: a data storage device may include a storage including a plurality of memory blocks composed of system memory blocks for storing system data and user memory blocks for storing user data; and a controller configured to: control exchange of the system and user data with the storage in response to a request of a host device; and determine whether a start condition for performing a garbage collection operation on the storage is satisfied, based on a number of bad memory blocks in the plurality of memory blocks.
Inventor(s): Dong Gyun KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jeong Yong SONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jae Yoon YOO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Bo Ra LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06T3/40, G06V10/25, G06V10/56, G06V10/75
CPC Code(s): G06T3/4007
Abstract: an image processing device, and a pixel interpolation method, includes a preprocessor configured to generate a region of interest having a preset size based on pixel values received from an image sensor including white pixels and configured to determine an interpolation direction in the region of interest. the image processing device and interpolation method also includes a pixel interpolator configured to determine a second target pixel corresponding to the interpolation direction based on a first target pixel included in the region of interest and configured to calculate an interpolated white pixel value of the first target pixel based on a ratio of pixel values of adjacent white pixels adjacent to the first target pixel and the second target pixel to pixel values corresponding to a color of the first target pixel.
Inventor(s): Choung Ki SONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/10, G11C7/22
CPC Code(s): G11C7/1039
Abstract: a buffer chip includes: a chip select signal reception circuit configured to receive chip select signals transmitted from a memory controller; a command address reception circuit configured to receive command address signals transmitted from the memory controller; a chip select signal transmission circuit configured to transmit the chip select signals to a plurality of memory chips; a command address transmission circuit configured to transmit the command address signals to the plurality of memory chips; and a command address fixing circuit configured to fix levels of at least one of the command address signals transmitted by the command address transmission circuit when the chip select signals are deactivated for a predetermined time or more.
Inventor(s): Choung Ki SONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Kwan Dong KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/10, G11C7/22
CPC Code(s): G11C7/109
Abstract: a semiconductor package may include: a package substrate including a plurality of terminals for communication with a memory controller and a plurality of bonding pads for communication inside a package; a buffer chip located on the package substrate; a plurality of memory chips stacked on the buffer chip; and a plurality of wires connecting the plurality of bonding pads and the plurality of memory chips. the buffer chip may communicate with the memory controller through the plurality of terminals of the package substrate, and the plurality of memory chips may communicate with the buffer chip through the plurality of wires and the plurality of bonding pads of the package substrate.
Inventor(s): Choung Ki SONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/4076, H01L23/00, H01L25/18, H10B80/00
CPC Code(s): G11C11/4076
Abstract: a buffer chip includes a control signal transmission path that transmitting, to a memory chip, control signals transmitted from a memory controller; a data transmission path including a variable delay circuit having a delay value adjusted by a delay code and transmitting, to the memory controller, data transmitted from the memory chip; a ring oscillator generating a ring oscillator clock; a counter circuit configured to count the number of toggles of the ring oscillator clock while an external clock toggles a reference number of times; a reference value storage circuit configured to store a counting value of the counter circuit as a reference value; a current value storage circuit configured to store the counting value of the counter circuit as a current value in response to a comparison signal; and a code generation circuit configured to generate the delay code by comparing the reference value with the current value.
Inventor(s): Choung Ki SONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/4093, H01L25/065, H01L25/18, H10B80/00
CPC Code(s): G11C11/4093
Abstract: a buffer chip includes: an external control signal interface configured to receive control signals transmitted from a memory controller; an internal control signal interface configured to transmit the control signals to a plurality of memory chips; an external data interface configured to transmit and receive (transmit/receive) data to and from (to/from) the memory controller; an internal data interface configured to transmit/receive the data to/from the plurality of memory chips; and a loopback circuit configured to be activated in a loopback mode to receive the control signals transmitted by the internal control signal interface, and transmits the control signals to the external data interface.
20240249774. MEMORY DEVICE AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Sang Tae AHN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Sung Min LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/14
CPC Code(s): G11C16/10
Abstract: provided herein may be a memory device and a method of operating the same. the memory device may include a memory block including strings, each including first memory cells coupled between a first dummy cell and a second dummy cell and second memory cells coupled between third dummy cell and fourth dummy cell, and a peripheral circuit performing a normal program operation on first and second memory cells, or a soft program operation on first to fourth dummy cells, wherein the peripheral circuit is configured to, perform a soft program operation on the fourth dummy cell which is farthest from an area to which the precharge voltage is applied and perform a normal program operation on second memory cells, wherein the precharge voltage is applied to the area during the normal program operation, and wherein the area is adjacent to the first dummy cells.
Inventor(s): Won Tae KOO of Gyeonggi-do (KR) for sk hynix inc., Mir IM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L21/02
CPC Code(s): H01L21/02356
Abstract: in a method of manufacturing a semiconductor device, a plurality of pattern structures disposed on a substrate and having sidewall surfaces extending in a direction perpendicular to a surface of the substrate are provided. an amorphous dielectric layer is formed on at least the sidewall surfaces of the plurality of pattern structures. a plurality of metal particles are distributed on the amorphous dielectric layer. a first crystalline dielectric layer by thermally treating the amorphous dielectric layer using laser light. in thermally treating the amorphous dielectric layer, the laser light is irradiated onto the amorphous dielectric layer from upper sides of the plurality of pattern structures, wherein the irradiated laser light is scattered from the plurality of metal particles.
20240250674. SEMICONDUCTOR SYSTEMS WITH DATA CLOCK APPLIED_simplified_abstract_(sk hynix inc.)
Inventor(s): Kyu Dong HWANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H03K5/156, G11C7/10, G11C7/22
CPC Code(s): H03K5/1565
Abstract: a semiconductor system includes a controller, configured to: adjust a duty ratio of a data clock according to a system rate in a half rate section, generate a transmission data clock and, transmit the transmission data clock through a channel. the system also includes a semiconductor device configured to receive the transmission data clock through the channel as a reception data clock, and generate an internal data clock for a data input and output operation, based on the reception data clock.
Inventor(s): Jin Ha KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/27, H10B63/00
CPC Code(s): H10B43/27
Abstract: a semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked with each other, and a channel layer passing through the stacked structure, wherein the channel layer is a single layer, the single layer including a first gidl region, a cell region, and a second gidl region, and the first gidl region has a greater thickness than each of the cell region and the second gidl region.
Inventor(s): Nam Jae LEE of Cheongju-si Chungcheongbuk-do (KR) for sk hynix inc.
IPC Code(s): H10B43/35, H01L21/768, H01L23/522, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27
CPC Code(s): H10B43/35
Abstract: a semiconductor device and a method of manufacturing a semiconductor device may be provided. the semiconductor device may include first and second vertical conductive patterns isolated from each other by a first slit. the semiconductor device may include at least one first half conductive pattern extending toward a first region disposed at one side of the first slit from the first vertical conductive pattern. the semiconductor device may include at least one second half conductive pattern extending toward a second region disposed at the other side of the first slit from the second vertical conductive pattern.
Inventor(s): Chi Ho KIM of Icheon (KR) for sk hynix inc., Kyung Seop KIM of Icheon (KR) for sk hynix inc., Hun KIM of Icheon (KR) for sk hynix inc., Young Cheol SONG of Icheon (KR) for sk hynix inc., Chang Jun YOO of Icheon (KR) for sk hynix inc., Jae Wan CHOI of Icheon (KR) for sk hynix inc.
IPC Code(s): H10B63/00, H10B63/10
CPC Code(s): H10B63/80
Abstract: a semiconductor device includes: a substrate; a plurality of memory cells positioned over the substrate, each of the plurality of memory cells having a multi-layer structure including a memory pattern; a sealing layer pattern filling a lower portion of a space between the memory cells, the lower portion being positioned below a bottom surface of the memory pattern; a liner layer pattern formed along a surface of an upper portion of the space to partially fill the upper portion; and a dielectric layer pattern filling a remaining portion of the space unfilled by the sealing layer pattern and the liner layer pattern.
Inventor(s): Hyung Keun KIM of Icheon (KR) for sk hynix inc., Jun Ku AHN of Icheon (KR) for sk hynix inc., Jun Young LIM of Icheon (KR) for sk hynix inc., Sung Lae CHO of Icheon (KR) for sk hynix inc.
IPC Code(s): H10B63/00, H10B61/00, H10N50/01, H10N70/00
CPC Code(s): H10B63/845
Abstract: a semiconductor device includes a stack structure including first electrodes and insulating layers alternately stacked on each other, a second electrode passing through the stack structure, and variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes. each of the first electrodes includes a first sidewall facing the second electrode, and each of the insulating layers includes a second sidewall facing the second electrode. at least a part of each of the variable resistance patterns protrudes farther towards the second electrode than the second sidewall.
Inventor(s): Myoung Sub KIM of Icheon (KR) for sk hynix inc., Tae Hoon KIM of Icheon (KR) for sk hynix inc., Beom Seok LEE of Icheon (KR) for sk hynix inc., Seung Yun LEE of Icheon (KR) for sk hynix inc., Hwan Jun ZANG of Icheon (KR) for sk hynix inc., Byung Jick CHO of Icheon (KR) for sk hynix inc., Ji Sun HAN of Icheon (KR) for sk hynix inc.
IPC Code(s): H10N70/00, H10B61/00, H10B63/00, H10N50/01, H10N50/80, H10N70/20
CPC Code(s): H10N70/841
Abstract: a method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. the second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
- SK hynix Inc.
- G01S7/487
- G01S7/4865
- G01S17/894
- CPC G01S7/487
- Sk hynix inc.
- G06F3/06
- CPC G06F3/0619
- G06F11/20
- G06F13/42
- CPC G06F11/2005
- G06F11/263
- G06F11/27
- CPC G06F11/2635
- G06F12/02
- CPC G06F12/0253
- G06T3/40
- G06V10/25
- G06V10/56
- G06V10/75
- CPC G06T3/4007
- G11C7/10
- G11C7/22
- CPC G11C7/1039
- CPC G11C7/109
- G11C11/4076
- H01L23/00
- H01L25/18
- H10B80/00
- CPC G11C11/4076
- G11C11/4093
- H01L25/065
- CPC G11C11/4093
- G11C16/10
- G11C16/14
- CPC G11C16/10
- H01L21/02
- CPC H01L21/02356
- H03K5/156
- CPC H03K5/1565
- H10B43/27
- H10B41/27
- H10B63/00
- CPC H10B43/27
- H10B43/35
- H01L21/768
- H01L23/522
- H10B41/10
- H10B41/35
- H10B43/10
- CPC H10B43/35
- H10B63/10
- CPC H10B63/80
- H10B61/00
- H10N50/01
- H10N70/00
- CPC H10B63/845
- H10N50/80
- H10N70/20
- CPC H10N70/841
