SK hynix Inc. patent applications on July 18th, 2024
Patent Applications by SK hynix Inc. on July 18th, 2024
SK hynix Inc.: 21 patent applications
SK hynix Inc. has applied for patents in the areas of G06F3/06 (5), G06T5/00 (2), H10B43/35 (2), H10B43/27 (2), H01L23/00 (2) G06F3/0659 (2), G01S17/32 (1), G06T7/97 (1), H10B43/23 (1), H10B12/315 (1)
With keywords such as: device, data, layer, configured, memory, based, control, information, bonding, and structure in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Yusuke Yata of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G01S17/32, G01S7/4911, G01S7/4915
CPC Code(s): G01S17/32
Abstract: provided herein is a distance measurement device. the distance measurement device includes a controller configured to generate a modulated light control signal based on a first modulation frequency selected from among a plurality of modulation frequencies, a length per code determined based on the plurality of modulation frequencies, and number of codes in a pseudo noise code determining whether a pulse, included in each code and corresponding to the first modulation frequency, is inverted, a light source configured to output modulated light in response to the modulated light control signal, and a unit pixel including a first tap to which a first modulation voltage determined based on the modulated light control signal is applied and a second tap to which a second modulation voltage that is inverted from the first modulation voltage is applied.
Inventor(s): Ki Young KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0634
Abstract: a memory system which includes a nonvolatile memory device configured to store a mapping table that includes a plurality of map segments each having mapping information between a logical address and a physical address; and a controller configured to: transfer the mapping information to a host through a host performance booster (hpb) operation based on a mode, which is selected by the host from a host control mode and a device control mode, and selectively request the host to change the mode between the host control mode and the device control mode based on a ratio of a read request with a physical address to all read requests, which are transferred from the host.
20240241657. STORAGE DEVICE AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Sung Jin PARK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a storage device according to the present disclosure includes a memory device including a plurality of memory blocks, and a memory controller configured to, when a boot data request is received from an external device, control the memory device to read a plurality of boot data items from memory blocks included in a super block based on boot address information indicating the super block in which the plurality of boot data items are stored, and provide the plurality of boot data items to the external device.
Inventor(s): Dayoung LEE of Incheon (KR) for sk hynix inc., Minseok SONG of Seoul (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0647
Abstract: a data storage system includes an interface circuit configured to receive a read request for a chunk of data; a disk array including a plurality of main disks and a plurality of sub disks; an input/output control circuit configured to read a chunk from the main disks according to the read request; a data mapping circuit configured to store mapping relations between logical addresses and physical addresses of chunks; and a data relocation control circuit configured to control relocation of chunks stored in the disk array. the data relocation control circuit is configured to control movement of a first chunk stored in a main disk in an overloaded state to a main disk in an underloaded state, and to control movement of a second chunk stored in a sub disk to a main disk which can accommodate a required bandwidth of the second chunk.
Inventor(s): Jung Woo KIM of Icheon (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: when a program operation to a second memory of user data in a first memory is to be performed and the size of user data is smaller than a unit program size of the second memory, final data having a size equal to the unit program size may be produced by concatenating the user data and meta data, and the final data may then programmed into the second memory. the second memory may be non-volatile memory, and the meta data may be meta data for the second memory. in some cases, dummy data may also be concatenated with the user data and meta data to produce the final data. accordingly, it is possible to perform the program operation according to the unit program size and improve the program operation efficiency by reducing the number of program operations performed to store meta data.
Inventor(s): Geon Woo KIM of Gyeonggi-do (KR) for sk hynix inc., Dae Hoon JANG of Gyeonggi-do (KR) for sk hynix inc., Jhu Yeong JHIN of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0659
Abstract: a memory controller that includes a buffer memory configured to store user data and a write command corresponding to a write request received from a host, a processor configured to control a memory device to perform a write operation, and a host interface configured to determine an active range based on mapping information of the memory device, determine the throttle trigger value based on the active range, determine a base latency based on a write ratio of the write command to commands received from the host, and determine a delay time of a write completion response based on the throttle trigger value and the base latency, delay the write completion response according to the delay time, and transmit the delayed write completion response to the host.
Inventor(s): Andrej GAVRILIN of Minsk (BY) for sk hynix inc., Alexander ZAPOTYLOK of Minsk (BY) for sk hynix inc.
IPC Code(s): G06F7/08, G06F9/54, G06F15/80
CPC Code(s): G06F7/08
Abstract: a system having plural slave processors, with each slave processor configured to process at least one input data entry, and having a master processor configured to: a) receive input data entries output from the plural slave processors, b) store the input data entries in a list from a head to a tail of the list based on a time sequence, c) sort the input data entries by comparing a current input data entry with a first input data entry immediately preceding the current input data in a direction of the head of the list, and repeatedly insert the current input data into a first location immediately preceding the first input data entry or a second location immediately following the first input data entry in order to form a time-sequenced list of the data entries.
Inventor(s): Eu-Joon BYUN of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F12/1009
CPC Code(s): G06F12/1009
Abstract: a memory system may include: a nonvolatile memory device; and a controller suitable for generating first map information which maps physical addresses of the nonvolatile memory device to logical addresses received from a host, selecting some segments of the first map information as second map information, and outputting the second map information to the host, the controller may determine whether the second map information is updated, and may determine updated map segments as third map information, and the controller may output information to the host indicating the third map information corresponding to a command received from the host.
Inventor(s): LAN FENG WANG of Zhubei City Hsinchu County (TW) for sk hynix inc.
IPC Code(s): G06F13/36
CPC Code(s): G06F13/36
Abstract: a controller capable of preparing capability information for an interconnection protocol and an electronic device are provided. the controller is for a first device linkable to a second device according to the interconnection protocol. the controller includes a hardware protocol engine and a processing unit. the hardware protocol engine is for implementing a link layer of the interconnection protocol, and capable of performing capability extraction and frame formatting to output capability frame information to a data buffer region and capable of sending, according to content of the data buffer region, a capability frame to the second device during link startup sequence (lss) capability exchange for the interconnection protocol. the processing unit is configured to be capable of modifying, during the lss capability exchange, the content of the data buffer region after the capability frame information is output to the data buffer region and before the capability frame is sent to the second device.
Inventor(s): Joon Seop SIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F13/42
CPC Code(s): G06F13/42
Abstract: an interface device may communicate between a first device and a second device. the interface device may comprise a first element configured to receive a first packet from the first device based on a first protocol and transmit the first packet to the second device, wherein the first packet includes a command and a command address representing a storage position of the command, and a second element configured to receive a second packet from the first device based on a second protocol different from the first protocol and transmit the second packet to the second device, wherein the second packet includes the command address.
20240242321. IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD_simplified_abstract_(sk hynix inc.)
Inventor(s): Jun Hyeok CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Dong Ik KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Cheol Jon JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06T7/00, G06T5/00, G06T7/62, G06T7/90, G06V10/56
CPC Code(s): G06T7/0002
Abstract: provided herein may be an image processing device and an image processing method. the image processing device may include a determination area manager configured to generate a determination area corresponding to a candidate defective pixel based on externally received pixel values and configured to determine whether the determination area is saturated based on pixel values of white pixels included in the determination area, and a defective pixel manager configured to calculate a reference value based on first pixel values of reference pixels that are set based on whether the white pixels are saturated and to determine whether a candidate defective pixel has a defect, based on both the reference value and second pixel values of determination pixels having a color identical to that of the candidate defective pixel, among pixels included in the determination area.
20240242364. IMAGE SIGNAL PROCESSOR_simplified_abstract_(sk hynix inc.)
Inventor(s): Ji Hee HAN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06T7/50, G06T7/80, G06V10/74
CPC Code(s): G06T7/50
Abstract: an image signal processor includes a calibration interpolation unit configured to generate interpolation calibration information for a target pixel using calibration information of at least one grid pixel adjacent to the target pixel. the image signal processor also includes a depth data correction unit configured to generate corrected depth data by correcting target depth data of the target pixel based on the interpolation calibration information.
20240242386. IMAGE PROCESSING DEVICE AND IMAGE BLURRING METHOD_simplified_abstract_(sk hynix inc.)
Inventor(s): Tae Hyun KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jin Su KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jong Hyun BAE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06T7/00, G06T5/00, G06T5/50
CPC Code(s): G06T7/97
Abstract: an image processing device for performing an image blurring method includes an image preprocessor configured to determine an in-focus area and an out-of-focus area for sub-images of an externally received image, the sub-images generated based on pixel values of the externally received image. the image processor is also configured to calculate disparity values between the sub-images in the out-of-focus area. the image processing device further includes an image combiner configured to perform a blur operation on the out-of-focus area depending on a strength of the blur operation determined based on the disparity values and to sum sub-images on which the blur operation is performed.
Inventor(s): Dong Sop LEE of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G11C5/14
CPC Code(s): G11C5/147
Abstract: data storage systems and semiconductor devices are disclosed. in an embodiment, a storage system includes a circuit board, a semiconductor device coupled to the circuit board and including at least one memory and a controller, wherein the controller is in communication with the at least one memory and configured to control the at least one memory, and a voltage level regulator coupled to the circuit board and including at least one switching element and located outside the at least one memory and the controller in the semiconductor device, the voltage level regulator configured to output, to at least one of the at least one memory or the controller, a driving voltage obtained by adjusting a level of at least one external voltage received from a device outside the semiconductor device.
Inventor(s): Gi Moon HONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Dae Han KWON of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/12, G11C7/10, G11C7/22, G11C29/14, G11C29/18
CPC Code(s): G11C29/12015
Abstract: a test circuit may include: a plurality of replication receivers configured to generate a plurality of oscillation signal pairs in response to a plurality of oscillation enable signals; and an oscillation control circuit configured to generate the plurality of oscillation enable signals in response to a test enable signal, and to generate a detection signal in response to any one of the plurality of oscillation signal pairs.
Inventor(s): Byung Ho LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/00, H01L25/065
CPC Code(s): H01L24/05
Abstract: a semiconductor device includes: a first semiconductor structure including a stacked structure of a first dielectric layer and a first bonding dielectric layer; a second semiconductor structure including a stacked structure of a second dielectric layer and a second bonding dielectric layer; and a bonding pad penetrating the stacked structure of the first dielectric layer and the first bonding dielectric layer, and the stacked structure of the second dielectric layer and the second bonding dielectric layer, wherein the first bonding dielectric layer and the second bonding dielectric layer contact each other, and a first width of a first portion of the bonding pad penetrating the first dielectric layer is greater than each of a second width of a second portion of the bonding pad penetrating the first bonding dielectric layer, and a third width of a third portion of the bonding pad penetrating the second bonding dielectric layer.
Inventor(s): Jeong Mook CHOI of Icheon-si (KR) for sk hynix inc., Kuem Ju LEE of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H01L27/146, H01L23/00
CPC Code(s): H01L27/14634
Abstract: disclosed is a method of manufacturing a semiconductor device, including: forming a first metal layer; forming a conductive layer on the first metal layer; forming a capping layer on the conductive layer; etching the first metal layer, the conductive layer, and the capping layer; depositing a bonding oxide layer; etching the bonding oxide layer and the capping layer; forming a first bonding metal layer in an etched space; and forming a second metal layer on the first bonding metal layer.
Inventor(s): Ji Hyo KANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H03K19/173, H03K19/0185, H03K19/096
CPC Code(s): H03K19/1737
Abstract: a clock multiplexing circuit includes: a mode control unit configured to generate first enable signals and second enable signals in response to mode control signals; a first multiplexing unit configured to convert first input signals having a current mode logic (cml) level into complementary metal-oxide semiconductor (cmos) level-signals in response to activation of the first enable signals, and to output the cmos level-signals; and a second multiplexing unit configured to buffer and output second input signals having the cmos level in response to the first enable signals and the second enable signals.
Inventor(s): Jae Hyun HAN of Icheon-si (KR) for sk hynix inc., Dong Ik SUH of Icheon-si (KR) for sk hynix inc., Jae Gil LEE of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: a semiconductor device includes a substrate, a bit line conductive layer extending in a lateral direction substantially parallel to a surface of the substrate, a first insulation line structure extending in a second direction that is perpendicular to the first lateral direction and that is substantially parallel to the surface of the substrate, first and second channel structures that are disposed to respectively contact first and second sides of the first insulation line structure and that partially overlap with the bit line conductive layer, first and second gate dielectric layers respectively disposed over the substrate and on side surfaces of the first and second channel structures, and first and second gate line conductive layers extending in the second lateral direction over the substrate and covering at least a portion of each of the first and second gate dielectric layers, respectively.
Inventor(s): Nam Jae LEE of Cheongju-si Chungcheongbuk-do (KR) for sk hynix inc.
IPC Code(s): H10B43/23, H10B43/27, H10B43/35
CPC Code(s): H10B43/23
Abstract: a semiconductor device and a method of manufacturing the semiconductor device are provided. the semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other; and a source contact structure extending into the stack structure in a vertical direction to be coupled to the source structure, wherein the source contact structure includes polysilicon.
Inventor(s): Dae Sung EOM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, G11C5/06, H10B43/10, H10B43/35
CPC Code(s): H10B43/27
Abstract: provided herein is a memory device and a method of manufacturing the memory device. the memory device includes a first conductive layer extending in a first direction, a second conductive layer extending from the first conductive layer in a second direction intersecting the first direction, a plurality of first channel structures penetrating the first conductive layer and disposed to be spaced apart from each other in the first direction, and a plurality of second channel structures penetrating the second conductive layer, wherein the first conductive layer may form an interface with the second conductive layer, and the interface may be disposed between the plurality of first channel structures and the plurality of second channel structures.
- SK hynix Inc.
- G01S17/32
- G01S7/4911
- G01S7/4915
- CPC G01S17/32
- Sk hynix inc.
- G06F3/06
- CPC G06F3/0634
- CPC G06F3/064
- CPC G06F3/0647
- CPC G06F3/0659
- G06F12/02
- G06F7/08
- G06F9/54
- G06F15/80
- CPC G06F7/08
- G06F12/1009
- CPC G06F12/1009
- G06F13/36
- CPC G06F13/36
- G06F13/42
- CPC G06F13/42
- G06T7/00
- G06T5/00
- G06T7/62
- G06T7/90
- G06V10/56
- CPC G06T7/0002
- G06T7/50
- G06T7/80
- G06V10/74
- CPC G06T7/50
- G06T5/50
- CPC G06T7/97
- G11C5/14
- CPC G11C5/147
- G11C29/12
- G11C7/10
- G11C7/22
- G11C29/14
- G11C29/18
- CPC G11C29/12015
- H01L23/00
- H01L25/065
- CPC H01L24/05
- H01L27/146
- CPC H01L27/14634
- H03K19/173
- H03K19/0185
- H03K19/096
- CPC H03K19/1737
- H10B12/00
- CPC H10B12/315
- H10B43/23
- H10B43/27
- H10B43/35
- CPC H10B43/23
- G11C5/06
- H10B43/10
- CPC H10B43/27
