SK hynix Inc. patent applications on December 19th, 2024
Patent Applications by SK hynix Inc. on December 19th, 2024
SK hynix Inc.: 30 patent applications
SK hynix Inc. has applied for patents in the areas of H10B43/27 (6), G11C16/10 (5), G11C16/04 (4), G11C16/26 (3), H10B43/10 (3) H10B43/27 (2), G11C16/10 (2), G06F3/0625 (2), G11C5/063 (2), G11C16/3459 (2)
With keywords such as: memory, device, data, voltage, semiconductor, configured, program, signal, lines, and control in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Seung Han OAK of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G01R31/28
CPC Code(s): G01R31/2839
Abstract: an electronic device includes a test control circuit configured to generate test codes, configured to generate reference voltages voltage levels of which are adjusted responsive to the test codes, and configured to generate a test current the amount of which is adjusted responsive to the reference voltages and an internal voltage detection circuit configured to generate a detection signal for controlling the driving of an internal voltage by detecting the internal voltage responsive to the test current.
20240419227. STORAGE DEVICE AND ELECTRONIC DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Seung Yeob BAEK of Icheon-si (KR) for sk hynix inc., Nam Hyeon Choi of Icheon-si (KR) for sk hynix inc., Jun Heum Bae of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F1/20, G06F1/3234
CPC Code(s): G06F1/206
Abstract: in an embodiment of the disclosed technology, a heat generation control equation used when changing a power mode for heat generation control of a component included in an electronic device such as a storage device is used by being set differently for each power mode. therefore, heat generation control that accurately reflects the relationship between a change in temperature of the component in each power mode and a temperature value obtained through a temperature sensor may be performed. accordingly, performance degradation due to unnecessary heat generation control may be prevented by efficient heat generation control, and operational performance of the storage device may be improved.
20240419341. STORAGE DEVICE AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Woong Sik SHIN of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06, G06F12/02, G06F12/1009
CPC Code(s): G06F3/0625
Abstract: provided herein may be a storage device and a method of operating the same. the storage device may include a memory device including a plurality of pages in which data is stored, and a memory controller configured to provide, when a read request is externally received, address information including a physical address and a dummy address to the memory device. the memory device may perform a successive read operation of sequentially reading data from pages starting from a selected page corresponding to the physical address, among the plurality of pages, according to the dummy address.
20240419342. MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Dong Kyu LEE of Gyeonggi-do (KR) for sk hynix inc., Seung Geol BAEK of Gyeonggi-do (KR) for sk hynix inc., Jae Hyun YOO of Gyeonggi-do (KR) for sk hynix inc., Seon Ju LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: a memory system may include a memory device including a plurality of memory areas each configured by a plurality of memory blocks; and a memory controller configured to generate zones each including at least one memory block selected from at least one of the memory areas included in the memory device, manage configuration information for each generated zone, sequentially store data from a first storage location of an open zone among the generated zones during a write operation on the open zone according to an external request, and determine a number of active target memory areas associated with the open zone on a basis of configuration information of the open zone.
Inventor(s): Jin Woo KIM of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a storage device may write data to a memory as requested by an external device. subsequently, the storage device may update an attribute of the data based on an increment of an average program-erase cycle of the memory and whether the data has been overwritten. the attribute of the data may be one of a plurality of candidate attributes and the plurality of candidate attributes may include hot, cold, and warm.
Inventor(s): Jae Young LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Won Sun PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F13/20
CPC Code(s): G06F13/20
Abstract: a semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. the first semiconductor apparatus transmits an address signal during an address cycle after transmitting a command signal during a command cycle. the first semiconductor apparatus transmits a selection signal during a logical unit number selection cycle before the command cycle. the second semiconductor apparatus performs a data input and output operation based on the selection signal, the command signal, and the address signal.
Inventor(s): Hyun Jun KIM of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06N20/00, G06F30/398
CPC Code(s): G06N20/00
Abstract: according to an embodiment of the disclosure, an ir-drop prediction system includes a data frame generator configured to generate a raw data frame including ir-drop data for each of a plurality of instances in a designed circuit, a training performer configured to select input instances among the plurality of instances included in the raw data frame and perform training for an ir-drop prediction based on the ir-drop data for the input instances, and an ir-drop predictor configured to predict an ir-drop based on an ir-drop prediction model obtained according to a result of the training. the ir-drop data includes an ir-drop value of a corresponding instance and a plurality of ir-drop factors related to the ir-drop value, and the input instances have the ir-drop values greater than or equal to a preset value.
20240420289. IMAGE SIGNAL PROCESSOR AND NOISE REMOVAL METHOD_simplified_abstract_(sk hynix inc.)
Inventor(s): Chang Hun CHO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Ja Min KOO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Seung Hyun KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Tae Hyun KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jae Hwan JEON of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Woo Young JEONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chang Hee PYEOUN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06T5/70, G06T7/20, G06T7/50
CPC Code(s): G06T5/70
Abstract: an image signal processor may include a data receiver configured to receive image data including depth values corresponding to pixels included in an image obtained from a distance measurement sensor. the image signal processor may also include a motion detector configured to detect motion in the image using either a first motion detection method which uses pixels or a second motion detection method which uses preset kernels, based on amplitude of the light source and generate a detection result indicating whether the motion is included in the target image. a noise remover removes noise from the target image using either a first noise removal method which uses previous image data corresponding to previous images or a second noise removal method which uses the image data corresponding to the target image based on the detection result.
20240420738. MEMORY DEVICE HAVING SUPPORT STRUCTURE_simplified_abstract_(sk hynix inc.)
Inventor(s): Jae Ho KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C5/02, H10B43/10, H10B43/27, H10B43/40
CPC Code(s): G11C5/025
Abstract: a memory device includes: a stack structure; first support structures penetrating the stack structure, the first support structures being spaced apart from each other in a first direction; a first protrusion pattern penetrating the stack structure, the first protrusion pattern being spaced apart from one of the first support structures in a second direction; a first outer support structure penetrating the stack structure, the first outer support structure extending along the first direction from the first protrusion pattern; and a central support structure penetrating the stack structure, the central support structure extending in the second direction in a region between the first support structures, the central support structure being in contact with the first outer support structure.
Inventor(s): Hyo Sub YEOM of Icheon-si (KR) for sk hynix inc., Kyoung Sik HAN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C5/06, H10B41/27, H10B43/27
CPC Code(s): G11C5/063
Abstract: a semiconductor memory device may include first gate structures each including first real gate lines and first insulating layers that are alternately stacked. the device may also include first dummy gate lines located on the first gate structures, a separation insulating structure configured to extend between the first dummy gate lines and between the first gate structures, and a second gate structure located on the first gate structures and the separation insulating structure and comprising a second dummy gate line having a greater width than each of the first dummy gate lines.
20240420740. MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Won Geun CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jeong Hwan KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C5/06, H10B43/10, H10B43/27
CPC Code(s): G11C5/063
Abstract: a memory device, and a method of manufacturing the same, includes a first select line including a first cell area, a second select line including a second cell area disposed in a first direction from the first cell area, a first separation pattern extending in a second direction intersecting the first direction between the first cell area and the second cell area, second separation patterns extending from both ends of the first separation pattern in the first direction and a third direction opposite the first direction, respectively, and a third separation pattern extending from at least one of the second separation patterns in the second direction, and disposed in a direction opposite the first separation pattern with respect to the at least one second separation pattern.
Inventor(s): Jae Young LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Won Sun Park of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/10
CPC Code(s): G11C7/1048
Abstract: a semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. the first semiconductor apparatus transmits an address signal during an address cycle after transmitting a command signal during a command cycle. the first semiconductor apparatus transmits a selection signal during a logical unit number selection cycle before the command cycle. the second semiconductor apparatus performs a data input and output operation based on the selection signal, the command signal, and the address signal.
Inventor(s): Woongrae KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Seol Min YI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Kyoung Chul JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/406, G11C29/12, G11C29/46
CPC Code(s): G11C11/40615
Abstract: a semiconductor system includes a controller outputting a clock, a chip selection signal, a command address, and data, and a semiconductor device performing an auto-refresh operation when the chip selection signal and command address input in synchronization with the clock have a combination for performing the auto-refresh operation, correcting an error of internal data stored therein by performing a read-modify-write operation instead of the auto-refresh operation when the auto-refresh operation is performed a first set number of times and storing the corrected internal data, performing a self-refresh operation when the chip selection signal and command address input in synchronization with the clock have a combination for performing the self-refresh operation, and correcting an error of the internal data stored therein by performing a read-modify-write operation instead of the self-refresh operation when the self-refresh operation is performed a second set number of times and to store the corrected internal data.
Inventor(s): Hyun Seung KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/4096, G11C11/4076, G11C11/4093
CPC Code(s): G11C11/4096
Abstract: a data input and output circuit includes a data input circuit configured to precharge first and second input and output lines after the end of a power-up operation and configured to generate first and second input data by driving the first and second input and output lines from each of which transfer data having a set logic level, among first and second transfer data, are output after the start of a write operation. the data input and output circuit also includes a data output circuit configured to generate first and second internal data based on logic levels of the first and second input data.
Inventor(s): Jung Shik JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., In Su PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Woo Pyo JEONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Dal CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jae Woong KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jeong Hwan KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/04, G11C16/08, G11C16/10, G11C16/24, G11C16/26
CPC Code(s): G11C16/0433
Abstract: the present discloses provides a memory device and a method of operating the memory device. the memory device includes first main plugs formed in a vertical direction over a substrate and arranged in a first direction, second main plugs, third main plugs arranged between the first and second main plugs, the third main plugs adjacent to the first and second main plugs, and bit lines above the first to third main plugs, wherein each of the first to third main plugs includes first and second sub-plugs facing each other, wherein portions of the first and second sub-plugs included in each of the first and third main plugs are coupled to different select lines, and wherein portions of the first and second sub-plugs included in each of the second and third main plugs are coupled to different select lines.
Inventor(s): Won Jae CHOI of Icheon-si Gyeonggi-Do (KR) for sk hynix inc., Won Jun KANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/08
CPC Code(s): G11C16/10
Abstract: a semiconductor device includes a memory cell connected to a word line and a bit line. the semiconductor device also includes a line driving circuit configured to apply a program voltage to the word line. the semiconductor device further includes a page buffer comprising a plurality of latches comprising at least one dynamic latch and at least one static latch and configured to control a voltage level of the bit line after the start of a program operation. the semiconductor device additionally includes a control circuit configured to control the page buffer to program, into the memory cell, data that have been stored in the static latch or store the data in the dynamic latch based on a temperature of the semiconductor device, when receiving a pause command during the program operation.
Inventor(s): Jae Yeop JUNG of Gyeonggi-do (KR) for sk hynix inc., Sung Hyun HWANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/34
CPC Code(s): G11C16/10
Abstract: a memory device comprising: a memory cell array including memory cells coupled between a word line and a plurality of bit lines, and a control unit suitable for performing a program operation of repeating a program loop including a voltage application operation and a verification operation on the memory cells according to an incremental step pulse program (ispp) method until the program operation is performed successfully, wherein the control unit repeatedly performs the program loop by setting a voltage level of an initial program pulse to one of first and second levels according to whether the program operation is an overwrite operation or not, wherein the initial program pulse is to be applied to the word line in the voltage application operation included in an initial program loop of the repeated program loops, and wherein the second level is lower than the first level by a first set level.
Inventor(s): Byoung Young KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/26, G11C16/04, G11C16/10
CPC Code(s): G11C16/26
Abstract: provided herein is a memory device for inputting and outputting data and a memory system including the memory device and a memory controller. the memory device includes memory cells, a plurality of latches configured to sense a plurality of pieces of logical page data stored in the memory cells, and an operation controller configured to output a first latch select signal for selecting first latches, by which first logical page data among the plurality of pieces of logical page data is sensed, from among the plurality of latches in response to a first page data output command. the first latches output the first logical page data in response to the first latch select signal.
20240420777. MEMORY DEVICE AND METHOD OF OPERATING MEMORY DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Byoung Young KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/26, G11C16/04, G11C16/08
CPC Code(s): G11C16/26
Abstract: according to an embodiment of the present disclosure, a memory device includes a memory cell array including a plurality of memory cells respectively connected to a plurality of word lines, a peripheral circuit including a voltage generation circuit and page buffers connected to the memory cells and latching data sensed from the memory cells, and a control logic configured to sense data stored in the memory cells in response to a cache read command received from an external device and configured to control the peripheral circuit to output data latched in the page buffers to the external device, and the control logic controls the peripheral circuit to generate an operation voltage to be applied to the word lines based on a comparison result of a first address corresponding to a first cache read command received from the external device and a second address corresponding to a second cache read command.
Inventor(s): Hyung Jin CHOI of Gyeonggi-do (KR) for sk hynix inc., In Gon YANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C7/04, G11C16/10
CPC Code(s): G11C16/3459
Abstract: a memory device comprising: a memory cell array including a plurality of memory cell strings coupled between a plurality of bit lines and a common source line, and a plurality of word lines coupled to the memory cell strings, and a control circuit configured to: repeat a program loop including a program pulse application operation and a verification operation until a program operation is successfully performed on memory cells that are coupled to a selected word line, a selected cell string, and the plurality of bit lines, additionally perform a channel precharge operation together with the program pulse application operation and the verification operation starting from a selected program loop, and vary a level of a precharge voltage applied to the common source line in the channel precharge operation according to an operation temperature.
Inventor(s): In Gon YANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jae Hyeon SHIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/24
CPC Code(s): G11C16/3459
Abstract: a page buffer of a semiconductor memory device includes a bit line connection transistor, an internal operation circuit, and a plurality of latch circuits. during a program operation of selected memory cells, a power voltage is applied to the bit line connection transistor to set a voltage of a bit line connected to memory cells having a threshold voltage greater than a main verify voltage as a program inhibit voltage. in addition, a second program allowable voltage less than the program inhibit voltage is applied to the bit line connection transistor. in addition, a first program allowable voltage less than the second program allowable voltage is applied to the gate of the bit line connection transistor.
Inventor(s): Se-Hun KANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L21/02
CPC Code(s): H01L21/02356
Abstract: a capacitor of a semiconductor device may include a first electrode, a second electrode, and a dielectric layer stack positioned between the first electrode and the second electrode and including at least one embedded doping level and at least one interface doping level, wherein the dielectric layer stack may include a plurality of hafnium oxide layers, a plurality of seed layers, and a plurality of direct contact interfaces that are in direct contact with the hafnium oxide layers and the seed layers, at least one the embedded doping level is positioned in at least one the hafnium oxide layers, and at least one the interface doping level is positioned at least one the direct contact interfaces.
Inventor(s): Myung Ok KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L21/768, H01L23/528, H01L23/532
CPC Code(s): H01L21/76885
Abstract: there is disclosed a method of manufacturing a semiconductor device including a separation pattern. an intermediate structure layer including first conductive pillars and second conductive pillars is formed over a semiconductor substrate. a separation layer is formed. some portions of the separation layer is selectively removed to form a separation pattern, and third conductive patterns filling holes of the separation pattern and fourth conductive patterns filling trenches of the separation pattern are formed.
Inventor(s): Nam Jae LEE of Cheongju-si Chungcheongbuk-do (KR) for sk hynix inc.
IPC Code(s): H01L23/522, H01L23/528, H10B41/27, H10B41/35, H10B41/41, H10B43/27, H10B43/35, H10B43/40
CPC Code(s): H01L23/5226
Abstract: a semiconductor memory device, and a method of manufacturing a semiconductor memory device, includes a stacked structure including a plurality of conductive layers for local lines stacked on a semiconductor substrate defined by a cell region and a slimming region to be spaced apart from each other, wherein the plurality of conductive layers for local lines are stacked in a step structure in the slimming region. the semiconductor memory device also includes a plurality of contact plugs formed to penetrate the stack structure in the slimming region, the plurality of contact plugs corresponding to each of the conductive layers for local lines. each of the plurality of contact plugs includes a protrusion part protruding horizontally, and the protrusion part is connected to a corresponding conductive layer for local lines among the plurality of conductive layers for local lines.
Inventor(s): Junghan LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H03K5/24, H02M3/07, H03K5/156
CPC Code(s): H03K5/24
Abstract: a clock generator includes a voltage supply circuit configured to generate a control voltage based on a first current and a control signal. the clock generator also includes a first clock output circuit configured to output the control signal by comparing a first reference voltage with the control voltage, and to output a first clock signal by comparing a third reference voltage having a different voltage level from the first reference voltage with the control voltage. clock generator further includes a second clock output circuit configured to compare a second reference voltage with the control voltage, to compare a fourth reference voltage having a different voltage level from the second reference voltage with the control voltage, and to generate a second clock signal having a phase different from that of the first clock signal.
Inventor(s): Fan ZHANG of Fremont CA (US) for sk hynix inc., Haobo Wang of Fremont CA (US) for sk hynix inc., Meysam ASADI of San Jose CA (US) for sk hynix inc.
IPC Code(s): H03M13/11, H03M13/01, H03M13/09
CPC Code(s): H03M13/1128
Abstract: decoding method and memory system which group bits in irregular ldpc codes having similar degrees of convergence into respective degree groups, classify the degree groups according to a metric indicative of a number of decoding iterations for convergence, divide a time period for convergence of the decoding iterations into different zones for the processing of selected degree groups within each zone, and skip decoding of the bits in a non-converging zone where the bits are not converging.
Inventor(s): Jun Sik KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: a unit cell may include an active layer, a separation region and a gate. the active layer may include a first junction region, a second junction region and a channel between the first junction region and the second junction region. the separation region may be formed in the active layer to separate the first junction region and the channel into at least two regions. the gate may be arranged in the separation region.
20240422972. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Won Geun CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., In Su PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Dal CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/23, H10B43/10
CPC Code(s): H10B43/23
Abstract: the present disclosure relates to a semiconductor memory device. the semiconductor memory device includes a gate stack, a hole penetrating the gate stack, and a channel structure. the hole has an undercut region defined on a sidewall thereof. the channel structure covers a portion of the undercut region and opens another portion of the undercut region.
20240422974. MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Nam Jae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27
CPC Code(s): H10B43/27
Abstract: a memory device, and a method of manufacturing the same, includes cell plugs in addition to an insulating pattern provided on the cell plugs, the insulating pattern including openings corresponding to the cell plugs, respectively. the memory device also includes bit lines provided on the insulating pattern and bit line contacts provided in the openings to couple the cell plugs and the bit lines, respectively. the memory device further includes first air gaps provided between the bit lines. the memory device additionally includes second air gaps extending from the first air gaps and enclosed by the bit line contacts and the insulating pattern.
Inventor(s): Seo Hyun KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., In Ku KANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/27, H10B63/00
CPC Code(s): H10B43/27
Abstract: a method of manufacturing a semiconductor device includes forming a stacked structure with first material layers and second material layers that are alternately stacked with each other, forming a first opening that passes through the stacked structure, forming second openings between the first material layers, forming first sacrificial layers in the second openings, forming first isolation layers that protrude into the first opening by oxidizing the first sacrificial layers, forming mold patterns on the first material layers between the protruding portions of the first isolation layers, forming third openings by etching portions of the first isolation layers that are exposed between the mold patterns, forming second sacrificial layers in the third openings, and forming second isolation layers that protrude farther toward the center of the first opening than the mold patterns by oxidizing the second sacrificial layers.
- SK hynix Inc.
- G01R31/28
- CPC G01R31/2839
- Sk hynix inc.
- G06F1/20
- G06F1/3234
- CPC G06F1/206
- G06F3/06
- G06F12/02
- G06F12/1009
- CPC G06F3/0625
- CPC G06F3/0659
- G06F13/20
- CPC G06F13/20
- G06N20/00
- G06F30/398
- CPC G06N20/00
- G06T5/70
- G06T7/20
- G06T7/50
- CPC G06T5/70
- G11C5/02
- H10B43/10
- H10B43/27
- H10B43/40
- CPC G11C5/025
- G11C5/06
- H10B41/27
- CPC G11C5/063
- G11C7/10
- CPC G11C7/1048
- G11C11/406
- G11C29/12
- G11C29/46
- CPC G11C11/40615
- G11C11/4096
- G11C11/4076
- G11C11/4093
- CPC G11C11/4096
- G11C16/04
- G11C16/08
- G11C16/10
- G11C16/24
- G11C16/26
- CPC G11C16/0433
- CPC G11C16/10
- G11C16/34
- CPC G11C16/26
- G11C7/04
- CPC G11C16/3459
- H01L21/02
- CPC H01L21/02356
- H01L21/768
- H01L23/528
- H01L23/532
- CPC H01L21/76885
- H01L23/522
- H10B41/35
- H10B41/41
- H10B43/35
- CPC H01L23/5226
- H03K5/24
- H02M3/07
- H03K5/156
- CPC H03K5/24
- H03M13/11
- H03M13/01
- H03M13/09
- CPC H03M13/1128
- H10B12/00
- CPC H10B12/315
- H10B43/23
- CPC H10B43/23
- CPC H10B43/27
- H10B63/00
