SK hynix Inc. patent applications on August 22nd, 2024
Patent Applications by SK hynix Inc. on August 22nd, 2024
SK hynix Inc.: 22 patent applications
SK hynix Inc. has applied for patents in the areas of G06F3/06 (3), G06F11/10 (3), G11C16/10 (2), H01L27/146 (2), G11C16/04 (2) H10B43/27 (2), G11C16/349 (1), H10B12/30 (1), H04N25/7795 (1), H03M13/3707 (1)
With keywords such as: memory, device, data, including, signal, semiconductor, chip, layer, configured, and read in patent application abstracts.
Patent Applications by SK hynix Inc.
20240281166. STORAGE DEVICE AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Jae Woong JEONG of Icheon (KR) for sk hynix inc., In Bo Shim of Icheon (KR) for sk hynix inc., Na Yeong Kim of Icheon (KR) for sk hynix inc., Dal Gon Kim of Icheon (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a storage device includes a memory controller and a plurality of memory devices. the plurality of memory devices comprise a first memory device coupled to the memory controller and an nmemory device coupled in series to the first memory device, where n is a natural number greater than 1. the memory controller is configured to transmit, to a first memory device, a signal that includes a target id indicating a selected memory device from among the plurality of memory devices. each memory device includes a plurality of memory dies, an interface configured to distribute the signal based on the target id, and a redriver configured to redrive the signal such that the signal is transferred to another memory device.
Inventor(s): Nam Hyun KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Kang Bong SEO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Kwang Jun CHO of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F7/58
CPC Code(s): G06F7/588
Abstract: a random number generation system for generating random number(s) using an image sensor is disclosed. the image sensor includes a photoelectric conversion element configured to generate charges in response to light, a first tap in which a first charge from among the charges generated by the photoelectric conversion element is accumulated, and a second tap in which a second charge from among the charges generated by the photoelectric conversion element is accumulated.
Inventor(s): Ji Hoon Kim of Seoul (KR) for sk hynix inc., So Hyeon Kim of Seoul (KR) for sk hynix inc.
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5044
Abstract: proposed are an on chip multi-core system and an optimizing method for pr resource selection in which management for allocating a plurality of partial regions (prs) constituting a reconfigurable resource pool to a corresponding core of multiple cores and management for reconfiguring the inside of each pr can be separately performed, fragmentation can be minimized after the allocation of the prs, and the reconfiguration time of an accelerator can be shortened. the on chip multi-core system includes a pr map, a core unit, a pr resource management processor, an inter pr routing controller, a bitstream memory, and an intra pr configuration controller.
Inventor(s): Jae Yong SON of Gyeonggi-do (KR) for sk hynix inc., Dae Sung KIM of Gyeonggi-do (KR) for sk hynix inc., Min Su CHOI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/10
Abstract: provided herein may be a memory controller and a memory system including the same. the memory controller may include an error correction circuit configured to perform error correction decoding on data that is read by read retry operations, a buffer memory configured to store decoding history information including retry fail voltages used for a failure in the read retry operations and syndrome weights respectively corresponding to the retry fail voltages, and a processor configured to, when a number of times that the read retry operations fail reaches a threshold number of times, determine a voltage corresponding to a minimum syndrome weight determined based on a relationship between changes in the syndrome weights relative to magnitudes of the retry fail voltages, to be an optimally estimated read voltage, and provide data that is read using the optimally estimated read voltage to the error correction circuit.
Inventor(s): Yong Wan HWANG of Icheon-si (KR) for sk hynix inc., Tae Woong HA of Icheon-si (KR) for sk hynix inc., Kwang Ho CHOI of Icheon-si (KR) for sk hynix inc., Moon Hyeok CHOI of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F11/10, G11C11/408, G11C11/4091
CPC Code(s): G06F11/1068
Abstract: a memory module includes a plurality of first memory chips and a second memory chip. raw data is stored in the plurality of first memory chips. parity data generated based on the raw data is stored in the second memory chip. each of the first memory chips and the second memory chip is configured to exchange data with a controller based on a burst length unit. the second memory chip stores a first parity data generated from the raw data by a first error correction method, and stores a second parity data generated from the raw data and the first parity data by a second error correction method.
Inventor(s): Ken Sawada of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06T7/80
CPC Code(s): G06T7/80
Abstract: an image processing device may include: a noise information manager for managing noise information of a target image sensor and a reference image sensor. it may also include a physical intrinsic identification key generator, which generates a physical intrinsic identification key of the target image sensor, based on a difference between noise signals output from pixels of the target image sensor that are adjacent to each other. an intrinsic image generator generates intrinsic image data, which includes the physical intrinsic identification key of the target image sensor.
Inventor(s): Yun Suk HONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/12, G11C7/08, G11C29/02, G11C29/50
CPC Code(s): G11C7/12
Abstract: a semiconductor device includes a pull-up source voltage generation circuit configured to drive a pull-up voltage to a normal voltage during a normal period and to drive the pull-source voltage to a test voltage during a test period. the semiconductor device also includes a pull-down source voltage generation circuit configured to drive a pull-down voltage to a ground voltage during the normal period and to drive the pull-down source voltage to a bit line pre-charge voltage during the test period. the semiconductor device further includes an equalization control signal driver configured to receive the pull-up source voltage and the pull-down source voltage to drive an equalization control signal for equalizing voltage levels of an internal bit line pair of a bit line sense amplifier.
Inventor(s): Hyun Seung KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hyeong Soo JEONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/22, G11C7/10
CPC Code(s): G11C7/222
Abstract: a semiconductor device includes first and second memory devices configured to share a first transmission line from which a write clock is received and a second transmission line from which data is received. the memory devices receive the data through first to eighth internal clocks that are generated by dividing a frequency of the write clock, and selectively align and store at least some of the data that is received in synchronization with the first to eighth internal clocks based on timing at which the data is synchronized with the write clock.
Inventor(s): Nam Jae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/413, H10B10/00
CPC Code(s): G11C11/413
Abstract: there are provided a semiconductor memory device and a manufacturing method thereof. the semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.
20240282375. STORAGE DEVICE AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Seung Han RYU of Gyeonggi-do (KR) for sk hynix inc., Sung Geun KANG of Gyeonggi-do (KR) for sk hynix inc., Hyeong Rak KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C14/00, G06F3/06
CPC Code(s): G11C14/0018
Abstract: according to the present technology, a storage device includes a nonvolatile storage area including a plurality of backup memory blocks each including a plurality of memory cells respectively connected to a plurality of word lines, and a controller configured to control the nonvolatile storage area to determine a target memory block in which data is to be stored among the plurality of backup memory blocks, determine a reference word line among the plurality of word lines coupled to the target memory block, and perform a pre-conditioning operation of programming dummy data to memory cells connected to at least one of remaining word lines except for the reference word line among the plurality of word lines coupled to the target memory block.
Inventor(s): Byoung In JOO of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/26, G11C7/02, G11C15/04, G11C16/10
CPC Code(s): G11C16/26
Abstract: a memory device includes a memory block including a plurality of pages; and a control logic configured to control, when a read command for a selected page among the plurality of pages is received, a read operation on the selected page to be performed using a plurality of read voltages, wherein the plurality of read voltages are determined based on a reference value for the selected page and a read count representing a number of times a read operation of reading data stored in the selected page is performed after a program operation of storing data in the selected page.
20240282394. MEMORY DEVICE AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Chang Beom WOO of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10, G11C16/16
CPC Code(s): G11C16/349
Abstract: provided herein may be a memory device and a method of operating the same. the memory device may include a memory block including a plurality of memory strings, a peripheral circuit configured to perform an erase operation and a program operation on the memory block, and a control logic configured to control the peripheral circuit to perform the erase operation and the program operation on the memory block, wherein the control logic is configured to control the peripheral circuit to perform an abnormally injected electron removal operation that removes abnormally injected electrons trapped in a charge storage layer of a plurality of memory cells included in the memory block after the erase operation has been completed.
Inventor(s): Jae Ho KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/522, H01L21/768, H01L29/10
CPC Code(s): H01L23/5226
Abstract: the present technology relates to a semiconductor device and a method of manufacturing the semiconductor device. the semiconductor device includes a stack including a plurality of interlayer insulating layers and a plurality of gate conductive layers alternately stacked, a channel plug formed on a cell region by vertically passing through the stack, a plurality of support structures formed on a contact region by vertically passing through the stack, and a sacrificial layer surrounding a lower end portion sidewall of each of the plurality of support structures.
Inventor(s): Jin Kyoung PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L25/065, H01L23/00
CPC Code(s): H01L25/0657
Abstract: a semiconductor package including: a base layer; a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including a plurality of semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack and chip identification pads for identifying the plurality of semiconductor chips in each of the first and second chip stacks; a first inter-chip wire and a second inter-chip wire connecting power-applied ones of the chip identification pads of the plurality of semiconductor chips of the first and second chip stacks; a first stack wire and second stack wire connecting the chip identification pad of a lowermost semiconductor chip of the first and second chip stacks to the base layer.
20240282768. SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Kyu Jin CHOI of Gyeonggi-do (KR) for sk hynix inc., Seong Min MA of Gyeonggi-do (KR) for sk hynix inc., Kyu Chan SHIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L27/08
CPC Code(s): H01L27/0805
Abstract: a semiconductor device may include a first capacitor and a second capacitor located at a different height from the first capacitor. each of the first and second capacitors includes a lower electrode, an upper electrode and a dielectric layer between the lower electrode and the upper electrode. a selected one of the lower and upper electrodes includes a first portion having a cylindrical shape including a closed lower surface and an opened upper surface and a second portion vertically extended from the first portion of the selected one. a selected another one of the lower and upper electrodes includes a first portion having a bar shape extended into the first portion of the selected one, a second portion vertically extended from the first portion of the selected another one, and a third portion having a disc shape between the first portion and the second portion in the selected another one.
Inventor(s): Yujin PARK of Gyeonggi-do (KR) for sk hynix inc., Sungwook SEO of Gyeonggi-do (KR) for sk hynix inc., Jeongeun SONG of Gyeonggi-do (KR) for sk hynix inc., Minseok SHIN of Gyeonggi-do (KR) for sk hynix inc., Ohjun KWON of Gyeonggi-do (KR) for sk hynix inc., Hansang KIM of Gyeonggi-do (KR) for sk hynix inc., Kangbong SEO of Gyeonggi-do (KR) for sk hynix inc., Jinuk JEON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L27/146, G01C3/08, H04N17/00, H04N23/65, H04N23/959, H04N25/705, H04N25/709, H04N25/76
CPC Code(s): H01L27/14609
Abstract: an image sensing device includes an image sensor suitable for correcting depth information based on a control signal, and for generating image data according to the depth information, and a controller suitable for analyzing an error of the depth information, and for generating the control signal, based on first and second cycle signals provided from the image sensor.
20240282786. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Jae Hyung JANG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14612
Abstract: disclosed is an image sensing device, including: a plurality of pixel arrays, and the pixel arrays include: a first pixel array including a plurality of first unit pixels, and a second pixel array disposed to surround the first pixel array and including a plurality of second unit pixels, and the first unit pixel includes a plurality of photodiodes, and each photodiode of the first unit pixel is connected to a different transfer transistor.
20240283467. DATA STORAGE DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Kyoung Lae CHO of Gyeonggi-do (KR) for sk hynix inc., Soo Jin KIM of Gyeonggi-do (KR) for sk hynix inc., Naveen KUMAR of San Jose CA (US) for sk hynix inc., Aman BHATIA of San Jose CA (US) for sk hynix inc., Yi-Min LIN of San Jose CA (US) for sk hynix inc., Chenrong XIONG of San Jose CA (US) for sk hynix inc., Fan ZHANG of Fremont CA (US) for sk hynix inc., Yu CAI of San Jose CA (US) for sk hynix inc., Abhiram PRABAHKAR of San Jose CA (US) for sk hynix inc.
IPC Code(s): H03M13/37, G06F3/06, G06F11/10, H03M13/11
CPC Code(s): H03M13/3707
Abstract: a data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. the data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
Inventor(s): Daisuke SHIRAISHI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N25/76, H03K5/22, H03K21/02, H04N23/661
CPC Code(s): H04N25/7795
Abstract: disclosed is an electronic device including a counter suitable for counting a clock signal and generating a count signal corresponding to a count value of the clock signal, a target count generator suitable for generating a target count signal based on the count signal and a second adjusting signal, a comparator suitable for comparing the target count signal with a reference count signal and generating a comparison signal which corresponds to a difference value between the count value corresponding to the target count signal and a count value corresponding to the reference count signal, and a count value adjuster suitable for generating the second adjusting signal corresponding to the difference value, based on the comparison signal.
Inventor(s): Seung Hwan KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00, G11C5/06, H01L27/06
CPC Code(s): H10B12/30
Abstract: a semiconductor memory device and method for making the same. the semiconductor device includes a transistor laterally extending in a direction parallel to a substrate and including an active layer over the substrate, the active layer having a first end and a second end; bit line contact nodes formed on an upper surface and a lower surface of the first end of the active layer, respectively; a bit line side-ohmic contact vertically extending and connecting to the first end of the active layer and the bit line contact nodes; a bit line extending in a vertical direction to the substrate and connected to the bit line side-ohmic contact; and a capacitor connected to the second end of the active layer.
Inventor(s): Dong Hun KWAK of Gyeonggi-do (KR) for sk hynix inc., Moon Soo SUNG of Gyeonggi-do (KR) for sk hynix inc., Woo Pyo JEONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, G11C16/04, G11C16/24, G11C16/26, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/35
CPC Code(s): H10B43/27
Abstract: a memory may include a first memory block including a plurality of first memory cells; and a second memory block including a plurality of second memory cells each having a larger size than each of the plurality of first memory cells. normal data may be stored in the first memory block, and critical data requiring reliability may be stored in the second memory block.
Inventor(s): Won Geun CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Rho Gyu KWAK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., In Su PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Dal CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/10, H10B41/27, H10B41/30, H10B43/10, H10B43/30
CPC Code(s): H10B43/27
Abstract: a semiconductor device includes a gate structure including conductive layers and insulating layers that are alternately stacked. the semiconductor device also includes an insulating core located in the gate structure and including a long axis and a short axis. the semiconductor device further includes a first channel pattern and a second channel pattern surrounding the insulating core and located to face each other along the long axis. the semiconductor device additionally includes a barrier pattern surrounding the first channel pattern and the second channel pattern and having different thicknesses along the long axis and the short axis.
- SK hynix Inc.
- G06F3/06
- CPC G06F3/0655
- Sk hynix inc.
- G06F7/58
- CPC G06F7/588
- G06F9/50
- CPC G06F9/5044
- G06F11/10
- CPC G06F11/10
- G11C11/408
- G11C11/4091
- CPC G06F11/1068
- G06T7/80
- CPC G06T7/80
- G11C7/12
- G11C7/08
- G11C29/02
- G11C29/50
- CPC G11C7/12
- G11C7/22
- G11C7/10
- CPC G11C7/222
- G11C11/413
- H10B10/00
- CPC G11C11/413
- G11C14/00
- CPC G11C14/0018
- G11C16/26
- G11C7/02
- G11C15/04
- G11C16/10
- CPC G11C16/26
- G11C16/34
- G11C16/04
- G11C16/16
- CPC G11C16/349
- H01L23/522
- H01L21/768
- H01L29/10
- CPC H01L23/5226
- H01L25/065
- H01L23/00
- CPC H01L25/0657
- H01L27/08
- CPC H01L27/0805
- H01L27/146
- G01C3/08
- H04N17/00
- H04N23/65
- H04N23/959
- H04N25/705
- H04N25/709
- H04N25/76
- CPC H01L27/14609
- CPC H01L27/14612
- H03M13/37
- H03M13/11
- CPC H03M13/3707
- H03K5/22
- H03K21/02
- H04N23/661
- CPC H04N25/7795
- H10B12/00
- G11C5/06
- H01L27/06
- CPC H10B12/30
- H10B43/27
- G11C16/24
- H10B41/10
- H10B41/27
- H10B41/35
- H10B43/10
- H10B43/35
- CPC H10B43/27
- H10B41/30
- H10B43/30
