SEMICONDUCTOR PACKAGE: abstract simplified (18210132)

• This abstract for appeared for patent application number 18210132 Titled 'SEMICONDUCTOR PACKAGE'

Simplified Explanation

This abstract describes a semiconductor package that consists of various components such as a package substrate, bumps, a semiconductor chip, connection patterns, molding, warpage control layer, and insulating layers. The package is designed to control warpage and provide connectivity between different components. The abstract mentions the specific openings in the insulating layers that expose the warpage control layer and connection patterns.

Original Abstract Submitted

A semiconductor package includes a package substrate, first and second bumps on a lower surface of the package substrate, a semiconductor chip on an upper surface of the package substrate, first and second connection patterns on the upper surface of the package substrate, a molding on the upper surface of the package substrate and covering the semiconductor chip, a warpage control layer on the molding, an upper insulating layer on the warpage control layer, a first opening passing through the upper insulating layer and exposing an upper surface of the warpage control layer, a second opening overlapping the first opening in a top view, the second opening passing through the warpage control layer and exposing the first connection pattern, and a third opening passing through the upper insulating layer and exposing the second connection pattern.