Qualcomm incorporated (20240176751). MULTIPLE-CORE MEMORY CONTROLLER simplified abstract
Contents
- 1 MULTIPLE-CORE MEMORY CONTROLLER
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MULTIPLE-CORE MEMORY CONTROLLER - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
MULTIPLE-CORE MEMORY CONTROLLER
Organization Name
Inventor(s)
Pankaj Deshmukh of San Diego CA (US)
Shyamkumar Thoziyoor of San Diego CA (US)
Vishakh Balakuntalam Visweswara of Vancouver (CA)
Jungwon Suh of San Diego CA (US)
Subbarao Palacharla of San Diego CA (US)
MULTIPLE-CORE MEMORY CONTROLLER - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240176751 titled 'MULTIPLE-CORE MEMORY CONTROLLER
Simplified Explanation
The patent application describes memory systems that can operate portions of a memory core at a lower frequency than the memory clock to save power and reduce costs.
- Memory controller with two cores: One core schedules memory operations for one portion of the clock cycle, while the other core schedules operations for another portion.
- The system aims to reduce power consumption and costs by operating parts of the memory core at a lower frequency.
- The technology can be applied to various memory systems to improve efficiency and reduce energy usage.
Potential Applications
This technology could be used in various electronic devices such as smartphones, tablets, and computers to improve energy efficiency and extend battery life.
Problems Solved
This innovation addresses the issue of high power consumption in memory systems, offering a solution to reduce energy usage and lower costs associated with operating memory cores.
Benefits
The benefits of this technology include reduced power consumption, lower costs, improved energy efficiency, and potentially longer battery life for electronic devices.
Potential Commercial Applications
This technology could be applied in the development of energy-efficient memory systems for consumer electronics, data centers, and other computing devices.
Possible Prior Art
One possible prior art could be memory systems that operate at a fixed frequency, without the ability to adjust the frequency of different portions of the memory core independently.
Unanswered Questions
How does this technology compare to other power-saving techniques in memory systems?
This article does not provide a comparison with other power-saving techniques, leaving the reader wondering about the effectiveness of this innovation relative to existing solutions.
Are there any limitations to implementing this technology in different types of memory systems?
The article does not address any potential limitations or challenges that may arise when implementing this technology in various memory systems, leaving room for further exploration and research.
Original Abstract Submitted
this disclosure provides systems, methods, and devices for memory systems that support operating a least portions of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. in a first aspect, a memory controller includes a first core for scheduling a first memory operation for a first portion of a clock cycle of the memory clock and includes a second core for scheduling a second memory operation for a second portion of the clock cycle of the memory clock. other aspects and features are also claimed and described.
