Qualcomm incorporated (20240161808). DDR PHY CRITICAL CLOCK SWITCHING AND GATING ARCHITECTURE simplified abstract
Contents
- 1 DDR PHY CRITICAL CLOCK SWITCHING AND GATING ARCHITECTURE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DDR PHY CRITICAL CLOCK SWITCHING AND GATING ARCHITECTURE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications of this Technology
- 1.6 Problems Solved by this Technology
- 1.7 Benefits of this Technology
- 1.8 Potential Commercial Applications of this Technology
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
DDR PHY CRITICAL CLOCK SWITCHING AND GATING ARCHITECTURE
Organization Name
Inventor(s)
Boris Dimitrov Andreev of San Diego CA (US)
Vikas Mahendiyan of San Diego CA (US)
DDR PHY CRITICAL CLOCK SWITCHING AND GATING ARCHITECTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240161808 titled 'DDR PHY CRITICAL CLOCK SWITCHING AND GATING ARCHITECTURE
Simplified Explanation
The patent application abstract describes a system with two clock sources, an OR gate, and clock gating circuits to control the flow of clock signals.
- The system includes a first clock source generating a clock signal.
- A second clock source generates another clock signal.
- An OR gate combines the two signals and outputs them to a clock path.
- Clock gating circuits control the input of each clock signal to the OR gate.
Potential Applications of this Technology
This technology could be applied in various electronic devices that require precise timing synchronization, such as communication systems, data processing units, and networking equipment.
Problems Solved by this Technology
This technology helps in ensuring accurate timing synchronization between different components of a system, reducing the chances of data loss, errors, or system failures due to timing discrepancies.
Benefits of this Technology
- Improved system reliability and performance - Simplified clock signal management - Enhanced overall system efficiency
Potential Commercial Applications of this Technology
The technology could be utilized in telecommunications infrastructure, computer networking devices, industrial automation systems, and other electronic equipment requiring precise timing control.
Possible Prior Art
One possible prior art could be the use of clock gating circuits and OR gates in digital systems to manage clock signals and ensure proper synchronization.
Unanswered Questions
How does this technology compare to existing clock synchronization methods in terms of accuracy and efficiency?
This article does not provide a direct comparison between this technology and other clock synchronization methods.
What are the potential limitations or drawbacks of implementing this system in real-world applications?
The article does not address any potential limitations or drawbacks that may arise when implementing this system in practical scenarios.
Original Abstract Submitted
in certain aspects, a system includes a first clock source configured to generate a first clock signal, a second clock source configured to generate a second clock signal, a clock path, and an or gate having a first input, a second input, and an output, wherein the output of the or gate is coupled to the clock path. the system also includes a first clock gating circuit coupled between the first clock source and the first input of the or gate, and a second clock gating circuit coupled between the second clock source and the second input of the or gate.
