QUALCOMM Incorporated (20240211141). MEMORY REFRESH RATE BASED THROTTLING SCHEME IMPLEMENTATION simplified abstract
Contents
- 1 MEMORY REFRESH RATE BASED THROTTLING SCHEME IMPLEMENTATION
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MEMORY REFRESH RATE BASED THROTTLING SCHEME IMPLEMENTATION - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Key Features and Innovation
- 1.6 Potential Applications
- 1.7 Problems Solved
- 1.8 Benefits
- 1.9 Commercial Applications
- 1.10 Prior Art
- 1.11 Frequently Updated Research
- 1.12 Questions about Memory Utilization Control
- 1.13 Original Abstract Submitted
MEMORY REFRESH RATE BASED THROTTLING SCHEME IMPLEMENTATION
Organization Name
Inventor(s)
Prathviraj Shetty of Bangalore (IN)
Srikar Karnam Venkat Naga of Bangalore (IN)
Pranav Agrawal of Hyderabad (IN)
Pankaj Kumar Sharma of Bangalore (IN)
Louis Louie of San Diego CA (US)
Shekar Babu Merla of Bangalore (IN)
Odelu Kukatla of Hyderabad (IN)
Ravi Teja Mandavilli of Bangalore (IN)
Sampath Kumar Kulasekara of Bangalore (IN)
Sudhakar Chakali of Bangalore (IN)
Rajkumar Hariharan of Bangalore (IN)
MEMORY REFRESH RATE BASED THROTTLING SCHEME IMPLEMENTATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240211141 titled 'MEMORY REFRESH RATE BASED THROTTLING SCHEME IMPLEMENTATION
Simplified Explanation
The patent application discusses methods for controlling memory utilization to accommodate changes in memory accessibility due to memory refreshes. This includes adjusting the bandwidth of processors based on the refresh rate of the memory.
- Memory utilization is controlled to adapt to memory refreshes.
- Bandwidth of processors is adjusted based on memory refresh rates.
- Quality of service manager may be involved in managing memory refresh rates.
Key Features and Innovation
- Methods for controlling memory utilization in response to memory refreshes.
- Adjusting processor bandwidth based on memory refresh rates.
- Involvement of a quality of service manager in managing memory refresh rates.
Potential Applications
The technology can be applied in various computing systems where memory refresh rates impact memory accessibility and processor performance.
Problems Solved
The technology addresses the challenge of managing memory utilization efficiently in response to memory refreshes to optimize processor performance.
Benefits
- Improved memory utilization management.
- Enhanced processor performance.
- Efficient adaptation to memory refresh rates.
Commercial Applications
- Data centers
- Cloud computing services
- High-performance computing systems
Prior Art
Prior research in memory management systems and quality of service in computing environments may provide insights into similar technologies.
Frequently Updated Research
Research on memory management algorithms, processor scheduling techniques, and quality of service optimization in computing systems may be relevant to this technology.
Questions about Memory Utilization Control
How does adjusting processor bandwidth based on memory refresh rates improve system performance?
By optimizing processor bandwidth according to memory refresh rates, the system can ensure efficient memory utilization and maintain consistent performance levels.
What role does the quality of service manager play in managing memory refresh rates?
The quality of service manager is responsible for monitoring memory refresh rates and making adjustments to processor bandwidth to maintain optimal system performance.
Original Abstract Submitted
various embodiments include methods for controlling memory utilization to accommodate changes in memory accessibility due to memory refreshes include controlling bandwidth of at least one processor based on a refresh rate of a memory. some embodiments may include receiving the refresh rate of the memory at a memory controller, and determining whether the refresh rate of the memory violates a high or low memory refresh rate threshold, sending an instruction configured to reduce or restore the bandwidth of the at least one processor in response to the determination. in some embodiments the methods may be performed by a quality of service manager, which may be part of a memory controller.
- QUALCOMM Incorporated
- Prathviraj Shetty of Bangalore (IN)
- Srikar Karnam Venkat Naga of Bangalore (IN)
- Pranav Agrawal of Hyderabad (IN)
- Pankaj Kumar Sharma of Bangalore (IN)
- Louis Louie of San Diego CA (US)
- Amod Kumar of Darbhanga (IN)
- Shekar Babu Merla of Bangalore (IN)
- Odelu Kukatla of Hyderabad (IN)
- Ravi Teja Mandavilli of Bangalore (IN)
- Anshul Verma of Bhilai (IN)
- Sampath Kumar Kulasekara of Bangalore (IN)
- Sudhakar Chakali of Bangalore (IN)
- Rajkumar Hariharan of Bangalore (IN)
- G06F3/06
- CPC G06F3/0613