Nvidia corporation (20240094793). TECHNIQUES TO MODIFY PROCESSOR PERFORMANCE simplified abstract
Contents
TECHNIQUES TO MODIFY PROCESSOR PERFORMANCE
Organization Name
Inventor(s)
Benjamin D. Faulkner of Los Altos Hills CA (US)
Padmanabhan Kannan of Santa Clara CA (US)
Srinivasan Raghuraman of San Jose CA (US)
Peng Cheng Shen of Sunnyvale CA (US)
Divya Ramakrishnan of San Jose CA (US)
Swanand Santosh Bindoo of San Jose CA (US)
Sreedhar Narayanaswamy of Sunnyvale CA (US)
Amey Y. Marathe of Union City CA (US)
TECHNIQUES TO MODIFY PROCESSOR PERFORMANCE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240094793 titled 'TECHNIQUES TO MODIFY PROCESSOR PERFORMANCE
Simplified Explanation
The patent application abstract describes methods to optimize processor performance by increasing the operation voltage of processors based on error rates.
- Explanation of the patent/innovation:
* Increase operation voltage of processors based on error rates to optimize performance.
- Potential applications of this technology:
* Data centers * High-performance computing * Artificial intelligence
- Problems solved by this technology:
* Improving processor performance * Reducing errors in processing tasks * Enhancing overall system efficiency
- Benefits of this technology:
* Increased processing speed * Enhanced system reliability * Improved overall performance
- Potential commercial applications of this technology:
* Processor manufacturers * Computer hardware companies * Cloud computing providers
- Possible prior art:
* Previous methods of optimizing processor performance based on voltage and error rates
- Unanswered Questions
- How does this technology impact energy consumption?
This article does not address the potential impact of increasing operation voltage on energy consumption.
- Are there any potential drawbacks to increasing operation voltage?
The article does not discuss any potential drawbacks or limitations of increasing operation voltage on processors.
Original Abstract Submitted
apparatuses, systems, and techniques to optimize processor performance. in at least one embodiment, a method increases an operation voltage of one or more processors, based at least in part, on one or more error rates of the one or more processors.
- Nvidia corporation
- Benjamin D. Faulkner of Los Altos Hills CA (US)
- Padmanabhan Kannan of Santa Clara CA (US)
- Srinivasan Raghuraman of San Jose CA (US)
- Peng Cheng Shen of Sunnyvale CA (US)
- Divya Ramakrishnan of San Jose CA (US)
- Swanand Santosh Bindoo of San Jose CA (US)
- Sreedhar Narayanaswamy of Sunnyvale CA (US)
- Amey Y. Marathe of Union City CA (US)
- G06F1/30
- G06F11/07