NVIDIA Corporation patent applications on September 5th, 2024
Patent Applications by NVIDIA Corporation on September 5th, 2024
NVIDIA Corporation: 12 patent applications
NVIDIA Corporation has applied for patents in the areas of G06F9/38 (2), G06F9/50 (2), G06N3/08 (2), H04L25/03 (2), G06T17/20 (2) H04L25/03171 (2), G06T17/20 (2), G06F9/3877 (1), G06F9/4881 (1), G06F13/161 (1)
With keywords such as: data, frame, voltage, domain, node, logic, density, network, lights, and various in patent application abstracts.
Patent Applications by NVIDIA Corporation
20240296052. DEVICE LINK MANAGEMENT_simplified_abstract_(nvidia corporation)
Inventor(s): Mitesh Meswani of Austin TX (US) for nvidia corporation, Kapil Dev of Milpitas CA (US) for nvidia corporation
IPC Code(s): G06F9/38, G06F9/48, G06F9/50, G06N3/08
CPC Code(s): G06F9/3877
Abstract: apparatuses, systems, and techniques to optimize device communications disclosed. in at least one embodiment, one or more neural networks are used to determine optimal power and frequency states for communication links between processing devices.
Inventor(s): Ashutosh Tadkase of Los Altos Hills CA (US) for nvidia corporation, Ian Tramble of Mountain View CA (US) for nvidia corporation, Akash Bellubbi of San Jose CA (US) for nvidia corporation, Suraj Das of Santa Clara CA (US) for nvidia corporation, Ranvijay Singh of Santa Clara CA (US) for nvidia corporation, Linda Xiong of Milpitas CA (US) for nvidia corporation, John Lore of San Jose (CA) for nvidia corporation, Albert Davies of San Jose CA (US) for nvidia corporation, Ian Howson of Santa Clara CA (US) for nvidia corporation, Peter Boonstoppel of Pleasanton CA (US) for nvidia corporation, Sai Gurrappadi of Santa Clara CA (US) for nvidia corporation, Pulkit Desai of San Jose CA (US) for nvidia corporation, Sever Topan of Burnaby CA (US) for nvidia corporation, Sharat Janapareddy of San Jose CA (US) for nvidia corporation, Ashkan Vafaee of Austin TX (US) for nvidia corporation, Michael Cox of Menlo Park CA (US) for nvidia corporation
IPC Code(s): G06F9/48, G06F9/30, G06F9/38, G06F9/50, G06F9/54, G06F11/07, G06F21/52
CPC Code(s): G06F9/4881
Abstract: one or more embodiments of the present disclosure relate to switching between execution schedules related to execution of tasks, or runnables, by multiple compute engines. the execution schedules includes respective sets of commands that dictate timing and order of execution, by the compute engines, of tasks, or runnables, corresponding to computing applications.
Inventor(s): Anurag CHAUDHARY of San Jose CA (US) for nvidia corporation, Scott Matthew PITKETHLY of Tampa FL (US) for nvidia corporation, Peter Lindsay GENTLE of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F13/16, G06F13/40
CPC Code(s): G06F13/161
Abstract: various embodiments include a network for transmitting data words from a source node to a destination node. the source node optionally inverts the logic levels of each data word so that the number of logic ‘1’ bits in each data word is less than or equal to half of the data bits. the destination node recovers the original data words by passing the data words not inverted by the source node and inverting the data words that were inverted by the source node. as the packet is transmitted through the network, each node encodes and/or decodes the data words by generating an output transition for each logic ‘1’ bit of the input data word. because no more than half the bits of the input data word are logic ‘1’ bits, the node generates output transitions for no more than one half of the data bits.
Inventor(s): David Acuna Marrero of Toronto (CA) for nvidia corporation, Guojun Zhang of Waterloo (CA) for nvidia corporation, Marc Law of Ontario (CA) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation
IPC Code(s): G06F18/214, G06F18/21, G06F18/241, G06N3/045, G06N3/08, G06V10/40
CPC Code(s): G06F18/2148
Abstract: approaches presented herein provide for unsupervised domain transfer learning. in particular, three neural networks can be trained together using at least labeled data from a first domain and unlabeled data from a second domain. features of the data are extracted using a feature extraction network. a first classifier network uses these features to classify the data, while a second classifier network uses these features to determine the relevant domain. a combined loss function is used to optimize the networks, with a goal of the feature extraction network extracting features that the first classifier network is able to use to accurately classify the data, but prevent the second classifier from determining the domain for the image. such optimization enables object classification to be performed with high accuracy for either domain, even though there may have been little to no labeled training data for the second domain.
Inventor(s): Anand Kumar Rajaram of Austin TX (US) for nvidia corporation, Erik Welty of Austin TX (US) for nvidia corporation, David Lyndell Brown of Austin TX (US) for nvidia corporation
IPC Code(s): G06F30/396, G06F30/392
CPC Code(s): G06F30/396
Abstract: mechanisms to place flip-flops and other synchronous logic cells in a circuit layout in a clock on-chip variation-aware, predetermined order based on analysis of the clock gating, connectivity, and logic depth of the unplaced netlist. the resulting placements enable clock trees having a regular structure leading to improvements in clock on-chip variation, timing, and clock power.
Inventor(s): Christopher Ryan Wyman of Redmond WA (US) for nvidia corporation, Benedikt Martin Bitterli of Kirkland WA (US) for nvidia corporation
IPC Code(s): G06T15/50, G06T15/00, G06T15/20
CPC Code(s): G06T15/506
Abstract: apparatuses, systems, and techniques to render computer graphics. in at least one embodiment, a first one or more lights are selected from among lights in a virtual scene to be rendered as a frame of graphics, and a second one or more lights are selected from among lights used to render one or more pixels in at least one of a prior frame or the current frame. a pixel of the current frame is rendered using the first and second one or more lights, and a light is selected for reuse in rendering a subsequent frame from among the first and second one or more lights.
Inventor(s): Jiahui Huang of Beijing (CN) for nvidia corporation, Francis Williams of Brooklyn NY (US) for nvidia corporation, Zan Gojcic of Zurich (CH) for nvidia corporation, Matan Atzmon of Toronto (CA) for nvidia corporation, Or Litany of Sunnyvale CA (US) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation
IPC Code(s): G06T17/20, G06T15/08
CPC Code(s): G06T17/20
Abstract: approaches presented herein provide for the reconstruction of implicit multi-dimensional shapes. in one embodiment, oriented point cloud data representative of an object can be obtained using a physical scanning process. the point cloud data can be provided as input to a trained density model that can infer density functions for various points. the points can be mapped to a voxel hierarchy, allowing density functions to be determined for those voxels at the various levels that are associated with at least one point of the input point cloud. contribution weights can be determined for the various density functions for the sparse voxel hierarchy, and the weighted density functions combined to obtain a density field. the density field can be evaluated to generate a geometric mesh where points having a zero, or near-zero, value are determined to contribute to the surface of the object.
Inventor(s): Tianchang Shen of Markham CA (US) for nvidia corporation, Jun Gao of Toronto (CA) for nvidia corporation, Kangxue Yin of Toronto (CA) for nvidia corporation, Ming-Yu Liu of San Jose CA (US) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation
IPC Code(s): G06T17/20, G06T7/50
CPC Code(s): G06T17/20
Abstract: in various examples, a deep three-dimensional (3d) conditional generative model is implemented that can synthesize high resolution 3d shapes using simple guides—such as coarse voxels, point clouds, etc.—by marrying implicit and explicit 3d representations into a hybrid 3d representation. the present approach may directly optimize for the reconstructed surface, allowing for the synthesis of finer geometric details with fewer artifacts. the systems and methods described herein may use a deformable tetrahedral grid that encodes a discretized signed distance function (sdf) and a differentiable marching tetrahedral layer that converts the implicit sdf representation to an explicit surface mesh representation. this combination allows joint optimization of the surface geometry and topology as well as generation of the hierarchy of subdivisions using reconstruction and adversarial losses defined explicitly on the surface mesh.
Inventor(s): Jason Golbus of Santa Clara CA (US) for nvidia corporation, Chad Parsons of Santa Clara CA (US) for nvidia corporation, Kirk Twardowski of Santa Clara CA (US) for nvidia corporation, Lalit Gupta of Santa Clara CA (US) for nvidia corporation, Jesse Wang of Santa Clara CA (US) for nvidia corporation, Ka Yun Lee of Santa Clara CA (US) for nvidia corporation, Amy Chen of Santa Clara CA (US) for nvidia corporation, Ramya Challa of Santa Clara CA (US) for nvidia corporation, Karan Gupta of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G11C7/10, G11C29/50
CPC Code(s): G11C7/1048
Abstract: the disclosure provides improvements for transmitting data between different voltage domains of an ic, such as a chip. the disclosure introduces a data transfer circuit that uses a multi-voltage ram, referred to herein as mvram, for transmitting data across the different voltage domains. the mvram has multiple memory cells with write ports and read ports on different clock and voltage domains. accordingly, a write operation can occur completely on the write domain voltage and the read operation can occur completely on the read domain voltage. in one example, the data transfer circuit includes: (1) write logic operating at a first operating voltage, (2) read logic operating at second operating voltage, and (3) a mvram with write ports that operate under the first operating voltage and read ports that operate under the second operating voltage.
Inventor(s): Jeremy David Furtek of San Antonio TX (US) for nvidia corporation
IPC Code(s): H04L25/03
CPC Code(s): H04L25/03171
Abstract: apparatuses, systems, and techniques to demodulate data for fifth-generation (5g) new radio (nr). in at least one embodiment, a processor includes one or more circuits to use a parallel processor to determine a signal value based, at least in part, on one or more predetermined probability values.
Inventor(s): Jeremy David Furtek of San Antonio TX (US) for nvidia corporation
IPC Code(s): H04L25/03
CPC Code(s): H04L25/03171
Abstract: apparatuses, systems, and techniques to demodulate data for fifth-generation (5g) new radio (nr). in at least one embodiment, a processor includes one or more circuits to use a parallel processor to determine a signal value based, at least in part, on one or more predetermined probability values.
Inventor(s): Jonathan Baird MCCAFFREY of Santa Clara CA (US) for nvidia corporation, Richard Gavin BRAMLEY of Santa Clara CA (US) for nvidia corporation, Prashant CHANDRASEKHAR of San Ramon CA (US) for nvidia corporation, Sang Hun LEE of Surrey (CA) for nvidia corporation, Sujay Raghavendra YADAWADKAR of Santa Clara CA (US) for nvidia corporation
IPC Code(s): H04N7/18, G06T7/80, H04N5/265
CPC Code(s): H04N7/181
Abstract: in various examples, a technique for performing transformation-invariant detection of duplicate frames includes determining a first sequence number for a first output frame, where the first output frame includes one or more views captured using one or more cameras. the technique also includes performing a first comparison of one or more pixel values from the first output frame. the technique further includes based at least on the sequence number not corresponding to the one or more pixel values, performing one or more operations with respect to the first output frame.
NVIDIA Corporation patent applications on September 5th, 2024
- NVIDIA Corporation
- G06F9/38
- G06F9/48
- G06F9/50
- G06N3/08
- CPC G06F9/3877
- Nvidia corporation
- G06F9/30
- G06F9/54
- G06F11/07
- G06F21/52
- CPC G06F9/4881
- G06F13/16
- G06F13/40
- CPC G06F13/161
- G06F18/214
- G06F18/21
- G06F18/241
- G06N3/045
- G06V10/40
- CPC G06F18/2148
- G06F30/396
- G06F30/392
- CPC G06F30/396
- G06T15/50
- G06T15/00
- G06T15/20
- CPC G06T15/506
- G06T17/20
- G06T15/08
- CPC G06T17/20
- G06T7/50
- G11C7/10
- G11C29/50
- CPC G11C7/1048
- H04L25/03
- CPC H04L25/03171
- H04N7/18
- G06T7/80
- H04N5/265
- CPC H04N7/181
