NVIDIA Corporation patent applications on September 19th, 2024
Patent Applications by NVIDIA Corporation on September 19th, 2024
NVIDIA Corporation: 14 patent applications
NVIDIA Corporation has applied for patents in the areas of G06T15/50 (3), G06N3/045 (2), G06F7/544 (2), G06T7/00 (1), G06V10/82 (1) G06T15/506 (3), B25J9/1674 (1), G06F3/165 (1), G06F9/4484 (1), G06F9/505 (1)
With keywords such as: systems, generate, data, various, feature, features, processing, safety, training, and based in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Riccardo Mariani of Porto Azzurro (IT) for nvidia corporation, Sudesh Kamath of Fremont CA (US) for nvidia corporation, Bhanu Pisupati of Cupertino CA (US) for nvidia corporation, Mathias Blake of Saratoga CA (US) for nvidia corporation, Gary Hicok of Mesa AZ (US) for nvidia corporation, Jacob Liberman of Austin TX (US) for nvidia corporation, Tarun Rathor of Pune (IN) for nvidia corporation
IPC Code(s): B25J9/16, G06V20/52
CPC Code(s): B25J9/1674
Abstract: in various examples, providing proactive safety measures for robotic systems and equipment is described herein. for instance, systems and methods may monitor equipment (e.g., a machine) in order to proactively detect potential safety events that may occur with regard to the equipment and/or activate one or more proactive safety measures in order to mitigate and/or eliminate the safety events before occurring. for example, sensors that are external to the equipment may generate sensor data representing the environment at least partially surrounding the equipment. the sensor data may then be processed to determine when a potential safety event is occurring with regard to the equipment. one or more safety measures may then be activated based at least on detecting the potential safety event, such as activating a warning and/or causing an internal reactive safety measure of the equipment to activate.
20240311080. DYNAMICALLY PREVENTING AUDIO ARTIFACTS_simplified_abstract_(nvidia corporation)
Inventor(s): Utkarsh Vaidya of Santa Clara CA (US) for nvidia corporation, Sumit Bhattacharya of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06F3/16, G06N3/045, G06N7/01
CPC Code(s): G06F3/165
Abstract: the disclosure is directed to a process that can predict and prevent an audio artifact from occurring. the process can monitor the systems, processes, and execution threads on a larger system/device, such as a mobile or in-vehicle device. using a learning algorithm, such as deep neural network (dnn), the information collected can generate a prediction of whether an audio artifact is likely to occur. the process can use a second learning algorithm, which also can be a dnn, to generate recommended system adjustments that can attempt to prevent the audio glitch from occurring. the recommendations can be for various systems and components on the device, such as changing the processing system frequency, the memory frequency, and the audio buffer size. after the audio artifact has been prevented, the system adjustments can be reversed fully or in steps to return the system to its state prior to the system adjustments.
20240311163. HARDWARE-DRIVEN CALL STACK ATTRIBUTION_simplified_abstract_(nvidia corporation)
Inventor(s): Avinash Bantval Baliga of Cedar Park TX (US) for nvidia corporation, Gregory Paul Smith of Cedar Park TX (US) for nvidia corporation, Magnus Strengert of Cedar Park TX (US) for nvidia corporation
IPC Code(s): G06F9/38
CPC Code(s): G06F9/4484
Abstract: apparatuses, systems, and techniques for hardware-driven call stack attribution. the apparatuses, systems, and techniques includes generating and updating call stacks within a processing device during execution of an application. in particular, determining a branch identifier associated with an instruction being executed by an execution thread, identifying a call stack identifier of the execution thread executing the instruction, and updating the call stack identifier of the execution thread based on the identified call stack identifier of the execution thread and the branch identifier.
Inventor(s): Duane George MERRILL, III of Charlottesville VA (US) for nvidia corporation
IPC Code(s): G06F9/50, G06F7/544
CPC Code(s): G06F9/505
Abstract: in various embodiments, a dispatch application performs multiply-accumulate (“mac”) computations across parallel processing elements. in operation, the dispatch application determines a first quantity of iterations associated with a given mac computation. the dispatch application determines a maximum number of tasks that can execute concurrently across a set of parallel processing elements. subsequently, the dispatch application causes the maximum number of tasks to be executed concurrently across the set of parallel processing elements in order to perform the mac computation. during execution, each task performs a substantially similar number of the first quantity of iterations. relative to conventional tile-based approaches to performing mac computations across parallel processing elements, the dispatch application can more evenly distribute iterations across the different parallel processing elements. accordingly, the dispatch application can reduce the amount of parallel processing element idle time when performing mac computations.
Inventor(s): Siamak Nazari of Mountain View CA (US) for nvidia corporation, JONATHAN ANDREW MCDOWELL of Belfast (GB) for nvidia corporation, PHILIP HERRON of Lisburn (GB) for nvidia corporation
IPC Code(s): G06F11/14, G06F11/20
CPC Code(s): G06F11/1464
Abstract: a storage platform () improves data flow when modifying mirrored volumes. a backup storage component ( a) that receives a service request keeps a copy of change data when redirecting the service request to a primary storage component (b) that owns the volume that the service request targets. the primary storage (b) component does not need to return the change data to the backup storage component (a) when the primary storage component (b) instructs the backup storage component ( a) to apply the modification request to the backup copy of the volume.
Inventor(s): Yi Dong of Lexington MA (US) for nvidia corporation, Xianchao Wu of Tokyo (JP) for nvidia corporation, Yi Fen Zenodia Charpy of Alingsås (SE) for nvidia corporation
IPC Code(s): G06F40/40
CPC Code(s): G06F40/40
Abstract: disclosed are systems and techniques that may generate prompts for language models. the techniques include obtaining a first dataset and a second dataset and training a hierarchical virtual token generator (vtg) model to generate a large language model (llm) input prompt. training the hierarchical vtg includes training, based on the first dataset, a first vtg to output a first virtual token and training, based on the second dataset, a second vtg to output a second virtual token embedding. the generated llm input prompt includes the first virtual token embedding and the second virtual token embedding.
Inventor(s): William James Dally of Incline Village NV (US) for nvidia corporation, Rangharajan Venkatesan of San Jose CA (US) for nvidia corporation, Brucek Kurdo Khailany of Austin TX (US) for nvidia corporation, Stephen G. Tell of Chapel Hill NC (US) for nvidia corporation
IPC Code(s): G06N3/063, G06F7/544, G06F7/575, G06F17/16, G06N3/02, G06N3/045
CPC Code(s): G06N3/063
Abstract: neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. however, performing addition on logarithmic format values is more complex. conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components using an asynchronous accumulator to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. the sum may then be converted back into the logarithmic format.
Inventor(s): Matthew JONES of Santa Clara CA (US) for nvidia corporation, Taylor Lee PATTI of Orange CA (US) for nvidia corporation
IPC Code(s): G06N10/20
CPC Code(s): G06N10/20
Abstract: in various examples, systems and methods for optimizing quantum computing circuit state partitions for simulation are provided. a quantum state of a quantum circuit may be represented by one or more state vector partitions. gate grouping, gate complexity, and/or qubit ordering optimization algorithms may be applied, and the one or more state vector partitions evaluated against a computing platform topology profile using a cost evaluation function. the cost evaluation function may estimate an efficiency associated with executing that the one or more state vector partitions given the processing resources of the currently available simulation platform for running the simulation. the one or more state vector partitions optimized for the simulation platform may be passed to the simulation platform in order to simulate the quantum circuit.
Inventor(s): Nicolas Moenne-Loccoz of Mont-Royal (CA) for nvidia corporation, Zan Gojcic of Zurich (CH) for nvidia corporation, Gavriel State of Toronto (CA) for nvidia corporation, Zian Wang of Toronto (CA) for nvidia corporation, Ignacio Llamas of Palo Alto CA (US) for nvidia corporation
IPC Code(s): G06T15/50, G06T5/50, G06V10/60, G06V10/74, G06V10/82
CPC Code(s): G06T15/506
Abstract: approaches presented herein provide for the generation of visual content, including different types of content representations from different sources, rendered to include consistent scene illumination for the various representations. a first render pass can produce a first image including only proxies of implicit representations (e.g., nerf objects) under scene illumination. a second render pass can produce a second image that includes a representation of the explicit scene objects, as well as the proxies of the implicit representations, under the scene illumination, which produces secondary lighting effects. the first and second images are compared to determine irradiance ratio data for the various pixel locations. a third render pass can produce a third image that includes the implicit representations, which can have relighting performed according to the irradiance ratio data to include the secondary lighting effects. the implicit and explicit objects can then be composited to produce an image with consistent scene illumination.
Inventor(s): Malik Aqeel Anwar of Atlanta GA (US) for nvidia corporation, Tae Eun Choe of Belmont CA (US) for nvidia corporation, Zian Wang of Toronto (CA) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation, Minwoo Park of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T15/50, G06T15/60, G06T19/20, G06V10/774, H04N23/698
CPC Code(s): G06T15/506
Abstract: in various examples, systems and methods are disclosed that relate to data augmentation for training/updating perception models in autonomous or semi-autonomous systems and applications. for example, a system may receive data associated with a set of frames that are captured using a plurality of cameras positioned in fixed relation relative to the machine; generate a panoramic view based at least on the set of frames; provide data associated with the panoramic view to a model to cause the model to generate a high dynamic range (hdr) panoramic view; determine lighting information associated with a light distribution map based at least on the hdr panoramic view; determine a virtual scene; and render an asset and a shadow on at least one of the frames, based at least on the virtual scene and the light distribution map, the shadow being a shadow corresponding to the asset.
Inventor(s): Alexey Panteleev of Los Gatos CA (US) for nvidia corporation
IPC Code(s): G06T15/50, G06T7/00, G06T7/246, G06T13/20
CPC Code(s): G06T15/506
Abstract: robust temporal gradients, representing differences in shading results, can be computed between current and previous frames in a temporal denoiser for ray-traced renderers. backward projection can be used to locate matching surfaces, with the relevant parameters of those surfaces being carried forward and used for patching. backward projection can be performed for each stratum in a current frame, a stratum representing a set of adjacent pixels. a pixel from each stratum is selected that has a matching surface in the previous frame, using motion vectors generated during the rendering process. a comparison of the depth of the normals, or the visibility buffer data, can be used to determine whether a given surface is the same in the current frame and the previous frame, and if so then parameters of the surface from the previous frame g-buffer is used to patch the g-buffer for the current frame.
Inventor(s): Yue Wu of Mountain View CA (US) for nvidia corporation, Cheng-Chieh Yang of Sunnyvale CA (US) for nvidia corporation, Xin Tong of Santa Clara CA (US) for nvidia corporation, Minwoo Park of Saratoga CA (US) for nvidia corporation
IPC Code(s): G06V10/771, G06V10/77
CPC Code(s): G06V10/771
Abstract: in various examples, feature tracking for autonomous or semi-autonomous systems and applications is described herein. systems and methods are disclosed that merge, using one or more processes, features detected using a feature tracker(s) and features detected using a feature detector(s) in order to track features between images. in some examples, the number of merged features and/or the locations of the merged features within the images are limited. this way, the systems and methods are able to identify merged features that are of greater importance for tracking while refraining from tracking merged features that are of less importance. for example, if the systems and methods are being used to identify features for autonomous driving, a greater number of merged features that are associated with objects located proximate to the driving surface may be tracked as compared to merged features that are associated with the sky.
Inventor(s): Jiwoong Choi of Sunnyvale CA (US) for nvidia corporation, Jose Manuel Alvarez Lopez of Mountain View CA (US) for nvidia corporation, Shiyi Lan of Sunnyvale CA (US) for nvidia corporation, Yashar Asgarieh of Palo Alto CA (US) for nvidia corporation, Zhiding Yu of Cupertino CA (US) for nvidia corporation
IPC Code(s): G06V20/58, B60W60/00
CPC Code(s): G06V20/58
Abstract: in various examples, temporal-based perception for autonomous or semi-autonomous systems and applications is described. systems and methods are disclosed that use a machine learning model (mlm) to intrinsically fuse feature maps associated with different sensors and different instances in time. to generate a feature map, image data generated using image sensors (e.g., cameras) located around a vehicle are processed using a mlm that is trained to generate the feature map. the mlm may then fuse the feature maps in order to generate a final feature map associated with a current instance in time. the feature maps associated with the previous instances in time may be preprocessed using one or more layers of the mlm, where the one or more layers are associated with performing temporal transformation before the fusion is performed. the mlm may then use the final feature map to generate one or more outputs.
Inventor(s): Bartley Douglas Richardson of Alexandria VA (US) for nvidia corporation, Shawn Davis of Burke VA (US) for nvidia corporation, Gorkem Batmaz of Cambridge (GB) for nvidia corporation, Rachel Allen of Arlington VA (US) for nvidia corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/1483
Abstract: approaches in accordance with various illustrative embodiments provide for the generation of synthetic communications for use in training and fine-tuning threat detection models for various categories of recipients. in at least one embodiment, guidelines can be determined for a category of recipient that can be used to generate multiple types of content using generative artificial intelligence (ai), as may include text, image, and file content. a training communication can be generated using these types of content, such as to generate an email message that corresponds to a potential spear phishing attack. the generated messages can be checked for quality, and any messages that are caught by existing filters can be deleted or regenerated so that only high quality examples of spear phishing are provided as output. these training communications can be used to train a spear phishing detector for a specific category of recipient, in order to accurately flag and prevent access to actual spear phishing communications.
NVIDIA Corporation patent applications on September 19th, 2024
- NVIDIA Corporation
- B25J9/16
- G06V20/52
- CPC B25J9/1674
- Nvidia corporation
- G06F3/16
- G06N3/045
- G06N7/01
- CPC G06F3/165
- G06F9/38
- CPC G06F9/4484
- G06F9/50
- G06F7/544
- CPC G06F9/505
- G06F11/14
- G06F11/20
- CPC G06F11/1464
- G06F40/40
- CPC G06F40/40
- G06N3/063
- G06F7/575
- G06F17/16
- G06N3/02
- CPC G06N3/063
- G06N10/20
- CPC G06N10/20
- G06T15/50
- G06T5/50
- G06V10/60
- G06V10/74
- G06V10/82
- CPC G06T15/506
- G06T15/60
- G06T19/20
- G06V10/774
- H04N23/698
- G06T7/00
- G06T7/246
- G06T13/20
- G06V10/771
- G06V10/77
- CPC G06V10/771
- G06V20/58
- B60W60/00
- CPC G06V20/58
- H04L9/40
- CPC H04L63/1483
