NVIDIA Corporation patent applications on September 12th, 2024
Patent Applications by NVIDIA Corporation on September 12th, 2024
NVIDIA Corporation: 19 patent applications
NVIDIA Corporation has applied for patents in the areas of G06T1/20 (3), B25J9/16 (2), G06V20/10 (2), G06F9/38 (2), G06V10/82 (2) B25J9/163 (2), G06T15/06 (2), G06T7/50 (1), H04L47/35 (1), H04L9/0822 (1)
With keywords such as: based, object, data, images, memory, network, virtual, translation, error, and such in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Bingjie TANG of Los Angeles CA (US) for nvidia corporation, Yashraj Shyam NARANG of Seattle WA (US) for nvidia corporation, Dieter FOX of Seattle WA (US) for nvidia corporation, Fabio TOZETO RAMOS of Seattle WA (US) for nvidia corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/163
Abstract: one embodiment of a method for training a machine learning model to control a robot includes causing a model of the robot to move within a simulation based on one or more outputs of the machine learning model, computing an error within the simulation, computing at least one of a reward or an observation based on the error, and updating one or more parameters of the machine learning model based on the at least one of a reward or an observation.
Inventor(s): Yashraj Shyam NARANG of Seattle WA (US) for nvidia corporation, Ankur HANDA of Seattle WA (US) for nvidia corporation, Karl VAN WYK of Issaquah WA (US) for nvidia corporation, Dieter FOX of Seattle WA (US) for nvidia corporation, Michael Andres LIN of San Mateo CA (US) for nvidia corporation, Fabio TOZETO RAMOS of Seattle WA (US) for nvidia corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/163
Abstract: one embodiment of a method for controlling a robot includes receiving sensor data indicating a state of the robot, generating an action based on the sensor data and a trained machine learning model, computing a target state of the robot based on the action and a previous target state of the robot, and causing the robot to move based on the target state of the robot.
Inventor(s): Padam Patt Krishnani of Bangalore (IN) for nvidia corporation, Avinash J V of Bangalore (IN) for nvidia corporation, Shraddha Manohar Gondkar of San Jose CA (US) for nvidia corporation, Sowmya Satya Venkata Naga Siva Sai Bindu Mandapati of Atchutapuram (IN) for nvidia corporation
IPC Code(s): B60W60/00, B60W50/02, G06F11/07, G07C5/00
CPC Code(s): B60W60/0016
Abstract: in various examples, an integrated circuit includes first and second portions. the first portion includes a timer that starts when the first portion transmits at least one error signal to the second portion. the timer may reset when data corresponding to at least one fault has been cleared from the first portion. the first portion transmits a timeout error signal when the timer indicates at least a predetermined amount of time has elapsed. the second portion receives the at least one error signal and the timeout error signal when the timeout error signal has been sent. the second portion may notify an external system after the timeout error signal is received.
Inventor(s): Brent Ralph Boswell of Aloha OR (US) for nvidia corporation, Ming Y. Siu of Santa Clara CA (US) for nvidia corporation, Jack H. Choquette of Palo Alto CA (US) for nvidia corporation, Jonah M. Alben of San Jose CA (US) for nvidia corporation, Stuart Oberman of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G06F9/30, G06F9/38, G06T1/20
CPC Code(s): G06F9/30014
Abstract: a method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (mma) operations. the processor includes a datapath configured to execute the mma operation to generate a plurality of elements of a result matrix at an output of the datapath. each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the mma operation. a dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.
Inventor(s): Piotr SIELSKI of Lodz (PL) for nvidia corporation, Mehmet Akif ÇÖRDÜK of Munich (DE) for nvidia corporation
IPC Code(s): G06F9/38
CPC Code(s): G06F9/3895
Abstract: systems and methods in accordance with the present disclosure can implement a parallel processing system, such as a graphics processing unit (gpu)-based system, to generate solutions to complex computational problems. aspects of this technical solution can retrieve a plurality of solutions each representing a plurality of values in a multi-dimensional space, allocate, to one or more processing units associated with the one or more circuits and having a parallelized configuration, one or more of the plurality of solutions, modify, by the one or more processing units according to the parallelized configuration, at least one value of the one or more solutions allocated to the one or more processing units, to determine a plurality of modified solutions, and output, from the plurality of modified solutions, according to one or more criteria indicating a diversity among the plurality of modified solutions, a selected solution.
Inventor(s): Aninda Manocha of Bethesda MD (US) for nvidia corporation, Zi Yan of Belmont MA (US) for nvidia corporation, David Nellans of Round Rock TX (US) for nvidia corporation
IPC Code(s): G06F12/1027
CPC Code(s): G06F12/1027
Abstract: computer systems often employ virtual address translation hierarchies in which virtual memory addresses are mapped to physical memory. use of the virtual address translation hierarchy speeds up the virtual address translation when the required mapping is stored in one of the higher levels of the hierarchy. to reduce a number of misses occurring in the virtual address translation hierarchy, huge memory pages may be selectively employed, which map larger continuous regions of virtual memory to continuous regions of physical memory, thereby increasing the coverage of each entry in the virtual address translation hierarchy. the present disclosure provides hardware support for optimizing this huge memory page selection.
Inventor(s): Noam Dor Korem of Tal-EI (IL) for nvidia corporation, Brian Scott Pharris of Cary NC (US) for nvidia corporation, Jacob Subag of Haifa (IL) for nvidia corporation
IPC Code(s): G06F12/126, G06N3/0464
CPC Code(s): G06F12/126
Abstract: apparatuses, systems, and techniques to manage a cache located on a processor of a computing system using eviction priority based on based on memory reuse. memory addresses associated with a workload of an application executing using the processor are identified. an amount of reuse of the memory addresses corresponding to the workload is determined. a cache management policy for the workload is determined based on the amount of reuse. the cache management policy is applied to the cache.
Inventor(s): Ming-Yu LIU of Redwood City CA (US) for nvidia corporation, Xun HUANG of Pittsburgh PA (US) for nvidia corporation, Tero Tapani KARRAS of Helsinki (FI) for nvidia corporation, Timo AILA of Tuusula (FI) for nvidia corporation, Jaakko LEHTINEN of Helsinki (FI) for nvidia corporation
IPC Code(s): G06N3/088, G06F18/214, G06F18/2431, G06T3/02, G06T3/60, G06T7/73, G06V10/764, G06V10/82
CPC Code(s): G06N3/088
Abstract: a few-shot, unsupervised image-to-image translation (“funit”) algorithm is disclosed that accepts as input images of previously-unseen target classes. these target classes are specified at inference time by only a few images, such as a single image or a pair of images, of an object of the target type. a funit network can be trained using a data set containing images of many different object classes, in order to translate images from one class to another class by leveraging few input images of the target class. by learning to extract appearance patterns from the few input images for the translation task, the network learns a generalizable appearance pattern extractor that can be applied to images of unseen classes at translation time for a few-shot image-to-image translation task.
20240303504. FEDERATED LEARNING TECHNIQUE_simplified_abstract_(nvidia corporation)
Inventor(s): Ziyue Xu of Reston VA (US) for nvidia corporation, Holger Reinhard Roth of Rockville MD (US) for nvidia corporation, Meirui Jiang of Zoucheng (CN) for nvidia corporation, Wenqi Li of London (GB) for nvidia corporation, Dong Yang of Pocatello ID (US) for nvidia corporation, Can Zhao of Rockville MD (US) for nvidia corporation, Vishwesh Nath of Nashville TN (US) for nvidia corporation, Daguang Xu of Potomac MD (US) for nvidia corporation
IPC Code(s): G06N3/098
CPC Code(s): G06N3/098
Abstract: apparatuses, systems, and techniques to train/use one or more neural networks. in at least one embodiment, a processor comprises one or more circuits to cause neural network training information to be aggregated based, at least in part, on contribution of the neural network training data and one or more performance metrics of the neural network.
Inventor(s): Joonhwa Shin of Santa Clara CA (US) for nvidia corporation, Zheng Liu of Los Altos CA (US) for nvidia corporation, Kaustubh Purandare of San Jose CA (US) for nvidia corporation
IPC Code(s): G06T7/292, G06F17/15, G06T1/20, G06T11/20, G06V10/764, G06V10/82, G06V20/10, G06V20/58
CPC Code(s): G06T7/292
Abstract: in various examples, image areas may be extracted from a batch of one or more images and may be scaled, in batch, to one or more template sizes. where the image areas include search regions used for localization of objects, the scaled search regions may be loaded into graphics processing unit (gpu) memory and processed in parallel for localization. similarly, where image areas are used for filter updates, the scaled image areas may be loaded into gpu memory and processed in parallel for filter updates. the image areas may be batched from any number of images and/or from any number of single- and/or multi-object trackers. further aspects of the disclosure provide approaches for associating locations using correlation response values, for learning correlation filters in object tracking based at least on focused windowing, and for learning correlation filters in object tracking based at least on occlusion maps.
Inventor(s): Chao LIU of Pittsburgh PA (US) for nvidia corporation, Benjamin ECKART of Oakland CA (US) for nvidia corporation, Jan KAUTZ of Lexington MA (US) for nvidia corporation
IPC Code(s): G06T7/50, G06T7/20, G06V10/762
CPC Code(s): G06T7/50
Abstract: the disclosed method for generating a first depth map for a first frame of a video includes performing one or more operations to generate a first intermediate depth map based on the first frame and a second frame preceding the first frame within the video, performing one or more operations to generate a second intermediate depth map based on the first frame, and performing one or more operations to combine the first intermediate depth map and the second intermediate depth map to generate the first depth map.
Inventor(s): Gregory MUTHLER of Chapel Hill NC (US) for nvidia corporation, John BURGESS of Austin TX (US) for nvidia corporation, James ROBERTSON of Austin TX (US) for nvidia corporation, Magnus ANDERSON of Skane (SE) for nvidia corporation
IPC Code(s): G06T15/06, G06F9/50, G06T1/20, G06T15/00, G06T15/08, G06T17/10
CPC Code(s): G06T15/06
Abstract: enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. the traversal efficiency of such hardware accelerators are improved, for example, by transforming a ray, in hardware, from the ray's coordinate space to two or more coordinate spaces at respective points in traversing the hierarchical acceleration structure. in one example, the hardware accelerator is configured to transform a ray, received from a processor, from the world space to at least one alternate world space and then to an object space in hardware before a corresponding ray-primitive intersection results are returned to the processor. the techniques disclosed herein facilitate the use of additional coordinate spaces to orient acceleration structures in a manner that more efficiently approximate the space occupied by the underlying primitives being ray-traced.
Inventor(s): Jonathan Paul Story of Grafrath (DE) for nvidia corporation
IPC Code(s): G06T15/06, G06T15/60
CPC Code(s): G06T15/06
Abstract: in examples, the number of rays used to sample lighting conditions of a light source in a virtual environment with respect to particular locations in the virtual environment may be adapted to scene conditions. an additional ray(s) may be used for locations that tend to be associated with visual artifacts in rendered images. a determination may be made on whether to cast an additional ray(s) to a light source for a location and/or a quantity of rays to cast. to make the determination variables such as visibilities and/or hit distances of ray-traced samples of the light source may be analyzed for related locations in the virtual environment, such as those in a region around the location (e.g., within an n-by-n kernel centered at the location). factors may include variability in visibilities and/or hit distances, differences between visibilities and/or hit distances relative to the location, and magnitudes of hit distances.
Inventor(s): Joonhwa Shin of Santa Clara CA (US) for nvidia corporation, Fangyu Li of San Jose CA (US) for nvidia corporation, Zheng Liu of Los Altos CA (US) for nvidia corporation, Kaustubh Purandare of San Jose CA (US) for nvidia corporation
IPC Code(s): G06V20/40, G06F18/22, G06V20/10
CPC Code(s): G06V20/49
Abstract: apparatuses, systems, and techniques for dynamically composable object tracker configuration for intelligent video analytics systems. a state of one or more objects included in an object is tracked using an object tracking application that implements an object tracker of a first type based on images depicting the environment. a request is received to perform tracking using a second object tracker type that is different from the first object tracker type. the object tracking application is configured to implement an object tracker of the second object tracker type in accordance with the request. the state of the objects in the environment is tracked using the object tracking application that implements the object tracker of the second object tracker type based on the images depicting the environment.
Inventor(s): Xianchao Wu of Tokyo (JP) for nvidia corporation, Hideaki Tagami of Yokohama (JP) for nvidia corporation, Peiying Ruan of Kanazawa (JP) for nvidia corporation
IPC Code(s): G10L13/10, G06F40/247, G06T17/20
CPC Code(s): G10L13/10
Abstract: approaches presented herein provide systems and methods for generating three-dimensional (3d) content with fine grained emotions and character traits. a set of classifiers may be used to identify emotions and character traits from an input provided by a user. each of the classifiers in the set of classifiers may use a set of seed words that is expanded through methods including manual collection, synonym extension, and/or word alignment. an input may then be evaluated for indications of emotion and/or character traits, such as by identifying certain words or phrases present within the input. output vectors associated with the identified emotion and/or character traits may then be provided to different generative models to adjust content, such as modifications to output audio or facial expressions for digital character representations.
Inventor(s): Suchitra Mandar Joshi of Pune (IN) for nvidia corporation, Mihir Manohar Nyayate of Pune (IN) for nvidia corporation, Ambrish Dantrey of Pune (IN) for nvidia corporation
IPC Code(s): G10L21/0232, G10L25/51, G10L25/78
CPC Code(s): G10L21/0232
Abstract: in various examples, a noise reduction may be performed based at least on determining that audio data encoding sound includes undesirable sound or lacks desirable sound. a frequency is determined for audio data based at least on value(s) associated with frequency(ies) within a frequency band and used to determine that sound encoded in the audio data includes undesirable sound or lacks desirable sound.
Inventor(s): Ron Keidar of San Diego CA (US) for nvidia corporation, Xinxing Hu of Shanghai (CN) for nvidia corporation, Hye Su Lee of Santa Clara CA (US) for nvidia corporation
IPC Code(s): H04L9/08, H04L9/14
CPC Code(s): H04L9/0822
Abstract: approaches in accordance with various illustrative embodiments provide for the encryption of communications going into and out of a device, such as a chip or proprietary bus. the encryption can occur in a central root-of-trust (rot), which can include agents for individual communication protocols to generate session keys used to encrypt communications for individual sessions, and the data can be sent to a crypto engine for the respective communication protocol. a key tunnel unit can be used to receive a wrapped session key over the public bus and then unwrap the key in hardware, then able to then transmit the unwrapped session key to the corresponding crypto engine without exposing the session key to software executing on the device outside the rot. the receiving inline crypto engine can then use that session key to encrypt session data to be transmitted to a separate device or destination.
Inventor(s): John Martin SNYDER of San Francisco CA (US) for nvidia corporation, Nan JIANG of Sudbury MA (US) for nvidia corporation, Alan Lynn DAVIS of Coalville UT (US) for nvidia corporation, Larry Robert DENNISON of Mendon MA (US) for nvidia corporation
IPC Code(s): H04L47/35, H04L47/12, H04L47/28
CPC Code(s): H04L47/35
Abstract: one embodiment of a method for reducing network congestion cause by multicast communications includes receiving, via a network, first data associated with one or more multicast operations, determining a congestion state of the network based on the first data, and performing one or more operations to reduce an amount of second data that is transmitted via the network based on the congestion state of the network.
Inventor(s): Georgi M. Chalakov of Duvall WA (US) for nvidia corporation, Kody Kantor of Saint Paul MN (US) for nvidia corporation
IPC Code(s): H04L67/06, H04L67/104
CPC Code(s): H04L67/06
Abstract: approaches presented herein provide systems and methods for dynamic transport switching for messages transmitted within a compute environment. messages generated by publishers may be evaluated within a client library against one or more rules to select a transmission protocol for the message. if a message has a parameter exceeding a threshold, a direct peer-to-peer transmission protocol may be selected to bypass transmission of the message to an intermediary. the client library may generate a smaller message for publication to one or more subscribers. the subscribers may then directly communicate with the client library in order to transmit the message.
NVIDIA Corporation patent applications on September 12th, 2024
- NVIDIA Corporation
- B25J9/16
- CPC B25J9/163
- Nvidia corporation
- B60W60/00
- B60W50/02
- G06F11/07
- G07C5/00
- CPC B60W60/0016
- G06F9/30
- G06F9/38
- G06T1/20
- CPC G06F9/30014
- CPC G06F9/3895
- G06F12/1027
- CPC G06F12/1027
- G06F12/126
- G06N3/0464
- CPC G06F12/126
- G06N3/088
- G06F18/214
- G06F18/2431
- G06T3/02
- G06T3/60
- G06T7/73
- G06V10/764
- G06V10/82
- CPC G06N3/088
- G06N3/098
- CPC G06N3/098
- G06T7/292
- G06F17/15
- G06T11/20
- G06V20/10
- G06V20/58
- CPC G06T7/292
- G06T7/50
- G06T7/20
- G06V10/762
- CPC G06T7/50
- G06T15/06
- G06F9/50
- G06T15/00
- G06T15/08
- G06T17/10
- CPC G06T15/06
- G06T15/60
- G06V20/40
- G06F18/22
- CPC G06V20/49
- G10L13/10
- G06F40/247
- G06T17/20
- CPC G10L13/10
- G10L21/0232
- G10L25/51
- G10L25/78
- CPC G10L21/0232
- H04L9/08
- H04L9/14
- CPC H04L9/0822
- H04L47/35
- H04L47/12
- H04L47/28
- CPC H04L47/35
- H04L67/06
- H04L67/104
- CPC H04L67/06
