NVIDIA Corporation patent applications on October 24th, 2024
Patent Applications by NVIDIA Corporation on October 24th, 2024
NVIDIA Corporation: 14 patent applications
NVIDIA Corporation has applied for patents in the areas of H04N19/176 (2), G06V10/74 (2), G06T15/06 (2), G01C21/00 (1), H04N19/186 (1) G01C21/3804 (1), G01D3/036 (1), G01R31/2839 (1), G06F9/30043 (1), G06F9/52 (1)
With keywords such as: quantum, data, destination, based, cost, sensor, vectors, techniques, compute, and memory in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Anton Mitrokhin of Santa Clara CA (US) for nvidia corporation, Roman Parys of Adliswil (CH) for nvidia corporation, Alexey Solovey of Campbell CA (US) for nvidia corporation, Tilman Wekel of San Jose CA (US) for nvidia corporation
IPC Code(s): G01C21/00, G06T17/00, G06V10/74
CPC Code(s): G01C21/3804
Abstract: in various examples, generating maps using first sensor data and then annotating second sensor data using the maps for autonomous systems and applications is described herein. systems and methods are disclosed that automatically propagate annotations associated with the first sensor data generated using a first type of sensor, such as a lidar sensor, to the second sensor data generated using a second type of sensor, such as an image sensor(s). to propagate the annotations, the first type of sensor data may be used to generate a map, where the map represents the locations of static objects as well as the locations of dynamic objects at various instances in time. the map and annotations associated with the first sensor data may then be used to annotate the second sensor data and/or determine additional information associated with the objects represented by the second sensors data.
Inventor(s): Hossein Seifoory of Toronto (CA) for nvidia corporation, Elad Mentovich of Tel Aviv (IL) for nvidia corporation, Juan Jose Vegas Olmos of Solroed Strand (DK) for nvidia corporation
IPC Code(s): G01D3/036
CPC Code(s): G01D3/036
Abstract: systems, devices, and methods are described herein that are employed in quantum metrology. an example quantum device includes a weak measurement module operably coupled with a quantum system. the weak measurement module is configured to apply one or more measurements to the quantum system and obtain information associated with the quantum system based on the one or more measurements. a strength of the one or more measurements by the weak measurement module is configured to prevent a wave function collapse associated with the quantum system. the quantum device further includes a data processing unit (dpu) operably coupled with the weak measurement module that performs one or more operations on the obtained information associated with the quantum system and provides improved time synchronization and networking features.
20240353475. INTEGRATED CURRENT MONITOR_simplified_abstract_(nvidia corporation)
Inventor(s): Miguel Rodriguez of Santa Clara CA (US) for nvidia corporation, Suhas Satheesh of Santa Clara CA (US) for nvidia corporation, Tezaswi Raja of Santa Clara CA (US) for nvidia corporation, Nishit Harshad Shah of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G01R31/28, H03K17/687
CPC Code(s): G01R31/2839
Abstract: circuitry and a method of determining electrical characteristics of material local to a specific area of a semiconductor wafer is disclosed. in one embodiment, the method includes sinking or sourcing current through a selected on of a plurality of devices under test (duts) on the semiconductor wafer, converting the current sourcing or sinking into a voltage, comparing the converted voltage against a linear voltage ramp, generating an output clock based on the comparison, and measuring a duty cycle of the output clock. in one embodiment, the duty cycle of the output clock is dependent on the current sinking or sourcing through the selected at least one of the plurality of duts on the wafer and electrical characteristics of material local to the specific area of the wafer where the selected one of the plurality of duts is located are determined based on the duty cycle of the output clock.
Inventor(s): Srinivas Santosh Kumar MADUGULA of Visakhapatnam (IN) for nvidia corporation, Olivier GIROUX of Santa Clara CA (US) for nvidia corporation, Wishwesh Anil GANDHI of Sunnyvale CA (US) for nvidia corporation, Michael Allen PARKER of San Jose CA (US) for nvidia corporation, Raghuram L of Bengaluru (IN) for nvidia corporation, Ivan TANASIC of San Francisco CA (US) for nvidia corporation, Manan PATEL of San Jose CA (US) for nvidia corporation, Mark HUMMEL of Franklin MA (US) for nvidia corporation, Alexander L. MINKIN of Los Altos CA (US) for nvidia corporation, Gregory Michael THORSON of Mequon WI (US) for nvidia corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30043
Abstract: various embodiments include techniques for performing self-synchronizing remote memory operations in a data center or multiprocessor computing system. during a remote memory operation, a source processor transmits multiple data segments to a destination processor. for each data segment, the source processor transmits a remote memory operation to the destination processor that includes associated metadata that identifies the memory location of a corresponding synchronization object representing a count of data segments to be stored or a flag for each data segment to be stored. the remote memory operation along with the metadata is transmitted as a single unit to the destination processor. the destination processor splits the operation into the remote memory operation and the memory synchronization operation. as a result, the source processor avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.
Inventor(s): David Anthony Fontaine of Mountain View CA (US) for nvidia corporation, Jason David Gaiser of Campbell CA (US) for nvidia corporation, Steven Arthur Gurfinkel of San Francisco CA (US) for nvidia corporation, Sally Tessa Stevenson of Broomfield CO (US) for nvidia corporation, Vladislav Zhurba of San Jose CA (US) for nvidia corporation, Stephen Anthony Bernard Jones of San Francisco CA (US) for nvidia corporation
IPC Code(s): G06F9/52, G06F9/38, G06F9/48, G06F9/50, G06F9/54
CPC Code(s): G06F9/52
Abstract: apparatuses, systems, and techniques to facilitate graph code synchronization between application programming interfaces. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to cause graph code to wait on a semaphore used by another api.
Inventor(s): Razvan DINU of Voluntari (RO) for nvidia corporation, Jonathan Michael COHEN of Mountain View CA (US) for nvidia corporation, Christopher Marc PARISIEN of Toronto (CA) for nvidia corporation, Traian-Eugen REBEDEA of Bucharest (RO) for nvidia corporation
IPC Code(s): G06F16/332, G06F40/35, G06F40/40
CPC Code(s): G06F16/3329
Abstract: systems and techniques are described related to providing dynamic, configurable, runtime model alignment—in the form of guardrails, in embodiments—for language models (such as llms) using a formal modeling language. in at least one embodiment, a dialog flow is determined based on a user input and executed using a language model to generate an output. the dialog flow is specified in a formal modeling programming language and controls output of the language model.
20240354570. VECTOR CLUSTERED QUANTIZATION_simplified_abstract_(nvidia corporation)
Inventor(s): Reena Elangovan of Santa Clara CA (US) for nvidia corporation, Charbel Sakr of Mountain View CA (US) for nvidia corporation, Brucek Kurdo Khailany of Austin TX (US) for nvidia corporation
IPC Code(s): G06N3/08, G06N3/0495
CPC Code(s): G06N3/08
Abstract: vector clustered quantization reduces precision (bitwidth) vectors of parameters and may enable energy-efficient acceleration of deep neural networks. a vector comprises one or more parameters within a single dimension of a multi-dimensional tensor (matrix or kernel). a set of quantizers is initialized for a first step (vector-clustering). after initialization, vectors are mapped into clusters based on quantization errors, where each one of the clusters is associated with a different one of the quantizers. during the second step (per-cluster quantization) each quantizer is optimized to quantize the vectors in the cluster that is associated with the quantizer. in an embodiment, the quantizers are optimized using the lloyd-max algorithm, which effectively minimizes the per-cluster quantization noise. the first and second steps may be repeated before the vectors are quantized for processing by a neural network model.
Inventor(s): Hossein Seifoory of Toronto (CA) for nvidia corporation, Elad Mentovich of Tel Aviv (IL) for nvidia corporation, Juan Jose Vegas Olmos of Solroed Strand (DK) for nvidia corporation
IPC Code(s): G06N10/40
CPC Code(s): G06N10/40
Abstract: systems, devices, and methods are described herein that generate data packets in dpu assisted quantum metrology. an example quantum device includes a first quantum measurement module operably coupled with a first quantum system. the first quantum measurement module applies one or more measurements to the first quantum system and obtains information associated with the first quantum system based on the one or more measurements. the quantum device includes a first dpu operably coupled with the first quantum measurement module. the first dpu generates a data packet including time-related quantum data based upon at least one of the one or more measurements by the first quantum measurement module or the obtained information associated with the first quantum system.
20240354912. RANK-1 LATTICE SAMPLING_simplified_abstract_(nvidia corporation)
Inventor(s): Alexander Georg Keller of Berlin (DE) for nvidia corporation, Carsten Alexander Waechter of Berlin (DE) for nvidia corporation, Nikolaus Binder of Berlin (DE) for nvidia corporation
IPC Code(s): G06T5/77, G06T11/00
CPC Code(s): G06T5/77
Abstract: in photorealistic image synthesis by light transport simulation, the colors of each pixel are an integral of a high-dimensional function. however, the functions to integrate contain discontinuities that cannot be predicted efficiently. in practice, the pixel colors are estimated by using monte carlo and quasi-monte carlo methods to sample light transport paths that connect light sources and cameras and summing up the contributions to evaluate an integral. because of the sampling, images appear noisy when the number of samples is insufficient. a rank-1 lattice sequence provides sample locations and these sample locations can be enumerated (assigned or distributed to pixels) according to a space-filling curve superimposed on a pixel grid. combinations of space-filling curves and rank-1 lattice sequences reduce correlations, are deterministic, and may be executed for each pixel in parallel. the rank-1 lattice sequence enables real-time light transport simulation, producing high visual quality even for low sampling rates.
20240355039. WATERTIGHT RAY TRIANGLE INTERSECTION_simplified_abstract_(nvidia corporation)
Inventor(s): Samuli LAINE of Uusimaa (FI) for nvidia corporation, Tero KARRAS of Uusimaa (FI) for nvidia corporation, Timo AILA of Helsinki (FI) for nvidia corporation, Robert OHANNESSIAN of Austin TX (US) for nvidia corporation, William Parsons NEWHALL, Jr. of Woodside CA (US) for nvidia corporation, Greg MUTHLER of Austin TX (US) for nvidia corporation, Ian KWONG of San Jose CA (US) for nvidia corporation, Peter NELSON of San Francisco CA (US) for nvidia corporation, John BURGESS of Austin TX (US) for nvidia corporation
IPC Code(s): G06T15/06, G06T15/00
CPC Code(s): G06T15/06
Abstract: a hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. the primitives may include triangles used in generating a virtual scene. the hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.
Inventor(s): Ingo Wald of Salt Lake City UT (US) for nvidia corporation, Steven Parker of Draper UT (US) for nvidia corporation
IPC Code(s): G06T15/50, G06T15/06
CPC Code(s): G06T15/506
Abstract: a compute node performing a distributed light transport simulation operation on a scene may select another compute node(s) for forwarding of a ray based on determining graphical data assigned to the other compute node(s) has already been intersection-tested using the ray. thus, the compute node can avoid forwarding the ray when the graphical data has already been processed using the ray, while providing flexibility in the partition strategy used to partition the scene amongst the compute nodes. the compute node may receive and/or determine traversal information indicating compute nodes that have already intersection-tested the ray and/or have not yet intersection-tested the ray. the traversal information may include a list of compute nodes that have or have not yet intersection-tested the ray. in some examples, the compute node replays the traversal logic used by the compute nodes to generate one or more portions of the list.
Inventor(s): Karan Gupta of Bangalore (IN) for nvidia corporation, Dane Thomas Mrazek of Redwood City CA (US) for nvidia corporation, Nan Jiang of Sudbury MA (US) for nvidia corporation, Mukesh Chand Agarwal of Bangalore (IN) for nvidia corporation
IPC Code(s): H04L49/101, H04L49/00, H04L49/9047
CPC Code(s): H04L49/101
Abstract: a dynamic destination selection (dds) crossbar, system for routing a packet, and a switch are provided. an illustrative dds crossbar includes one or more adaptive routing circuits to track destination credit and port availability at a time of dispatching a packet, group multiple destinations into super destination groups, perform dynamic destination routing within a super destination group, and use the destination credit and port availability for the super destination group at the time of receiving the packet to select an output destination for the packet.
Inventor(s): Yonghai Wu of Shanghai (CN) for nvidia corporation, Jianjun Chen of Shanghai (CN) for nvidia corporation, Yongmao Tang of Shanghai (CN) for nvidia corporation, Jing Yang of Shanghai (CN) for nvidia corporation, Wei Feng of Shanghai (CN) for nvidia corporation
IPC Code(s): H04N19/11, G06V10/74, H04N19/176, H04N19/186
CPC Code(s): H04N19/11
Abstract: disclosed are systems and techniques for efficient real-time codec encoding of video files. in one embodiments, the techniques include receiving one or more intra-prediction modes, each having a corresponding cost; calculating a first cost of a chroma-from-luma intra-prediction mode; calculating a second cost of the chroma-from-luma intra-prediction mode; and calculating a final cost based on the first cost and the second cost. the techniques also include selecting a final intra-prediction mode; generating, based on the selected final intra-prediction mode, a block of predicted pixels that approximates a block of source pixels of an image frame; and encoding a first alpha value in a bitstream.
Inventor(s): Yongmao Tang of Shanghai (CN) for nvidia corporation, Jianjun Chen of Shanghai (CN) for nvidia corporation, Junan Chen of Jiangsu (CN) for nvidia corporation, Yonghai Wu of Shanghai (CN) for nvidia corporation, Zejun Hu of Jiangsu (CN) for nvidia corporation, Wei Feng of Shanghai (CN) for nvidia corporation
IPC Code(s): H04N19/61, H04N19/105, H04N19/109, H04N19/122, H04N19/139, H04N19/156, H04N19/172, H04N19/176, H04N19/182, H04N19/423
CPC Code(s): H04N19/61
Abstract: disclosed are systems and techniques for efficient real-time codec encoding of video files. in one embodiment, the techniques include obtaining a first plurality of motion vectors of a first resolution, generating a second plurality of motion vectors of a second resolution, and calculating a first cost of the motion vector using a first cost function of a first size. the techniques include selecting a subset of motion vectors of the second plurality of motion vectors, calculating a second cost using a second cost function of a second size, and generating a plurality of combined motion vectors based on the subset of motion vectors. the techniques include calculating a third cost using the second cost function of the second size, selecting a final motion vector, and generating, based on the selected final motion vector, a block of predicted pixels that approximates a block of source pixels of an image frame.
NVIDIA Corporation patent applications on October 24th, 2024
- NVIDIA Corporation
- G01C21/00
- G06T17/00
- G06V10/74
- CPC G01C21/3804
- Nvidia corporation
- G01D3/036
- CPC G01D3/036
- G01R31/28
- H03K17/687
- CPC G01R31/2839
- G06F9/30
- CPC G06F9/30043
- G06F9/52
- G06F9/38
- G06F9/48
- G06F9/50
- G06F9/54
- CPC G06F9/52
- G06F16/332
- G06F40/35
- G06F40/40
- CPC G06F16/3329
- G06N3/08
- G06N3/0495
- CPC G06N3/08
- G06N10/40
- CPC G06N10/40
- G06T5/77
- G06T11/00
- CPC G06T5/77
- G06T15/06
- G06T15/00
- CPC G06T15/06
- G06T15/50
- CPC G06T15/506
- H04L49/101
- H04L49/00
- H04L49/9047
- CPC H04L49/101
- H04N19/11
- H04N19/176
- H04N19/186
- CPC H04N19/11
- H04N19/61
- H04N19/105
- H04N19/109
- H04N19/122
- H04N19/139
- H04N19/156
- H04N19/172
- H04N19/182
- H04N19/423
- CPC H04N19/61
