NVIDIA Corporation patent applications on October 17th, 2024
Patent Applications by NVIDIA Corporation on October 17th, 2024
NVIDIA Corporation: 4 patent applications
NVIDIA Corporation has applied for patents in the areas of A63F13/52 (1), A63F13/355 (1), G06F9/52 (1), G06F9/54 (1), G06N5/022 (1) A63F13/52 (1), G06F9/52 (1), G06N5/022 (1), H04B1/7093 (1)
With keywords such as: techniques, design, rendering, graph, include, systems, schedule, cells, apparatuses, and bounding in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Sau Yan Keith LI of San Jose CA (US) for nvidia corporation, Ziad Ben Hadj Alouane of San Jose CA (US) for nvidia corporation, Seth Schneider of San Jose CA (US) for nvidia corporation, Viktor Grigoryevich Vandanov of San Jose CA (US) for nvidia corporation, Rouslan Lyubomirov Dimitrov of Santa Clara CA (US) for nvidia corporation
IPC Code(s): A63F13/52, A63F13/355
CPC Code(s): A63F13/52
Abstract: disclosed are apparatuses, systems, and techniques that eliminate frame tears, reduce stutters, and minimize latency in frame rendering pipelines. the techniques include but are not limited to collecting one or more latency metrics associated with rendering of a first set of one or more frames using a graphics rendering pipeline operating according to a first frame-generation schedule. the techniques further include modifying, using the one or more latency metrics, a first frame-generation schedule to obtain a second frame-generation schedule. the techniques include, rendering using the graphics rendering pipeline operating according to the second frame-generation schedule, a second set of one or more frames, and causing the second set of frames to be displayed on a display device.
Inventor(s): David Anthony Fontaine of Mountain View CA (US) for nvidia corporation, Jason David Gaiser of Campbell CA (US) for nvidia corporation, Steven Arthur Gurfinkel of San Francisco CA (US) for nvidia corporation, Sally Tessa Stevenson of Broomfield CO (US) for nvidia corporation, Vladislav Zhurba of San Jose CA (US) for nvidia corporation, Stephen Anthony Bernard Jones of San Francisco CA (US) for nvidia corporation
IPC Code(s): G06F9/52, G06F9/54
CPC Code(s): G06F9/52
Abstract: apparatuses, systems, and techniques to facilitate graph code synchronization between application programming interfaces. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to cause graph code to update a semaphore used by another api.
Inventor(s): Tian Yang of Los Altos CA (US) for nvidia corporation, Shijia Hu of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06N5/022
CPC Code(s): G06N5/022
Abstract: apparatuses, systems, and techniques for bounding area planning using a congestion prediction model. placement data associated with cells of an ic design is identified. a graph based on the identified placement data is generated. the graph is provided as input to a machine learning model. the machine learning model is trained to predict, based on a given graph associated with cells according to a respective ic design, a congestion level for cells at one or more bounding areas of a respective ic design. outputs of the machine learning model are obtained. the outputs include congestion data indicating a congestion level for a first bounding area of the ic design. cells are designated for installation at a region, of the ic design, corresponding to the first bounding area.
Inventor(s): David Henry Schmitz of Encinitas CA (US) for nvidia corporation, James Hansen Delfeld of Austin TX (US) for nvidia corporation
IPC Code(s): H04B1/7093, H04W16/22
CPC Code(s): H04B1/7093
Abstract: apparatuses, systems, and techniques to decode fifth generation (5g) open radio access network (oran) wireless signals. in at least one embodiment, two or more operations associated with a fast walsh hadamard transform are used to decode 5g oran wireless signals in parallel.
NVIDIA Corporation patent applications on October 17th, 2024
