NVIDIA Corporation patent applications on October 10th, 2024
Patent Applications by NVIDIA Corporation on October 10th, 2024
NVIDIA Corporation: 13 patent applications
NVIDIA Corporation has applied for patents in the areas of G06F9/54 (3), G06F9/52 (2), G06T15/06 (2), B60W60/00 (1), G06T5/70 (1) G06F9/52 (2), B60W60/00272 (1), G01R31/31727 (1), G06F7/24 (1), G06F9/54 (1)
With keywords such as: clock, path, signal, count, pulse, phase, perception, when, based, and simulation in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Julia Ng of San Jose CA (US) for nvidia corporation, David Nister of Bellevue WA (US) for nvidia corporation, Zhenyi Zhang of San Jose CA (US) for nvidia corporation, Yizhou Wang of San Jose CA (US) for nvidia corporation
IPC Code(s): B60W60/00, B60W30/095
CPC Code(s): B60W60/00272
Abstract: in various examples, systems and methods are disclosed for weighting one or more optional paths based on obstacle avoidance or other safety considerations. in some embodiments, the obstacle avoidance considerations may be computed using a comparison of trajectories representative of safety procedures at present and future projected time steps of an ego-vehicle and other actors to ensure that each actor is capable of implementing their respective safety procedure while avoiding collisions at any point along the trajectory. this comparison may include filtering out a path(s) of an actor at a time step(s)—e.g., using a one-dimensional lookup—based on spatial relationships between the actor and the ego-vehicle at the time step(s). where a particular path—or point along the path—does not satisfy a collision-free standard, the path may be penalized more negatively with respect to the obstacle avoidance considerations, or may be removed from consideration as a potential path.
Inventor(s): Kedar Rajpathak of Santa Clara CA (US) for nvidia corporation, Tezaswi Raja of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G01R31/317, G05B19/4155, G06F1/14
CPC Code(s): G01R31/31727
Abstract: circuitry and a method of operating a clock monitoring circuit for monitoring a clock signal is disclosed. the method comprises generating a train of pulses corresponding to a duration of respective phases of a clock signal, counting a number of pulses in respective generated pulse trains, determining (using the number of pulses) when durations of subsequent phases of the clock signal lengthen, determining (using the number of pulses) when durations of the subsequent phases of the clock signal shorten, and providing a clock abnormality detect (cad) signal when the clock signal either lengthens or shortens. the number of pulses in each respective pulse train is indicative of the duration of the respective phases of the clock signal.
20240338175. TENSOR DIMENSION ORDERING TECHNIQUES_simplified_abstract_(nvidia corporation)
Inventor(s): Paul Martin Springer of Iserlohn (DE) for nvidia corporation, Ali Mohamad Charara of Knoxville TN (US) for nvidia corporation, Markus Hoehnerbach of Santa Clara CA (US) for nvidia corporation, Andreas Roland Hehn of Zürich (CH) for nvidia corporation
IPC Code(s): G06F7/24, G06F7/483, G06F7/78
CPC Code(s): G06F7/24
Abstract: apparatuses, systems, and techniques to store tensor operands. in at least one embodiment, modes of one or more tensor operands are sorted based, at least in part, on one or more performance metrics of one or more tensor operations to be performed using said one or more tensor operands.
Inventor(s): David Anthony Fontaine of Mountain View CA (US) for nvidia corporation, Jason David Gaiser of Campbell CA (US) for nvidia corporation, Steven Arthur Gurfinkel of San Francisco CA (US) for nvidia corporation, Sally Tessa Stevenson of Broomfield CO (US) for nvidia corporation, Vladislav Zhurba of San Jose CA (US) for nvidia corporation, Stephen Anthony Bernard Jones of San Francisco CA (US) for nvidia corporation
IPC Code(s): G06F9/52, G06F9/54
CPC Code(s): G06F9/52
Abstract: apparatuses, systems, and techniques to facilitate graph code synchronization between application programming interfaces. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to cause graph code to update a semaphore used by another api.
Inventor(s): David Anthony Fontaine of Mountain View CA (US) for nvidia corporation, Jason David Gaiser of Campbell CA (US) for nvidia corporation, Steven Arthur Gurfinkel of San Francisco CA (US) for nvidia corporation, Sally Tessa Stevenson of Broomfield CO (US) for nvidia corporation, Vladislav Zhurba of San Jose CA (US) for nvidia corporation, Stephen Anthony Bernard Jones of San Francisco CA (US) for nvidia corporation
IPC Code(s): G06F9/52, G06F9/38, G06F9/48, G06F9/50, G06F9/54
CPC Code(s): G06F9/52
Abstract: apparatuses, systems, and techniques to facilitate graph code synchronization between application programming interfaces. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to cause graph code to wait on a semaphore used by another api.
Inventor(s): David Anthony Fontaine of Mountain View CA (US) for nvidia corporation
IPC Code(s): G06F9/54, G06F8/30, G06F9/448
CPC Code(s): G06F9/54
Abstract: apparatuses, systems, and techniques to identify a location of one or more portions of incomplete graph code. in at least one embodiment, a location of one or more portions of incomplete graph code is identified based on, for example, cuda or other parallel computing platform code.
20240338358. CONCURRENT DATASET UPDATES USING HASH MAPS_simplified_abstract_(nvidia corporation)
Inventor(s): Pascal Gautron of Speracedes (FR) for nvidia corporation
IPC Code(s): G06F16/23, G06F9/46, G06F16/22, G06T15/06
CPC Code(s): G06F16/2379
Abstract: approaches in accordance with various embodiments can perform spatial hash map updates while ensuring the atomicity of the updates for arbitrary data structures. a hash map can be generated for a dataset where entries in the hash map may correspond to multiple independent values, such as pixels of an image to be rendered. update requests for independent values may be received on multiple concurrent threads, but change requests for independent values corresponding to a hash map entry can be aggregated from a buffer and processed iteratively in a single thread for a given hash map entry. in the case of multi-resolution spatial hashing where data can be stored at various discretization levels, this operation can be repeated to propagate changes from one level to another.
Inventor(s): Caelan Reed GARRETT of Seattle WA (US) for nvidia corporation, Fabio TOZETO RAMOS of Seattle WA (US) for nvidia corporation, Iretiayo AKINOLA of Seattle WA (US) for nvidia corporation, Alperen DEGIRMENCI of Jersey City NJ (US) for nvidia corporation, Clemens EPPNER of Seattle WA (US) for nvidia corporation, Dieter FOX of Seattle WA (US) for nvidia corporation, Tucker Ryer HERMANS of Salt Lake City UT (US) for nvidia corporation, Ajay Uday MANDLEKAR of Cupertino CA (US) for nvidia corporation, Arsalan MOUSAVIAN of Seattle WA (US) for nvidia corporation, Yashraj Shyam NARANG of Seattle WA (US) for nvidia corporation, Rowland Wilde O'FLAHERTY of Seattle WA (US) for nvidia corporation, Balakumar SUNDARALINGAM of Seattle WA (US) for nvidia corporation, Wei YANG of Lake Forest Park WA (US) for nvidia corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: one embodiment of a method for generating simulation data to train a machine learning model includes generating a plurality of simulation environments based on a user input, and for each simulation environment included in the plurality of simulation environments: generating a plurality of tasks for a robot to perform within the simulation environment, performing one or more operations to determine a plurality of robot trajectories for performing the plurality of tasks, and generating simulation data for training a machine learning model by performing one or more operations to simulate the robot moving within the simulation environment according to the plurality of trajectories.
Inventor(s): Donghoom LEE of Sunnyvale CA (US) for nvidia corporation, Sifei Liu of Santa Clara CA (US) for nvidia corporation, Jinwei Gu of San Jose CA (US) for nvidia corporation, Ming-Yu Liu of San Jose CA (US) for nvidia corporation, Jan Kautz of Lexington MA (US) for nvidia corporation
IPC Code(s): G06T11/60, G06F18/21, G06F18/24, G06T3/02, G06T7/30, G06T7/70, G06V30/262
CPC Code(s): G06T11/60
Abstract: one embodiment of a method includes applying a first generator model to a semantic representation of an image to generate an affine transformation, where the affine transformation represents a bounding box associated with at least one region within the image. the method further includes applying a second generator model to the affine transformation and the semantic representation to generate a shape of an object. the method further includes inserting the object into the image based on the bounding box and the shape.
20240338884. SHADOW DENOISING IN RAY-TRACING APPLICATIONS_simplified_abstract_(nvidia corporation)
Inventor(s): Shiqui Liu of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T15/06, G06T5/20, G06T5/70, G06T15/50, G06T15/60
CPC Code(s): G06T15/06
Abstract: in various examples, the actual spatial properties of a virtual environment are used to produce, for a pixel, an anisotropic filter kernel for a filter having dimensions and weights that accurately reflect the spatial characteristics of the virtual environment. geometry of the virtual environment may be computed based at least in part on a projection of a light source onto a surface through an occluder, in order to determine a footprint that reflects a contribution of the light source to lighting conditions of the pixel associated with a point on the surface. the footprint may define a size, orientation, and/or shape of the anisotropic filter kernel and corresponding filter weights. the anisotropic filter kernel may be applied to the pixel to produce a graphically-rendered image of the virtual environment.
Inventor(s): Davide Marco Onofrio of San Francisco CA (US) for nvidia corporation, Hae-Jong Seo of San Jose CA (US) for nvidia corporation, David Nister of Bellevue WA (US) for nvidia corporation, Minwoo Park of Saratoga CA (US) for nvidia corporation, Neda Cvijetic of East Palo Alto CA (US) for nvidia corporation
IPC Code(s): G08G1/16, G06F18/23, G06N3/08, G06V20/56
CPC Code(s): G08G1/167
Abstract: in various examples, a path perception ensemble is used to produce a more accurate and reliable understanding of a driving surface and/or a path there through. for example, an analysis of a plurality of path perception inputs provides testability and reliability for accurate and redundant lane mapping and/or path planning in real-time or near real-time. by incorporating a plurality of separate path perception computations, a means of metricizing path perception correctness, quality, and reliability is provided by analyzing whether and how much the individual path perception signals agree or disagree. by implementing this approach—where individual path perception inputs fail in almost independent ways—a system failure is less statistically likely. in addition, with diversity and redundancy in path perception, comfortable lane keeping on high curvature roads, under severe road conditions, and/or at complex intersections, as well as autonomous negotiation of turns at intersections, may be enabled.
Inventor(s): Kedar Rajpathak of Santa Clara CA (US) for nvidia corporation, Tezaswi Raja of Santa Clara CA (US) for nvidia corporation
IPC Code(s): H04L7/033, H04L7/00
CPC Code(s): H04L7/0331
Abstract: circuitry and method of operating a circuit for monitoring a clock signal having phase-to-phase variation is disclosed. the method comprises adding a fixed number of bits to a pulse count of a reference phase instance for a high or low phase to yield a modified added pulse count when detecting a clock slow abnormality, subtracting the fixed number of bits from the pulse count of the reference phase instance to yield a modified subtracted pulse count when detecting a clock fast abnormality, comparing the modified added pulse count to a pulse count for an immediately subsequent phase instance of the high or low phase count of the clock signal when detecting the clock slow abnormality, and comparing the modified subtracted pulse count to the pulse count for the immediately subsequent phase instance of the high phase or low phase count of the clock signal when detecting the clock fast abnormality.
Inventor(s): Vishnu Balan of Saratoga CA (US) for nvidia corporation, Viswanath Annampedu of Plano TX (US) for nvidia corporation, Pervez Mirzra Aziz of Dallas TX (US) for nvidia corporation
IPC Code(s): H04L25/03
CPC Code(s): H04L25/03057
Abstract: a receiver includes a partial response (pr) system that receives a received signal from a transmitter over a channel and equalize the received signal such that there is a controlled relationship between consecutive values of equalized received symbols and transmitted data transmitted by the transmitter. the receiver also includes a decision feed forward equalization (dffe) system that receives partial response signals from the pr system and cancel at least one of pre-cursor intersymbol interference (isi) or post-cursor isi introduced by the channel.
NVIDIA Corporation patent applications on October 10th, 2024
- NVIDIA Corporation
- B60W60/00
- B60W30/095
- CPC B60W60/00272
- Nvidia corporation
- G01R31/317
- G05B19/4155
- G06F1/14
- CPC G01R31/31727
- G06F7/24
- G06F7/483
- G06F7/78
- CPC G06F7/24
- G06F9/52
- G06F9/54
- CPC G06F9/52
- G06F9/38
- G06F9/48
- G06F9/50
- G06F8/30
- G06F9/448
- CPC G06F9/54
- G06F16/23
- G06F9/46
- G06F16/22
- G06T15/06
- CPC G06F16/2379
- G06N20/00
- CPC G06N20/00
- G06T11/60
- G06F18/21
- G06F18/24
- G06T3/02
- G06T7/30
- G06T7/70
- G06V30/262
- CPC G06T11/60
- G06T5/20
- G06T5/70
- G06T15/50
- G06T15/60
- CPC G06T15/06
- G08G1/16
- G06F18/23
- G06N3/08
- G06V20/56
- CPC G08G1/167
- H04L7/033
- H04L7/00
- CPC H04L7/0331
- H04L25/03
- CPC H04L25/03057
