NVIDIA Corporation patent applications on May 30th, 2024
Patent Applications by NVIDIA Corporation on May 30th, 2024
NVIDIA Corporation: 17 patent applications
NVIDIA Corporation has applied for patents in the areas of G06T15/00 (4), G06F9/54 (4), G01S15/931 (4), G01S15/86 (4), G06F3/06 (3)
With keywords such as: data, systems, perform, generated, circuit, techniques, within, examples, input, and memory in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Stephen Holmes of Fort Collins CO (US) for nvidia corporation, Pierre Gervais of Blainville (CA) for nvidia corporation
IPC Code(s): A63F13/86, A63F13/355, A63F13/537
Abstract: in various examples, compute resources may be allocated for highlight generation in cloud gaming systems. systems and methods are disclosed that distribute, between and among various devices, processing including user interface generation and overlay, analysis of game streams for actionable events, generation of highlights, storage of highlights, and sharing of highlights. the distribution of processing or compute resources within the cloud gaming system may be dependent on system information of various devices and/or networks. recordings, snapshots, and/or other highlights may be generated within the cloud gaming system using the determined distribution of compute resources.
Inventor(s): David Nister of Bellevue WA (US) for nvidia corporation, Hon-Leung Lee of Bellevue WA (US) for nvidia corporation, Julia Ng of San Jose CA (US) for nvidia corporation, Yizhou Wang of Santa Clara CA (US) for nvidia corporation
IPC Code(s): B60W30/09, B60W30/095
Abstract: in various examples, a current claimed set of points representative of a volume in an environment occupied by a vehicle at a time may be determined. a vehicle-occupied trajectory and at least one object-occupied trajectory may be generated at the time. an intersection between the vehicle-occupied trajectory and an object-occupied trajectory may be determined based at least in part on comparing the vehicle-occupied trajectory to the object-occupied trajectory. based on the intersection, the vehicle may then execute the first safety procedure or an alternative procedure that, when implemented by the vehicle when the object implements the second safety procedure, is determined to have a lesser likelihood of incurring a collision between the vehicle and the object than the first safety procedure.
Inventor(s): David Weikersdorfer of Moutain View CA (US) for nvidia corporation, Qian Lin of Berkeley CA (US) for nvidia corporation, Aman Jhunjhunwala of Toronto (CA) for nvidia corporation, Emilie Lucie Eloïse Wirbel of Nogent-sur-Marne (FR) for nvidia corporation, Sangmin Oh of San Jose CA (US) for nvidia corporation, Minwoo Park of Saratoga CA (US) for nvidia corporation, Gyeong Woo Cheon of San Jose CA (US) for nvidia corporation, Arthur Henry Rajala of Greenville OH (US) for nvidia corporation, Bor-Jeng Chen of San Jose CA (US) for nvidia corporation
IPC Code(s): G01S15/931, G01S15/86
Abstract: in various examples, techniques for sensor-fusion based object detection and/or free-space detection using ultrasonic sensors are described. systems may receive sensor data generated using one or more types of sensors of a machine. in some examples, the systems may then process at least a portion of the sensor data to generate input data, where the input data represents one or more locations of one or more objects within an environment. the systems may then input at least a portion of the sensor data and/or at least a portion of the input data into one or more neural networks that are trained to output one or more maps or other output representations associated with the environment. in some examples, the map(s) may include a height, an occupancy, and/or height/occupancy map generated, e.g., from a birds-eye-view perspective. the machine may use these outputs to perform one or more operations.
Inventor(s): David Weikersdorfer of Mountain View CA (US) for nvidia corporation, Qian Lin of Berkeley CA (US) for nvidia corporation, Aman Jhunjhunwala of Toronto (CA) for nvidia corporation, Emilie Lucie Eloïse Wirbel of Nogent-su-Marne (FR) for nvidia corporation, Sangmin Oh of San Jose CA (US) for nvidia corporation, Minwoo Park of Saratoga CA (US) for nvidia corporation, Gyeong Woo Cheon of San Jose CA (US) for nvidia corporation, Arthur Henry Rajala of Greenville OH (US) for nvidia corporation, Bor-Jeng Chen of San Jose CA (US) for nvidia corporation
IPC Code(s): G01S15/931, G01S15/86
Abstract: in various examples, techniques for sensor-fusion based object detection and/or free-space detection using ultrasonic sensors are described. systems may receive sensor data generated using one or more types of sensors of a machine. in some examples, the systems may then process at least a portion of the sensor data to generate input data, where the input data represents one or more locations of one or more objects within an environment. the systems may then input at least a portion of the sensor data and/or at least a portion of the input data into one or more neural networks that are trained to output one or more maps or other output representations associated with the environment. in some examples, the map(s) may include a height, an occupancy, and/or height/occupancy map generated, e.g., from a birds-eye-view perspective. the machine may use these outputs to perform one or more operations
Inventor(s): Harold Carter Edwards of Campbell CA (US) for nvidia corporation, Olivier Giroux of Santa Clara CA (US) for nvidia corporation, Jack H. Choquette of Palo Alto CA (US) for nvidia corporation, Gokul Ramaswamy Hirisave Chandra Shekhara of Bangalore (IN) for nvidia corporation, Rui Guo of Shanghai (CN) for nvidia corporation, Chao Li of Austin TX (US) for nvidia corporation, Vishalkumar Ketankumar Mehta of Stäfa (CH) for nvidia corporation, David Dastous St. Hilaire of Lake Stevens WA (US) for nvidia corporation, Aditya Avinash Atluri of Redmond WA (US) for nvidia corporation, Apoorv Parle of San Jose CA (US) for nvidia corporation, Ronny Meir Krashinsky of Portola Valley CA (US) for nvidia corporation, Subhasmita Chakraborty of Austin TX (US) for nvidia corporation, Vikram Dhar of Campbell CA (US) for nvidia corporation
IPC Code(s): G06F3/06
Abstract: apparatuses, systems, and techniques to provide memory transaction information. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to cause information about one or more memory transactions to be provided to one or more users.
Inventor(s): Harold Carter Edwards of Campbell CA (US) for nvidia corporation, Olivier Giroux of Santa Clara CA (US) for nvidia corporation, Jack H. Choquette of Palo Alto CA (US) for nvidia corporation, Gokul Ramaswamy Hirisave Chandra Shekhara of Bangalore (IN) for nvidia corporation, Rui Guo of Shanghai (CN) for nvidia corporation, Chao Li of Austin TX (US) for nvidia corporation, Vishalkumar Ketankumar Mehta of Stafa (CH) for nvidia corporation, David Dastous St. Hilaire of Lake Stevens WA (US) for nvidia corporation, Aditya Avinash Atluri of Redmond WA (US) for nvidia corporation, Apoorv Parle of San Jose CA (US) for nvidia corporation, Ronny Meir Krashinsky of Portola Valley CA (US) for nvidia corporation, Subhasmita Chakraborty of Austin TX (US) for nvidia corporation, Vikram Dhar of Campbell CA (US) for nvidia corporation
IPC Code(s): G06F3/06
Abstract: apparatuses, systems, and techniques to check memory transaction information. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to check for information provided in a token by one or more users about one or more memory transactions after a first amount of time indicated by one or more users.
Inventor(s): Stephen David GLASER of San Francisco CA (US) for nvidia corporation
IPC Code(s): G06F3/06
Abstract: a method, computer program product, apparatus, and system are provided. some embodiments may include transmitting a request to make one or more writes associated with an identification tag. the request may include the identification tag, the one or more writes, a first instruction to make the one or more writes to one of a plurality of persistence levels of a memory, and a second instruction to respond with at least one first indication that the one or more writes associated with the identification tag have been written to at least one of the one of the plurality of persistence levels of the memory. some embodiments may include receiving the at least one first indication that the one or more writes associated with the identification tag have been written to at least one of the one of the plurality of persistence levels of the memory.
Inventor(s): Karthik Raghavan Ravi of Bangalore (IN) for nvidia corporation, Ashutosh Jain of Bengaluru (IN) for nvidia corporation, Rahul Suresh of Bangalore (IN) for nvidia corporation
IPC Code(s): G06F9/38, G06F9/54
Abstract: apparatuses, systems, and techniques to execute one or more application programming interfaces (apis) to perform one or more operations for one or more accelerators within a heterogeneous processor. in at least one embodiment, one or more processors are to perform one or more instructions in response to one or more apis to indicate one or more functions to be performed in response to one or more errors from one or more accelerators within a heterogeneous processor.
20240176663.TENSOR MAP CACHE STORAGE_simplified_abstract_(nvidia corporation)
Inventor(s): Gokul Ramaswamy HIRISAVE CHANDRA SHEKHARA of Bangalore (IN) for nvidia corporation, Alexander Lev Minkin of Los Altos CA (US) for nvidia corporation, Harold Carter Edwards of Campbell CA (US) for nvidia corporation, Yashwardhan Narawane of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F9/50, G06F12/0802
Abstract: apparatuses, systems, and techniques to store one or more tensor maps in one or more cache storages. in at least one embodiment, a processor includes one or more tensor acceleration logic circuits to cause one or more tensor maps to be stored in one or more cache storages.
Inventor(s): Karthik Raghavan Ravi of Bangalore (IN) for nvidia corporation, Ashutosh Jain of Bengaluru (IN) for nvidia corporation, Rahul Suresh of Bangalore (IN) for nvidia corporation
IPC Code(s): G06F9/54
Abstract: apparatuses, systems, and techniques to execute one or more application programming interfaces (apis) to perform one or more operations for one or more accelerators within a heterogeneous processor. in at least one embodiment, one or more processors are to perform one or more instructions in response to one or more apis to indicate one or more operations in a sequence of operations to be performed by one or more accelerators within a heterogeneous processor.
Inventor(s): Karthik Raghavan Ravi of Bangalore (IN) for nvidia corporation, Ashutosh Jain of Bengaluru (IN) for nvidia corporation, Rahul Suresh of Bangalore (IN) for nvidia corporation
IPC Code(s): G06F9/54
Abstract: apparatuses, systems, and techniques to execute one or more application programming interfaces (apis) to perform one or more operations for one or more accelerators within a heterogeneous processor. in at least one embodiment, one or more processors are to perform one or more instructions in response to one or more apis to indicate one or more memory regions to store error information from one or more accelerators within a heterogeneous processor.
Inventor(s): Karthik Raghavan Ravi of Bangalore (IN) for nvidia corporation, Ashutosh Jain of Bengaluru (IN) for nvidia corporation, Rahul Suresh of Bangalore (IN) for nvidia corporation
IPC Code(s): G06F9/54
Abstract: apparatuses, systems, and techniques to execute one or more application programming interfaces (apis) to perform one or more operations for one or more accelerators within a heterogeneous processor. in at least one embodiment, one or more processors are to perform one or more instructions in response to one or more apis to transfer information between memory of two or more accelerators.
Inventor(s): Shubhadeep Das of Kolkata (IN) for nvidia corporation, Sumit Kumar Bhattacharya of Pune (IN) for nvidia corporation, Oluwatobi Olabiyi of Falls Church VA (US) for nvidia corporation
IPC Code(s): G06F16/33, G06F16/338
Abstract: in various examples, contextual data may be generated using structured and unstructured data for conversational ai systems and applications. systems and methods are disclosed that use structured data (converted to unstructured form) and unstructured data, such as from a knowledge database(s), to generate contextual data. for instance, the contextual data may represent text (e.g., narratives), where a first portion of the text is generated using the structured data and a second portion of the text is generated using the unstructured data. the systems and methods may then use a neural network(s), such as a neural network(s) associated with a dialogue manager, to process input data representing a request (e.g., a query) and the contextual data in order to generate a response to the request. for instance, if the request includes a query for information associated with a topic, the neural network(s) may generate a response that includes the requested information.
Inventor(s): Matthew JONES of Longmont CO (US) for nvidia corporation
IPC Code(s): G06N10/20
Abstract: in various examples, systems and methods for simulation of quantum computing circuits using kronecker factorization are provided. a partitioned quantum computing circuit may be generated by partitioning the quantum computing circuit using at least one partition boundary with respect to its state vector, to subdivide the quantum computing circuit into a plurality of circuit partitions. circuit instances may be generated for the circuit partitions, where at least one circuit partition comprises a circuit instance that includes at least one operator derived from a kronecker factorization that corresponds to a quantum operator that operates using qudits from more than one of the circuit partitions. a representation of at least a component of a state of the state vector for the quantum computing circuit may be generated based at least on simulating the at least one circuit instance for the circuit partitions.
Inventor(s): Adithyavairavan Murali of Seattle WA (US) for nvidia corporation, Arsalan Mousavian of Seattle WA (US) for nvidia corporation, Clemens Eppner of Seattle WA (US) for nvidia corporation, Adam Fishman of Seattle WA (US) for nvidia corporation, Dieter Fox of Seattle WA (US) for nvidia corporation
IPC Code(s): G06T15/00, B25J9/16, G06T9/00
Abstract: one common robotic task is the rearrangement of physical objects situated in an environment. this typically involves a robot manipulator picking up a target object and placing the target object in some target location, such as a shelf, cabinet or cubby, and requires the skills of picking, placing and generating complex collision-free motions, oftentimes in a cluttered environment. the present disclosure provides collision detection for object rearrangement using a three-dimensional (3d) scene representation.
Inventor(s): Pawel Kozlowski of Truckee CA (US) for nvidia corporation, Maksim Aizenshtein of Sammamish WA (US) for nvidia corporation
IPC Code(s): G06T15/00, G06T5/70, G06T7/20, G06T7/70
Abstract: systems and methods relate to the determination of accurate motion vectors, for rendering situations such as a noisy monte carlo integration where image object surfaces are at least partially translucent. to optimize the search for “real world” positions, this invention defines the background as first path vertices visible through multiple layers of refractive interfaces. to find matching world positions, the background is treated as a single layer morphing in a chaotic way, permitting the optimized algorithm to be executed only once. further improving performance over the prior linear gradient descent, the present techniques can apply a cross function and numerical optimization, such as newton's quadratic target or other convergence function, to locate pixels via a vector angle minimization. determined motion vectors can then serve as input for services including image denoising.
Inventor(s): James Hansen Delfeld of Austin TX (US) for nvidia corporation
IPC Code(s): H04L25/02
Abstract: apparatuses, systems, and techniques to estimate one or more wireless channels between one or more user devices and a base station. in at least one embodiment, one or more circuits use one or more groups of two or more reflected wireless reference signals to estimate the one or more wireless channels based, at least in part, on one or more bandlimited functions.
