NVIDIA Corporation patent applications on March 28th, 2024
Patent Applications by NVIDIA Corporation on March 28th, 2024
NVIDIA Corporation: 20 patent applications
NVIDIA Corporation has applied for patents in the areas of G06T1/20 (6), G06T17/10 (4), G06N3/08 (4), G06T7/70 (4), G06V10/82 (4)
With keywords such as: techniques, image, mesh, coordinate, logic, based, error, embodiment, network, and systems in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Ankur HANDA of Seattle WA (US) for nvidia corporation, Gavriel STATE of Toronto (CA) for nvidia corporation, Arthur David ALLSHIRE of Toronto (CA) for nvidia corporation, Victor MAKOVIICHUK of Santa Clara CA (US) for nvidia corporation, Aleksei Vladimirovich PETRENKO of Cupertino CA (US) for nvidia corporation
IPC Code(s): B25J9/16
Abstract: systems techniques to control a robot are described herein. in at least one embodiment, a machine learning model for controlling a robot is trained based at least on one or more population-based training operations or one or more reinforcement learning operations. once trained, the machine learning model can be deployed and used to control a robot to perform a task.
Inventor(s): Sayed Mehdi Sajjadi Mohammadabadi of Santa Clara CA (US) for nvidia corporation, Berta Rodriguez Hervas of Santa Clara CA (US) for nvidia corporation, Hang Dou of Fremont CA (US) for nvidia corporation, Igor Tryndin of Fremont CA (US) for nvidia corporation, David Nister of Belleview WA (US) for nvidia corporation, Minwoo Park of Saratoga CA (US) for nvidia corporation, Neda Cvijetic of East Palo Alto CA (US) for nvidia corporation, Junghyun Kwon of San Jose CA (US) for nvidia corporation, Trung Pham of Santa Clara CA (US) for nvidia corporation
IPC Code(s): B60W30/18, B60W30/09, B60W30/095, B60W60/00, G06N3/08, G06V10/25, G06V10/75, G06V10/764, G06V10/80, G06V10/82, G06V20/56, G06V20/70, G08G1/01
Abstract: in various examples, live perception from sensors of a vehicle may be leveraged to detect and classify intersections in an environment of a vehicle in real-time or near real-time. for example, a deep neural network (dnn) may be trained to compute various outputs—such as bounding box coordinates for intersections, intersection coverage maps corresponding to the bounding boxes, intersection attributes, distances to intersections, and/or distance coverage maps associated with the intersections. the outputs may be decoded and/or post-processed to determine final locations of, distances to, and/or attributes of the detected intersections.
20240103437.HOLOGRAPHIC VOLUMETRIC DISPLAYS_simplified_abstract_(nvidia corporation)
Inventor(s): Jonghyun KIM of San Francisco CA (US) for nvidia corporation, Ward LOPES of San Jose CA (US) for nvidia corporation, David LUEBKE of Charlottesville VA (US) for nvidia corporation
IPC Code(s): G03H1/00, G03H1/12
Abstract: one embodiment of a display system includes one or more light sources, one or more spatial light modulators, and a plurality of scatterers. one embodiment of a method for displaying content includes computing at least one of a phase or an amplitude modulation associated with two-dimensional (2d) or three-dimensional (3d) content, and causing one or more spatial light modulators to modulate light based on the at least one of a phase or an amplitude modulation to generate modulated light, where the modulated light is scattered by a plurality of scatterers.
Inventor(s): Adithya Hrudhayan Krishnamurthy of Sunnyvale CA (US) for nvidia corporation, Ish Chadha of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F11/07, G06F11/16
Abstract: a receiver device includes detection logic, error counter logic, and threshold logic. the detection detects frame errors in data frames received by a transmitter device. the error counter logic increments a first value of an error count responsive to each error signal, indicative of a frame error in a data frame, received from the detection logic. the error counter logic reduces the first value to a second value (non-zero value) for the error count responsive to receiving a decrement signal and a period marker signal corresponding to a programmable period. the error counter logic resets the first value or the second value of the error count to zero responsive to receiving a reset signal. the threshold logic compares a current value of the error count with a threshold number of frame errors and output an interrupt responsive to the current value satisfying the threshold number of frame errors.
Inventor(s): Kedar Rajpathak of Bengaluru (IN) for nvidia corporation, Tezaswi Raja of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06F21/75, G06F21/52
Abstract: techniques are described for detecting an electromagnetic (“em”) fault injection attack directed toward circuitry in a target digital system. in various embodiments, a first node may be coupled to first driving circuitry, and a second node may be coupled to second driving circuitry. the driving circuitry is implemented in a manner such that a logic state on the second node has greater sensitivity to an em pulse than has a logic state on the first node. comparison circuitry may be coupled to the first and to the second nodes to assert an attack detection output responsive to sensing a logic state on the second node that is unexpected relative to a logic state on the first node.
Inventor(s): Rongjian LIANG of Austin TX (US) for nvidia corporation, Haoxing REN of Austin TX (US) for nvidia corporation
IPC Code(s): G06F30/392
Abstract: techniques are disclosed herein for designing a circuit. the techniques include receiving a specification for a driver and a plurality of sinks; executing, based on the driver and the plurality of sinks, a machine learning model that predicts at least one of a size, a location, or a delay target of one or more buffers; generating a tree that includes a plurality of nodes representing the driver, the plurality of sinks, and the one or more buffers between the driver and one or more of the sinks; and generating a design of a circuit based on the tree.
20240104345.NEURAL NETWORK ARCHITECTURE SELECTION_simplified_abstract_(nvidia corporation)
Inventor(s): Cheng Peng of Cockeysville MD (US) for nvidia corporation, Andriy Myronenko of San Francisco CA (US) for nvidia corporation, Ali Hatamizsadeh of Los Angeles CA (US) for nvidia corporation, Vishwesh Nath of Nashville TN (US) for nvidia corporation, Md Mahfuzur Rahman Siddiquee of Tempe AZ (US) for nvidia corporation, Yufan He of Philadelphia PA (US) for nvidia corporation, Daguang Xu of Potomac MD (US) for nvidia corporation, Dong Yang of Pocatello ID (US) for nvidia corporation
IPC Code(s): G06N3/04, G06N3/08, G16H30/20
Abstract: apparatuses, systems, and techniques are presented to generate images representing realistic motion or activity. in at least one embodiment, one or more neural networks are used to select a first neural network to perform a first task based, at least in part, upon a performance estimated by a second neural network.
Inventor(s): Robert Thomas Pottorff of Layton UT (US) for nvidia corporation, Karan Sapra of San Jose CA (US) for nvidia corporation, Andrew Leighton Edelsten of Morgan Hill CA (US) for nvidia corporation
IPC Code(s): G06T3/40, G06T1/20
Abstract: apparatuses, systems, and techniques to process image frames. in at least one embodiment, an application programming interface (api) is performed to enable frame interpolation to use one or more neural networks.
Inventor(s): Robert Thomas Pottorff of Layton UT (US) for nvidia corporation, Karan Sapra of San Jose CA (US) for nvidia corporation, Andrew Leighton Edelsten of Morgan Hill CA (US) for nvidia corporation
IPC Code(s): G06T3/40
Abstract: apparatuses, systems, and techniques to process image frames. in at least one embodiment, an application programming interface (api) is performed to indicate frame size information using one or more neural networks.
Inventor(s): Robert Thomas Pottorff of Layton UT (US) for nvidia corporation, Karan Sapra of San Jose CA (US) for nvidia corporation, Andrew Leighton Edelsten of Morgan Hill CA (US) for nvidia corporation
IPC Code(s): G06T3/40, G06T1/20
Abstract: apparatuses, systems, and techniques to process image frames. in at least one embodiment, an application programming interface (api) is performed to indicate support to use one or more neural networks to perform frame interpolation.
20240104698.NEURAL NETWORK-BASED PERTURBATION REMOVAL_simplified_abstract_(nvidia corporation)
Inventor(s): Weili Nie of Sunnyvale CA (US) for nvidia corporation, Yujia Huang of Pasadena CA (US) for nvidia corporation, Chaowei Xiao of Seattle WA (US) for nvidia corporation, Arash Vahdat of Mountain View CA (US) for nvidia corporation, Anima Anandkumar of Pasadena CA (US) for nvidia corporation
IPC Code(s): G06T5/00, G06N3/04, G06T5/50
Abstract: apparatuses, systems, and techniques are presented to remove unintended variations introduced into data. in at least one embodiment, a first image of an object can be generated based, at least in part, upon adding noise to, and removing the noise from, a second image of the object.
20240104790.OPTIMIZING GRID-BASED COMPUTE GRAPHS_simplified_abstract_(nvidia corporation)
Inventor(s): Shekhar Dwivedi of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T11/00, G06T1/20, G06T1/60
Abstract: disclosed are apparatuses, systems, and techniques that enable compressed grid-based graph representations for efficient implementations of graph-mapped computing applications. the techniques include but are not limited to selecting a reference grid having a plurality of blocks, assigning nodes of the graph to blocks of the grid, and generating a graph representation that maps directions, relative to the reference grid, of nodal connections of the graph.
Inventor(s): Gregory MUTHLER of Austin TX (US) for nvidia corporation, John BURGESS of Austin TX (US) for nvidia corporation, Ronald Charles BABICH, JR. of Murrysville CA (US) for nvidia corporation, William Parsons Newhall, JR. of Woodside CA (US) for nvidia corporation
IPC Code(s): G06T15/06, G06F9/48, G06F9/50, G06T17/10
Abstract: techniques are disclosed for improving the throughput of ray intersection or visibility queries performed by a ray tracing hardware accelerator. throughput is improved, for example, by releasing allocated resources before ray visibility query results are reported by the hardware accelerator. the allocated resources are released when the ray visibility query results can be stored in a compressed format outside of the allocated resources. when reporting the ray visibility query results, the results are reconstructed based on the results stored in the compressed format. the compressed format storage can be used for ray visibility queries that return no intersections or terminate on any hit ray visibility query. one or more individual components of allocated resources can also be independently deallocated based on the type of data to be returned and/or results of the ray visibility query.
Inventor(s): Yen-Chen LIN of Cambridge MA (US) for nvidia corporation, Valts BLUKIS of Kirkland WA (US) for nvidia corporation, Dieter FOX of Seattle WA (US) for nvidia corporation, Alexander KELLER of Berlin (DE) for nvidia corporation, Thomas MUELLER-HOEHNE of Zurich (CH) for nvidia corporation, Jonathan TREMBLAY of Redmond WA (US) for nvidia corporation
IPC Code(s): G06T15/20, G06T7/55, G06T15/00
Abstract: one embodiment of a method for generating representations of scenes includes assigning each image included in a set of images of a scene to one or more clusters of images based on a camera pose associated with the image, and performing one or more operations to generate, for each cluster included in the one or more clusters, a corresponding three-dimensional (3d) representation of the scene based on one or more images assigned to the cluster.
Inventor(s): Koki Nagano of Playa Vista CA (US) for nvidia corporation, Alexander Trevithick of Mamaroneck NY (US) for nvidia corporation, Chao Liu of Pittsburgh PA (US) for nvidia corporation, Eric Ryan Chan of Alameda CA (US) for nvidia corporation, Sameh Khamis of Alameda CA (US) for nvidia corporation, Michael Stengel of Hayward CA (US) for nvidia corporation, Zhiding Yu of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T17/00, G06T5/20, G06T7/70, G06T7/90, G06V10/771
Abstract: a method for generating, by an encoder-based model, a three-dimensional (3d) representation of a two-dimensional (2d) image is provided. the encoder-based model is trained to infer the 3d representation using a synthetic training data set generated by a pre-trained model. the pre-trained model is a 3d generative model that produces a 3d representation and a corresponding 2d rendering, which can be used to train a separate encoder-based model for downstream tasks like estimating a triplane representation, neural radiance field, mesh, depth map, 3d key points, or the like, given a single input image, using the pseudo ground truth 3d synthetic training data set. in a particular embodiment, the encoder-based model is trained to predict a triplane representation of the input image, which can then be rendered by a volume renderer according to pose information to generate an output image of the 3d scene from the corresponding viewpoint.
Inventor(s): Pascal GAUTRON of Speracedes (FR) for nvidia corporation, Christoph KUBISCH of Aachen (DE) for nvidia corporation
IPC Code(s): G06T17/20, G06T1/60
Abstract: various embodiments include techniques for generating topological data for a mesh included in a computer-generated environment. the mesh includes simple geometric shapes, such as triangles. the disclosed techniques identify vertices in the mesh that have the same position and have identical attributes, such as color, normal vector, and texture coordinates. the disclosed techniques further identify vertices in the mesh that have the same position but differ in one or more attributes. the techniques generate lists of the triangles that are adjacent to each vertex included in the mesh. the techniques generate a list of the unique edges included in the mesh. further, the techniques are well suited for execution on highly parallel processors, such as graphics processing units, thereby reducing the time to generate this topological data. the topological data may then be efficiently used by other computer graphics processing operations.
Inventor(s): Pascal GAUTRON of Speracedes (FR) for nvidia corporation, Christoph KUBISCH of Aachen (DE) for nvidia corporation
IPC Code(s): G06T17/20, G06T17/10
Abstract: various embodiments include techniques for performing parallel edge decimation on a high resolution mesh by collapsing multiple edges in parallel by blocking only the neighbor edges of the edges selected as collapse candidates. effectively, the disclosed techniques dynamically partition the mesh into small partitions around the collapse candidates. in this manner, the techniques identify all the edges that may be independently collapsed in a single, now parallel, iteration. edge decimation may be performed so that certain computational geometry techniques can be efficiently applied to a simpler mesh. in so doing, the disclosed techniques preserve the history of how the edge decimation process displaces the vertices of the original mesh to generate the simplified mesh. as a result, the results of the computational geometry techniques as applied to the simplified mesh can be propagated back to the original mesh.
Inventor(s): Hairong JIANG of Campbell CA (US) for nvidia corporation, Yuzhuo REN of Sunnyvale CA (US) for nvidia corporation, Nitin BHARADWAJ of Cupertino CA (US) for nvidia corporation, Chun-Wei CHEN of San Jose CA (US) for nvidia corporation, Varsha Chandrashekhar HEDAU of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G06V10/24, B60W40/02, G06T3/60, G06T7/20, H04N13/246
Abstract: in various examples, calibration techniques for interior depth sensors and image sensors for in-cabin monitoring systems and applications are provided. an intermediary coordinate system may be generated using calibration targets distributed within an interior space to reference 3d positions of features detected by both depth-perception and optical image sensors. rotation-translation transforms may be determined to compute a first transform (h1) between the depth-perception sensor's 3d coordinate system and the 3d intermediary coordinate system, and a second transform (h2) between the optical image sensor's 2d coordinate system and the intermediary coordinate system. a third transform (h3) between the depth-perception sensor's 3d coordinate system and the optical image sensor's 2d coordinate system can be computed as a function of h1 and h2. the calibration targets may comprise a structural substrate that includes one or more fiducial point markers and one or more motion targets.
Inventor(s): Yuzhuo REN of Sunnyvale CA (US) for nvidia corporation, Hairong JIANG of Campbell CA (US) for nvidia corporation, Niranjan AVADHANAM of Saratoga CA (US) for nvidia corporation, Varsha Chandrashekhar HEDAU of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G06V20/59, G06F3/01, G06T3/20, G06T3/60, G06T7/70, G06T7/80, G06V10/82
Abstract: in various examples, sensor parameter calibration techniques for in-cabin monitoring systems and applications are presented. an occupant monitoring system (oms) is an example of a system that may be used within a vehicle or machine cabin to perform real-time assessments of driver and occupant presence, gaze, alertness, and/or other conditions. in some embodiments, a calibration parameter for an interior image sensor is determined so that the coordinates of features detected in 2d captured images may be referenced to an in-cabin 3d coordinate system. in some embodiments, a processing unit may detect fiducial points using an image of an interior space captured by a sensor, determine a 2d image coordinate for a fiducial point using the image, determine a 3d coordinate for the fiducial point, determine a calibration parameter comprising a rotation-translation transform from the 2d image coordinate and the 3d coordinate, and configure an operation based on the calibration parameter.
Inventor(s): Ajay Anil Thorve of Maple Valley WA (US) for nvidia corporation, Allan Enemark of Santa Cruz CA (US) for nvidia corporation, Rachel Allen of Arlington VA (US) for nvidia corporation, Bartley Richardson of Alexandria VA (US) for nvidia corporation
IPC Code(s): H04L9/40, G06F3/04845
Abstract: technologies for generating a graphical user interface (gui) dashboard with a three-dimensional (3d) grid of unit cells are described. an anomaly statistic can be determined for a set of records. a subset of network address identifiers can be identified and sorted according to the anomaly statistic. the subset can have higher anomaly statistics than other network address identifiers. there can be a maximum number in the subset. the gui dashboard is generated with unit cells organized by the subset of network address identifiers as rows, time intervals as columns, colors as a configurable anomaly score indicator, and a number of network access events as column heights. each unit cell is a colored, 3d visual object representing a composite score of anomaly scores associated with zero or more network access events corresponding to the respective network address identifier at the respective time interval. the gui dashboard is rendered on a display.
- NVIDIA Corporation
- B25J9/16
- Nvidia corporation
- B60W30/18
- B60W30/09
- B60W30/095
- B60W60/00
- G06N3/08
- G06V10/25
- G06V10/75
- G06V10/764
- G06V10/80
- G06V10/82
- G06V20/56
- G06V20/70
- G08G1/01
- G03H1/00
- G03H1/12
- G06F11/07
- G06F11/16
- G06F21/75
- G06F21/52
- G06F30/392
- G06N3/04
- G16H30/20
- G06T3/40
- G06T1/20
- G06T5/00
- G06T5/50
- G06T11/00
- G06T1/60
- G06T15/06
- G06F9/48
- G06F9/50
- G06T17/10
- G06T15/20
- G06T7/55
- G06T15/00
- G06T17/00
- G06T5/20
- G06T7/70
- G06T7/90
- G06V10/771
- G06T17/20
- G06V10/24
- B60W40/02
- G06T3/60
- G06T7/20
- H04N13/246
- G06V20/59
- G06F3/01
- G06T3/20
- G06T7/80
- H04L9/40
- G06F3/04845
