NVIDIA Corporation patent applications on March 27th, 2025
Patent Applications by NVIDIA Corporation on March 27th, 2025
NVIDIA Corporation: 23 patent applications
NVIDIA Corporation has applied for patents in the areas of G06T15/06 (4), G06T15/00 (3), G06T5/00 (2), B60W60/00 (2), G06N3/04 (2) G06T15/06 (4), B60W60/001 (1), G06T3/4046 (1), H04N7/0137 (1), H04B10/40 (1)
With keywords such as: data, based, network, video, used, shader, ray, vehicle, embodiment, and optical in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Akash CHANDRA SHEKAR of Redmond WA US for nvidia corporation, Andy CAMPBELL of Kirkland WA US for nvidia corporation, Matthew ASHMAN of Redmond WA US for nvidia corporation, Russell CHREPTYK of Seattle WA US for nvidia corporation, Tharun BATTULA of Redmond WA US for nvidia corporation, Vaibhav THUKRAL of Bellevue WA US for nvidia corporation, Wei WANG of Bothell WA US for nvidia corporation
IPC Code(s): B60W60/00, B60W30/095, B60W30/18
CPC Code(s): B60W60/001
Abstract: embodiments of the present disclosure relate to performing navigation operations based on junction area information digested at runtime of one or more systems of a machine. in some embodiments, the junction area information may be encoded in map data corresponding to a map, and the encoding may include organizing vehicle paths that traverse through a junction area according to path groups and organizing contentions that influence behavior of vehicles traveling along the vehicle paths according to contention groups. in addition, the encoding may include generating direction data structures that associate respective path groups with one or more of the contention groups. in these or other embodiments, the map data that corresponds to the junction area may be updated with direction data structures.
Inventor(s): Birgit Henke of Seattle WA US for nvidia corporation, David Nister of Bellevue WA US for nvidia corporation, Julia Ng of San Jose CA US for nvidia corporation
IPC Code(s): B60W60/00
CPC Code(s): B60W60/0011
Abstract: a trajectory for an autonomous machine may be evaluated for safety based at least on determining whether the autonomous machine would be capable of occupying points of the trajectory in space-time while still being able to avoid a potential future collision with one or more objects in the environment through use of one or more safety procedures. to do so, a point of the trajectory may be evaluated for conflict based at least on a comparison between points in space-time that correspond to the autonomous machine executing the safety procedure(s) from the point and arrival times of the one or more objects to corresponding position(s) in the environment. a trajectory may be sampled and evaluated for conflicts at various points throughout the trajectory. based on results of one or more evaluations, the trajectory may be scored, eliminated from consideration, or otherwise considered for control of the autonomous machine.
20250103049. QUANTIZING AUTOENCODERS IN A NEURAL NETWORK_simplified_abstract_(nvidia corporation)
Inventor(s): Jon Hasselgren of Bunkeflostrand SE for nvidia corporation, Jacob Munkberg of Skane SE for nvidia corporation
IPC Code(s): G05D1/00, G05B13/02, G05D1/227, G05D1/249, G06N3/02, G06N3/04, G06N3/043, G06N3/045, G06N3/088
CPC Code(s): G05D1/0231
Abstract: the performance of a neural network is improved by applying quantization to data at various points in the network. in an embodiment, a neural network includes two paths. a quantization is applied to each path, such that when an output from each path is combined, further quantization is not required. in an embodiment, the neural network is an autoencoder that includes at least one skip connection. in an embodiment, the system determines a set of quantization parameters based on the characteristics of the data in the primary path and in the skip connection, such that both network paths produce output data in the same fixed point format. as a result, the data from both network paths can be combined without requiring an additional quantization.
20250103076. CLOCK TO ANALOG REFERENCE VOLTAGE GENERATOR_simplified_abstract_(nvidia corporation)
Inventor(s): Siddharth Saxena of San Jose CA US for nvidia corporation, Sudhir Shrikantha Kudva of Dublin CA US for nvidia corporation, Miguel Rodriguez of Golden CO US for nvidia corporation, Vijay Srinivasan of San Francisco CA US for nvidia corporation, Tezaswi Raja of San Jose CA US for nvidia corporation, Tom Gray of Apex NC US for nvidia corporation, Santosh Santosh of Los Gatos CA US for nvidia corporation
IPC Code(s): G05F1/56, G04F10/00, H03M7/16
CPC Code(s): G05F1/56
Abstract: reference voltage generators including a header circuit configured to pass current from a power supply to a time-to-digital converter, an amount of the current to pass determined by a thermometer code, and logic to update the thermometer code based on a comparison between an output of the time-to-digital converter and a digital code representing a reference voltage level.
Inventor(s): Michael Oxford of San Jose CA US for nvidia corporation, Patrick Neill of Sherwood OR US for nvidia corporation, Franck Diard of Roquefort les pins FR for nvidia corporation, Paul Albert Lalonde of Victoria CA for nvidia corporation
IPC Code(s): G06F8/70, G06F8/10, G06F8/41, G06F9/455, G06T1/60, G06T15/80
CPC Code(s): G06F8/70
Abstract: apparatuses, systems, and techniques for a compiled shader program caches in a cloud computing environment. a set of compiled shader programs associated with an instance of an application hosted by an application hosting platform is received. the set of compiled shader programs are included in an shader cache associated with the application, the shader cache hosted by the application hosting platform. a detection is made that a shader program is referenced during a runtime of the instance of the application. responsive to a determination that a compiled version of the referenced shader program is not included in the received set of compiled shader programs, the shader program is compiled to generate the compiled version of the shader program. a request is transmitted to the application hosting platform to modify the shader cache in view of the compiled version of the shader program.
Inventor(s): Ahmad Itani of San Jose CA US for nvidia corporation, Yen-Te Shih of Zhubei City TW for nvidia corporation, Jagadeesh Sankaran of Dublin CA US for nvidia corporation, Ravi P. Singh of Austin TX US for nvidia corporation, Ching-Yu Hung of Pleasanton CA US for nvidia corporation
IPC Code(s): G06F13/28
CPC Code(s): G06F13/28
Abstract: in various examples, a vpu and associated components may be optimized to improve vpu performance and throughput. for example, the vpu may include a min/max collector, automatic store predication functionality, a simd data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. in addition, decoupled accelerators may be used to offload vpu processing tasks to increase throughput and performance, and a hardware sequencer may be included in a dma system to reduce programming complexity of the vpu and the dma system. the dma and vpu may execute a vpu configuration mode that allows the vpu and dma to operate without a processing controller for performing dynamic region based data movement operations.
20250103718. PLATFORM RESILIENCY AUTHORITY_simplified_abstract_(nvidia corporation)
Inventor(s): Joseph Michael Pennisi of Apex NC US for nvidia corporation, Thorsten Peter Stremlau of Cary NC US for nvidia corporation
IPC Code(s): G06F21/57, G06F8/65
CPC Code(s): G06F21/572
Abstract: systems and methods are directed toward a platform resiliency authority that may be used to identify a component capability to manage one or more update requests using on-component structures. when an update request is received, a component capability level may be determined and, if the component is unable to perform each of a protection, a detection, and a recovery operation on-component, additional update information may be identified and used to cause the update to be installed for the component.
20250103868. IMAGE GENERATION USING NEURAL NETWORKS_simplified_abstract_(nvidia corporation)
Inventor(s): Mateusz Sieniawski of Warsaw PL for nvidia corporation, Pawel Morkisz of San Jose CA US for nvidia corporation
IPC Code(s): G06N3/0475, G06T5/00
CPC Code(s): G06N3/0475
Abstract: apparatuses, systems, and techniques to generate an image using a neural network based model using a variable error threshold. in at least one embodiment, one or more neural networks are used to generate a final output image by iteratively removing noise from an initial image based, at least in part, on one or more variable error threshold values.
Inventor(s): Urs Muller of Keyport NJ US for nvidia corporation, Mariusz Bojarski of Brooklyn NY US for nvidia corporation, Chenyi Chen of Fremont CA US for nvidia corporation, Bernhard Firner of Highland Park NJ US for nvidia corporation
IPC Code(s): G06N3/08, G06N20/00, G06V10/774, G06V20/56
CPC Code(s): G06N3/08
Abstract: in various examples, a machine learning model—such as a deep neural network (dnn)—may be trained to use image data and/or other sensor data as inputs to generate two-dimensional or three-dimensional trajectory points in world space, a vehicle orientation, and/or a vehicle state. for example, sensor data that represents orientation, steering information, and/or speed of a vehicle may be collected and used to automatically generate a trajectory for use as ground truth data for training the dnn. once deployed, the trajectory points, the vehicle orientation, and/or the vehicle state may be used by a control component (e.g., a vehicle controller) for controlling the vehicle through a physical environment. for example, the control component may use these outputs of the dnn to determine a control profile (e.g., steering, decelerating, and/or accelerating) specific to the vehicle for controlling the vehicle through the physical environment.
Inventor(s): Wonmin BYEON of Santa Cruz CA US for nvidia corporation, Sudarshan BABU of Chicago IL US for nvidia corporation, Shalini DE MELLO of San Francisco CA US for nvidia corporation, Jan KAUTZ of Lexington MA US for nvidia corporation
IPC Code(s): G06N3/0985, G06N3/0895
CPC Code(s): G06N3/0985
Abstract: one embodiment of the present invention sets forth a technique for performing meta-learning. the technique includes performing a first set of training iterations to convert a prediction learning network into a first trained prediction learning network based on a first support set of training data and executing a representation learning network and the first trained prediction learning network to generate a first set of supervised training output and a first set of self-supervised training output based on a first query set of training data corresponding to the first support set of training data. the technique also includes performing a first training iteration to convert the representation learning network into a first trained representation learning network based on a first loss associated with the first set of supervised training output and a second loss associated with the first set of self-supervised training output.
Inventor(s): Zizheng Pan of Melbourne AU for nvidia corporation, De-An Huang of Cupertino CA US for nvidia corporation, Weili Nie of Sunnyvale CA US for nvidia corporation, Zhiding Yu of Cupertino CA US for nvidia corporation, Chaowei Xiao of Seattle WA US for nvidia corporation, Anima Anandkumar of Pasadena CA US for nvidia corporation
IPC Code(s): G06N20/20
CPC Code(s): G06N20/20
Abstract: diffusion models are machine learning algorithms that are uniquely trained to generate high-quality data from an input lower-quality data. diffusion probabilistic models use discrete-time random processes or continuous-time stochastic differential equations (sdes) that learn to gradually remove the noise added to the data points. with diffusion probabilistic models, high quality output currently requires sampling from a large diffusion probabilistic model which corners at a high computational cost. the present disclosure stitches together the trajectory of two or more inferior diffusion probabilistic models during a denoising process, which can in turn accelerate the denoising process by avoiding use of only a single large diffusion probabilistic model.
Inventor(s): Loudon Cohen of San Jose CA US for nvidia corporation, Gregory Massal of Austin TX US for nvidia corporation, Pekka Janis of Uusimaa FI for nvidia corporation
IPC Code(s): G06T3/40, G06N3/04, G06T5/00, G06T5/50
CPC Code(s): G06T3/4046
Abstract: apparatuses, systems, and techniques are presented to reconstruct one or more images. in at least one embodiment, one or more neural networks are used to upsample one or more images based, at least in part, on one or more brightness values.
20250104264. SELECTING LOCATIONS OF OBJECTS WITHIN IMAGES_simplified_abstract_(nvidia corporation)
Inventor(s): Pankaj Ratnakar Kadtan of Pune IN for nvidia corporation
IPC Code(s): G06T7/70, G06T7/11, G06V10/25, G06V20/54
CPC Code(s): G06T7/70
Abstract: apparatuses, systems, and methods to cause one or more locations of one or more objects within one or more images to be identified based, at least in part, on one or more locations of the one or more objects within one or more previous images.
Inventor(s): Jonathan TREMBLAY of Redmond WA US for nvidia corporation, Stanley BIRCHFIELD of Sammamish WA US for nvidia corporation, Valts BLUKIS of Seattle WA US for nvidia corporation, Balakumar SUNDARALINGAM of Seattle WA US for nvidia corporation, Stephen TYREE of University City MO US for nvidia corporation, Bowen WEN of Bellevue WA US for nvidia corporation
IPC Code(s): G06T7/73, G06T15/04
CPC Code(s): G06T7/75
Abstract: one embodiment of a method for determining object poses includes receiving first sensor data and second sensor data, where the first sensor data is associated with a first modality, and the second sensor data is associated with a second modality that is different from the first modality, and performing one or more iterative operations to determine a pose of an object based on one or more comparisons of (i) one or more renderings of a three-dimensional (3d) representation of the object in the first modality with the first sensor data, and (ii) one or more renderings of the 3d representation of the object in the second modality with the second sensor data.
Inventor(s): Jakob Richard Hoydis of Paris FR for nvidia corporation, Faycal Ait Aoudia of Santa Clara CA US for nvidia corporation, Sebastian Cammerer of Tuebingen DE for nvidia corporation, Alexander Georg Keller of Berlin DE for nvidia corporation, Merlin Nimier-David of Nyon CH for nvidia corporation, Nikolaus Binder of Berlin DE for nvidia corporation, Guillermo Anibal Marcus Martinez of Berlin DE for nvidia corporation
IPC Code(s): G06T15/06
CPC Code(s): G06T15/06
Abstract: embodiments of the present disclosure relate to neural components for differentiable ray tracing of radio propagation. differentiable ray tracing may be used to refine the scene geometry of the physical environment, to learn or optimize the scene properties of objects in the scene, to learn or optimize the scene properties of antennas, and to learn or optimize antenna patterns, array geometries, and orientations and positions of transmitters and receivers. once scene properties have been learned or optimized, the differentiable ray tracer may further be used to simulate the performance of different configurations of the transmitters, receivers, and scene geometry. in an embodiment, one or more of the scene geometry, scene properties, and antenna characteristics are computed by a differentiable parametric function, such as a neural network, etc. and parameters of the differentiable parametric function are learned using the differentiable ray tracing.
Inventor(s): Samuli LAINE of Uusimaa FI for nvidia corporation, Timo AILA of Uusimaa FI for nvidia corporation, Tero KARRAS of Uusimaa FI for nvidia corporation, Gregory MUTHLER of Austin TX US for nvidia corporation, William P. NEWHALL, JR. of Woodside CA US for nvidia corporation, Ronald C BABICH, JR. of Murrysville PA US for nvidia corporation, Craig KOLB of Oakland CA US for nvidia corporation, Ignacio LLAMAS of Palo Alto CA US for nvidia corporation, John BURGESS of Austin TX US for nvidia corporation
IPC Code(s): G06T15/06, G06T15/00, G06T17/00
CPC Code(s): G06T15/06
Abstract: methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. in an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. in an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.
Inventor(s): Gregory MUTHLER of Chapel Hill NC US for nvidia corporation, John BURGESS of Austin TX US for nvidia corporation, Magnus ANDERSSON of Lund SE for nvidia corporation, Ian KWONG of Santa Clara CA US for nvidia corporation, Edward BIDDULPH of Helsinki FI for nvidia corporation
IPC Code(s): G06T15/06, G06T15/00, G06T15/40
CPC Code(s): G06T15/06
Abstract: techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. the reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
Inventor(s): Samuli Laine of Uusimaa FI for nvidia corporation, Tero Karras of Uusimaa FI for nvidia corporation, Greg Muthler of Austin TX US for nvidia corporation, William Parsons Newhall, JR. of Woodside CA US for nvidia corporation, Ronald Charles Babich, JR. of Murrysville PA US for nvidia corporation, Ignacio LLamas of Palo Alto CA US for nvidia corporation, John Burgess of Austin TX US for nvidia corporation
IPC Code(s): G06T15/06, G06T1/20, G06T15/00
CPC Code(s): G06T15/06
Abstract: a hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. the primitives may include opaque and alpha triangles used in generating a virtual scene. the hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. the hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.
Inventor(s): Viktor Grigoryevich Vandanov of San Jose CA US for nvidia corporation, Rouslan Lyubomirov Dimitrov of Santa Clara CA US for nvidia corporation, Seth Schneider of Santa Clara CA US for nvidia corporation
IPC Code(s): G09G5/395
CPC Code(s): G09G5/395
Abstract: disclosed are apparatuses, systems, and techniques that reduce latency of frame processing pipelines. the techniques include but are not limited to causing a display to set a refresh rate that matches a frame rendering rate of an application and rendering, with the frame rendering rate, a plurality of frames. rendering frames includes generating, using a first processing unit, sets of instructions associated with respective frames and generated starting at times spaced with the refresh rate, processing, using a second processing unit, the sets of instructions to render the frames, and causing the display to display the rendered frames.
20250105734. WIDE-RANGE POWER DELIVERY SYSTEM_simplified_abstract_(nvidia corporation)
Inventor(s): Siddharth Saxena of San Jose CA US for nvidia corporation, Sudhir Shrikantha Kudva of Dublin CA US for nvidia corporation, Miguel Rodriguez of Golden CO US for nvidia corporation, Vijay Srinivasan of San Francisco CA US for nvidia corporation, Tezaswi Raja of San Jose CA US for nvidia corporation, Carl Thomas Gray of Apex NC US for nvidia corporation, Santosh Santosh of Los Gatos CA US for nvidia corporation
IPC Code(s): H02M3/155, H01L23/528
CPC Code(s): H02M3/155
Abstract: power delivery systems for integrated circuits that include a first metal path traversing first metal layers from a global power domain supply to a voltage regulator, a second metal path traversing second metal layers from a local power domain supply to the voltage regulator, and a third metal path traversing third metal layers from the local power domain supply to an integrated circuit. electrical isolation gaps are formed between the first metal layers, the second metal layers, and the third metal layers.
20250105920. OPTICAL LINK ARCHITECTURE_simplified_abstract_(nvidia corporation)
Inventor(s): Benjamin Giles Lee of Ridgefield CT US for nvidia corporation, Meer Nazmus Sakib of Berkeley CA US for nvidia corporation
IPC Code(s): H04B10/40, H04B10/80, H04J14/02
CPC Code(s): H04B10/40
Abstract: an optical apparatus, with an optical interconnect, the optical interconnect including a first optical transceiver having a first notch filter, the first notch filter including first and second optical add drop multiplexer demultiplexers connected to receive a continuous wave light beam and send a first and second filtered wavelengths to first and second resonant modulators which send first and send modulated optical signals through a light propagation path. the second filtered wavelength is different from the first filtered wavelength, and the second modulated optical signal has a polarity that is orthogonal to a polarity of the first modulated optical signal. methods of communicating using the apparatus and an optical filter for use in an optical transceiver are also disclosed.
20250106355. ADAPTIVE VIDEO FRAME BLENDING_simplified_abstract_(nvidia corporation)
Inventor(s): Zhekun Luo of Santa Clara CA US for nvidia corporation, Robert Thomas Pottorff of Layton UT US for nvidia corporation, Karan Sapra of San Jose CA US for nvidia corporation, Jarmo Rafael Lunden of Espoo FI for nvidia corporation, Andrew J. Tao of Los Altos CA US for nvidia corporation, Bryan Christopher Catanzaro of Los Altos Hills CA US for nvidia corporation
IPC Code(s): H04N7/01, A63F13/52, G06T7/20, G06T7/579
CPC Code(s): H04N7/0137
Abstract: apparatuses, systems, and techniques to process image frames. in at least one embodiment, one or more intermediate video frames are generated between a first video frame and a second video frame. in at least one embodiment, the one or more intermediate video frames are generated based, at least in part, on depth information of one or more pixels of the first video frame or second video frame.
Inventor(s): Rongrong Zhou of Shenzhen CN for nvidia corporation
IPC Code(s): H04N19/124, G06T1/00, G06V10/60, G06V10/74, H04N19/132
CPC Code(s): H04N19/124
Abstract: in various examples, visual differences between video data and an encoded version of the video data are used to determine updates to quantization parameters (qps) used to encode the video data to store or upload video clips that corresponds to notable events associated with a machine. the video data may correspond to images applied to a machine learning model to perform control operations for the machine. a metric may be used to quantify the visual differences. to evaluate the visual differences, samples of the video data and encoded video data may be determined and analyzed, rather than entire images or frames. to selectively enable updates to qps, the system may detect that a deviation between a bitrate corresponding to the encoded data and a reference bitrate has exceeded a threshold.
- NVIDIA Corporation
- B60W60/00
- B60W30/095
- B60W30/18
- CPC B60W60/001
- Nvidia corporation
- CPC B60W60/0011
- G05D1/00
- G05B13/02
- G05D1/227
- G05D1/249
- G06N3/02
- G06N3/04
- G06N3/043
- G06N3/045
- G06N3/088
- CPC G05D1/0231
- G05F1/56
- G04F10/00
- H03M7/16
- CPC G05F1/56
- G06F8/70
- G06F8/10
- G06F8/41
- G06F9/455
- G06T1/60
- G06T15/80
- CPC G06F8/70
- G06F13/28
- CPC G06F13/28
- G06F21/57
- G06F8/65
- CPC G06F21/572
- G06N3/0475
- G06T5/00
- CPC G06N3/0475
- G06N3/08
- G06N20/00
- G06V10/774
- G06V20/56
- CPC G06N3/08
- G06N3/0985
- G06N3/0895
- CPC G06N3/0985
- G06N20/20
- CPC G06N20/20
- G06T3/40
- G06T5/50
- CPC G06T3/4046
- G06T7/70
- G06T7/11
- G06V10/25
- G06V20/54
- CPC G06T7/70
- G06T7/73
- G06T15/04
- CPC G06T7/75
- G06T15/06
- CPC G06T15/06
- G06T15/00
- G06T17/00
- G06T15/40
- G06T1/20
- G09G5/395
- CPC G09G5/395
- H02M3/155
- H01L23/528
- CPC H02M3/155
- H04B10/40
- H04B10/80
- H04J14/02
- CPC H04B10/40
- H04N7/01
- A63F13/52
- G06T7/20
- G06T7/579
- CPC H04N7/0137
- H04N19/124
- G06T1/00
- G06V10/60
- G06V10/74
- H04N19/132
- CPC H04N19/124