NVIDIA Corporation patent applications on March 21st, 2024
Contents
Patent Applications by NVIDIA Corporation on March 21st, 2024
NVIDIA Corporation: 45 patent applications
NVIDIA Corporation has applied for patents in the areas of G06V10/82 (10), G06T15/06 (8), G06T1/20 (4), G06T7/20 (4), G06N3/084 (4)
With keywords such as: systems, techniques, data, embodiment, apparatuses, based, neural, networks, processor, and video in patent application abstracts.
NVIDIA Corporation's patent applications on March 21st, 2024, showcase a broad spectrum of innovations across multiple technological domains. Here's a detailed exploration of these applications, highlighting their relevance and potential impact.
NVIDIA Corporation's March 21st, 2024, Patent Applications
NVIDIA Corporation filed 45 patent applications, revealing its expansive research and development efforts in various areas of technology. These applications primarily fall into the International Patent Classification (IPC) codes of G06V10/82, G06T15/06, G06T1/20, G06T7/20, and G06N3/084. The keywords identified in the patent application abstracts such as "systems," "techniques," "data," "embodiment," "apparatuses," "based," "neural," "networks," "processor," and "video," suggest a strong focus on innovations related to computing technologies, particularly in the areas of machine learning, neural networks, and video processing.
Highlighted Innovations
1. **VIRTUAL AGENT TRAJECTORY PREDICTION AND TRAFFIC MODELING FOR MACHINE SIMULATION SYSTEMS AND APPLICATIONS** (20240092390): This patent application focuses on model-based trajectory simulation of agents in simulated environments, which is crucial for testing autonomous or semi-autonomous vehicle designs in diverse and complex environments. This innovation has implications for enhancing the safety and reliability of autonomous vehicles.
2. **FLEXIBLE ONE-HOT DECODING LOGIC FOR CLOCK CONTROLS** (20240094291): A circuit designed to improve control over asynchronous signal crossings during circuit scan tests. This technology could significantly enhance the efficiency and reliability of integrated circuits used in various electronic devices.
3. **TECHNIQUES TO MODIFY PROCESSOR PERFORMANCE** (20240094793 and 20240094796): These applications propose methods to optimize processor performance, including adjusting operation voltages and clock frequencies based on error rates or the performance of other processors. Such advancements could lead to more efficient and powerful computing systems.
4. **PROGRAM CODE VERSIONS** (20240095024): Focusing on performing versions of program code based on memory region overlaps. This innovation can lead to more efficient software development and execution, particularly in complex computing environments.
5. **OFFLOADED TASK COMPUTATION ON NETWORK-ATTACHED CO-PROCESSORS** (20240095062): This invention relates to devices and methods for performing computing operations more efficiently by offloading certain tasks to co-processors. This could enhance the performance of data centers and cloud computing services.
6. **PROMPT GENERATOR FOR USE WITH ONE OR MORE MACHINE LEARNING PROCESSES** (20240095077): A method to generate prompts for machine learning processes to perform tasks identified in the prompts. This could have broad applications in automating complex tasks using artificial intelligence.
7. **PARALLEL WORKLOAD SCHEDULING BASED ON WORKLOAD DATA COHERENCE** (20240095083): This patent application addresses the efficient processing of workloads that exhibit high divergence in execution and data access, which is crucial for optimizing parallel computing tasks.
Questions about NVIDIA Corporation's Patent Applications
- What specific industries could be most significantly impacted by NVIDIA Corporation's latest patent applications?
- Industries Impacted: The automotive industry, particularly autonomous vehicle development, electronics manufacturing, cloud computing, and AI development sectors, stand to benefit significantly.
- How do these patent applications compare to current technologies and solutions available in the market?
- Comparison to Current Technologies: NVIDIA's latest innovations appear to focus on enhancing efficiency, performance, and flexibility, potentially offering advancements over existing solutions in terms of processing power and energy consumption.
- What are the potential environmental impacts of implementing these innovations, particularly in terms of energy consumption and electronic waste?
- Environmental Impacts: By improving efficiency and processor performance, these innovations could lead to reduced energy consumption. However, the environmental benefits would need to be balanced against the lifecycle impacts of producing and disposing of advanced electronics.
- How could these innovations influence the future of machine learning and artificial intelligence development?
- Influence on AI Development: These patents, especially those related to machine learning and neural networks, could accelerate the development of more sophisticated and capable AI systems.
- What are the potential challenges in commercializing these technologies, including regulatory hurdles and market acceptance?
- Commercialization Challenges: Regulatory approval processes, particularly for autonomous vehicle technologies, and ensuring market readiness and acceptance for advanced computing solutions could pose significant challenges.
Patent Applications by NVIDIA Corporation
Inventor(s): Jonah PHILION of Toronto (CA) for nvidia corporation, Jeevan DEVARANJAN of Toronto (CA) for nvidia corporation, Xue Bin PENG of Vancouver (CA) for nvidia corporation, Sanja FIDLER of Toronto (CA) for nvidia corporation
IPC Code(s): B60W60/00, B60W30/095, B60W50/00, B60W50/14
Abstract: in various examples, systems and methods are presented for model-based trajectory simulation of agents in a simulated environment. traffic simulators mimic reality so that autonomous or semi-autonomous vehicle design teams can validate driving models in environments that have diversity and complexity. in some embodiments, for a model-controlled agent of a simulation environment, a plurality of navigation probability distributions are generated, each of the plurality of navigation probability distributions defining a candidate trajectory for the agent to follow. a trajectory is selected for the agent based at least on at least one of the plurality of navigation probability distributions, and the agent is moved within the simulation environment based at least on the selected trajectory. in some embodiments, a search algorithm may be applied across multiple time-steps of a simulation, for example, to identify the occurrence of collision-free sequences of navigation probability distributions.
Inventor(s): Mahmut Yilmaz of Los Altos Hills CA (US) for nvidia corporation, Vinod Pagalone of San Jose CA (US) for nvidia corporation, Munish Aggarwal of Santa Clara CA (US) for nvidia corporation, Doochul Shin of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G01R31/3185, G01R31/317
Abstract: a circuit for improving control over asynchronous signal crossings during circuit scan tests includes multiple scan registers and a decoder configured to translate a combined output of the scan registers into multiple one-hot controls to the local clock gates of scan registers disposed in multiple different clock domains. programmable registers are provided to selectively enable and disable the local clock gates of the different clock domains.
Inventor(s): Mohammed Nasir of San Jose CA (US) for nvidia corporation
IPC Code(s): G05B13/04
Abstract: embodiments of the present disclosure relate to a method of automated tuning of control parameters. in some implementations, the method may include obtaining, from a search algorithm, one or more parameter sets that determine how a controller responds to an environment with at least one changing variable. in these and other implementations, at least one of the parameter sets may include a vector parameter that includes a vector of values. in these and other implementations, a value selected from the vector of values for the vector parameter during operation of the controller may be based on the at least one changing variable. in some implementations, the method may include ordering the vector of values for the vector parameter of the parameter sets and simulating at least one operation of the controller using the parameter sets with the ordered vector of values for the vector parameter.
20240094793.TECHNIQUES TO MODIFY PROCESSOR PERFORMANCE_simplified_abstract_(nvidia corporation)
Inventor(s): Benjamin D. Faulkner of Los Altos Hills CA (US) for nvidia corporation, Padmanabhan Kannan of Santa Clara CA (US) for nvidia corporation, Srinivasan Raghuraman of San Jose CA (US) for nvidia corporation, Peng Cheng Shen of Sunnyvale CA (US) for nvidia corporation, Divya Ramakrishnan of San Jose CA (US) for nvidia corporation, Swanand Santosh Bindoo of San Jose CA (US) for nvidia corporation, Sreedhar Narayanaswamy of Sunnyvale CA (US) for nvidia corporation, Amey Y. Marathe of Union City CA (US) for nvidia corporation
IPC Code(s): G06F1/30, G06F11/07
Abstract: apparatuses, systems, and techniques to optimize processor performance. in at least one embodiment, a method increases an operation voltage of one or more processors, based at least in part, on one or more error rates of the one or more processors.
20240094796.TECHNIQUES TO MODIFY PROCESSOR PERFORMANCE_simplified_abstract_(nvidia corporation)
Inventor(s): Sreedhar Narayanaswamy of Sunnyvale CA (US) for nvidia corporation, Kyle John O'Shaughnessy of Santa Rosa CA (US) for nvidia corporation, Pratikkumar Dilipkumar Patel of Milpitas CA (US) for nvidia corporation, Chad R. Plummer of San Rafael CA (US) for nvidia corporation, Benjamin D. Faulkner of Los Altos Hills CA (US) for nvidia corporation
IPC Code(s): G06F1/324, G06F1/3237, G06F1/3296
Abstract: apparatuses, systems, and techniques to optimize performance of a processor group. in at least one embodiment, a method increases a processor's clock frequency based, at least in part, on performance of other processors in a group.
20240095024.PROGRAM CODE VERSIONS_simplified_abstract_(nvidia corporation)
Inventor(s): Güray Özen of Berlin (DE) for nvidia corporation, Michael Joseph Wolfe of Hillsboro OR (US) for nvidia corporation
IPC Code(s): G06F8/71
Abstract: apparatuses, systems, and techniques to perform versions of program code. in at least one embodiment, one or more versions of a plurality of versions of software code are performed. in at least one embodiment, one or more versions of a plurality of versions of software code are performed based, at least in part, on whether the versions of the program code access overlapping memory regions.
Inventor(s): Shelton George Dsouza of San Jose CA (US) for nvidia corporation, Michael Murphy of Newark CA (US) for nvidia corporation
IPC Code(s): G06F9/445, G06F8/51, G06F9/54
Abstract: apparatuses, systems, and techniques to optimize processor performance. in at least one embodiment, a processor is to perform an application programming interface (api) to exclude one or more portions of program code from a program.
Inventor(s): Sourav Chakraborty of Austin TX (US) for nvidia corporation, Tomislav Janjusic of Parker TX (US) for nvidia corporation, Mohammadreza Bayatpour of Campbell CA (US) for nvidia corporation, Joshua Samuel Ladd of Knoxville TN (US) for nvidia corporation
IPC Code(s): G06F9/48, G06F9/445, G06F12/1081
Abstract: systems, methods, and devices for performing computing operations are provided. in one example, a device is described to include a first processing unit and second processing unit in communication via a network interconnect. the first processing unit is configured to offload at least one of computation tasks and communication tasks to the second processing unit while the first processing unit performs the application-level processing tasks. the second processing unit is also configured to provide a result vector to the first processing unit when the at least one of computation tasks and communication tasks are completed.
Inventor(s): Ishika Singh of Seattle WA (US) for nvidia corporation, Arsalan Mousavian of Seattle WA (US) for nvidia corporation, Ankit Goyal of Seattle WA (US) for nvidia corporation, Danfei Xu of Atlanta GA (US) for nvidia corporation, Jonathan Tremblay of Redmond WA (US) for nvidia corporation, Dieter Fox of Seattle WA (US) for nvidia corporation, Animesh Garg of Berkeley CA (US) for nvidia corporation, Valts Blukis of Kirkland WA (US) for nvidia corporation
IPC Code(s): G06F9/50, G06N20/00
Abstract: apparatuses, systems, and techniques to generate a prompt for one or more machine learning processes. in at least one embodiment, the machine learning process(es) generate(s) a plan to perform a task (identified in the prompt) that is to be performed by an agent (real world or virtual).
Inventor(s): Martin Stich of Memmingen (DE) for nvidia corporation, Rasmus Barringer of Helsingborg (SE) for nvidia corporation, Robert Toth of Lund (SE) for nvidia corporation
IPC Code(s): G06F9/50
Abstract: approaches for addressing issues associated with processing workloads that exhibit high divergence in execution and data access are provided. a plurality of workload items to be processed at least partially in parallel may be identified. coherence information associated with the plurality of workload items may be determined. the plurality of workload items may be enqueued in a segmented queue. the plurality of workload items may be sorted based at least on a similarity of the coherence information. the sorted plurality of workload items may be stored to the queue. using a set of processing units, the workload items in the queue may be processed at least partially in parallel according to an order of the sorting.
Inventor(s): Robert Thomas Pottorff of Layton UT (US) for nvidia corporation, Karan Sapra of San Jose CA (US) for nvidia corporation, Andrew Leighton Edelsten of Morgan Hill CA (US) for nvidia corporation
IPC Code(s): G06F9/54, G06T1/20, H04N7/01
Abstract: apparatuses, systems, and techniques to process image frames. in at least one embodiment, an application programming interface (api) is performed to cause frame interpolation to be performed using one or more neural networks.
20240095133.FREQUENCY ADJUSTMENT FOR PROCESSORS_simplified_abstract_(nvidia corporation)
Inventor(s): Sreedhar Narayanaswamy of Sunnyvale CA (US) for nvidia corporation, Benjamin D. Faulkner of Los Altos Hills CA (US) for nvidia corporation
IPC Code(s): G06F15/78, G06F11/07
Abstract: apparatuses, systems, and techniques adjust a frequency at which a processor operates. in at least one embodiment, a frequency at which a processor operates is adjusted based, at least in part, on different cores of the processor performing one or more identical instructions.
20240095302.CHANGING PRECISION OF OPERANDS_simplified_abstract_(nvidia corporation)
Inventor(s): Jiqun Tu of New York NY (US) for nvidia corporation, David Maxwell Clark of Mountain View CA (US) for nvidia corporation
IPC Code(s): G06F17/16, G06F7/544
Abstract: apparatuses, systems, and techniques to perform matrix multiply-accumulate (mma) operations on data of a first type using one or more mma instructions for data of a second type. in at least one embodiment, a single tensorfloat-32 (tf32) mma instruction computes a 32-bit floating point (fp32) output using tf32 input operands converted from fp32 data values.
20240095447.NEURAL NETWORK-BASED LANGUAGE RESTRICTION_simplified_abstract_(nvidia corporation)
Inventor(s): Wei Ping of Sunnyvale CA (US) for nvidia corporation, Boxin Wang of Urbana IL (US) for nvidia corporation, Chaowei Xiao of Seattle WA (US) for nvidia corporation, Mohammad Shoeybi of Foster City CA (US) for nvidia corporation, Mostofa Patwary of Fremont CA (US) for nvidia corporation, Anima Anandkumar of Pasadena CA (US) for nvidia corporation, Bryan Catanzaro of Los Altos Hills CA (US) for nvidia corporation
IPC Code(s): G06F40/279, G06F40/205, G06F40/55
Abstract: apparatuses, systems, and techniques are presented to identify and prevent generation of restricted content. in at least one embodiment, one or more neural networks are used to identify restricted content based only on the restricted content.
Inventor(s): Peng Xu of Redwood City CA (US) for nvidia corporation, Mostofa Patwary of Fremont CA (US) for nvidia corporation, Rajath Shetty of Sunnyvale CA (US) for nvidia corporation, Niral Lalit Pathak of San Jose CA (US) for nvidia corporation, Ratin Kumar of Cupertino CA (US) for nvidia corporation, Bryan Catanzaro of Los Altos Hills CA (US) for nvidia corporation, Mohammad Shoeybi of Foster City CA (US) for nvidia corporation
IPC Code(s): G06F40/35
Abstract: in various examples, systems and methods that use dialogue systems associated with various machine systems and applications are described. for instance, the systems and methods may receive text data representing speech, such as a question associated with a vehicle or other machine type. the systems and methods then use a retrieval system(s) to retrieve a question/answer pair(s) associated with the text data and/or contextual information associated with the text data. in some examples, the contextual information is associated with a knowledge base associated with or corresponding to the vehicle. the systems and methods then generate a prompt using the text data, the question/answer pair(s), and/or the contextual information. additionally, the systems and methods determine, using a language model(s) and based at least on the prompt, an output associated with the text data. for instance, the output may include information that answers the question associated with the vehicle.
Inventor(s): Ryan Leary of Woodstock GA (US) for nvidia corporation, Jonathan Cohen of Mountain View CA (US) for nvidia corporation
IPC Code(s): G06F40/40, G06F40/284
Abstract: approaches presented herein can provide for the performance of specific types of tasks using a large model, without a need to retrain the model. custom endpoints can be trained for specific types of tasks, as may be indicated by the specification of one or more guidance mechanisms. a guidance mechanism can be added to or used along with a request to guide the model in performing a type of task with respect to a string of text. an endpoint receiving such a request can perform any marshalling needed to get the request in a format required by the model, and can add the guidance mechanisms to the request by, for example, prepending one or more text strings (or text prefixes) to a text-formatted request. a model receiving this string can process the text according to the guidance mechanisms. such an approach can allow for a variety of tasks to be performed by a single model.
Inventor(s): Ankur HANDA of San Jose CA (US) for nvidia corporation, Gavriel STATE of Toronto (CA) for nvidia corporation, Arthur David ALLSHIRE of Toronto (CA) for nvidia corporation, Dieter FOX of Seattle WA (US) for nvidia corporation, Jean-Francois Victor LAFLECHE of Toronto (CA) for nvidia corporation, Jingzhou LIU of Oakville (CA) for nvidia corporation, Viktor MAKOVIICHUK of Santa Clara CA (US) for nvidia corporation, Yashraj Shyam NARANG of Seattle WA (US) for nvidia corporation, Aleksei Vladimirovich PETRENKO of Cupertino CA (US) for nvidia corporation, Ritvik SINGH of Toronto (CA) for nvidia corporation, Balakumar SUNDARALINGAM of Seattle WA (US) for nvidia corporation, Karl VAN WYK of Issaquah WA (US) for nvidia corporation, Alexander ZHURKEVICH of San Jose CA (US) for nvidia corporation
IPC Code(s): G06N3/08
Abstract: systems and techniques are described related to training one or more machine learning models for use in control of a robot. in at least one embodiment, one or more machine learning models are trained based at least on simulations of the robot and renderings of such simulations—which may be performed using one or more ray tracing algorithms, operations, or techniques.
20240095534.NEURAL NETWORK PROMPT TUNING_simplified_abstract_(nvidia corporation)
Inventor(s): Anima Anandkumar of Pasadena CA (US) for nvidia corporation, Chaowei Xiao of Tempe AZ (US) for nvidia corporation, Weili Nie of Sunnyvale CA (US) for nvidia corporation, De-An Huang of Cupertino CA (US) for nvidia corporation, Zhiding Yu of Cupertino CA (US) for nvidia corporation, Manli Shu of Greenbelt MD (US) for nvidia corporation
IPC Code(s): G06N3/084, G06N3/045
Abstract: apparatuses, systems, and techniques to perform neural networks. in at least one embodiment, a most consistent output of one or more pre-trained neural networks is to be selected. in at least one embodiment, a most consistent output of one or more pre-trained neural networks is to be selected based, at least in part, on a plurality of variances of one or more inputs to the one or more neural networks.
20240095536.NEURAL NETWORK TRAINING BASED ON CAPABILITY_simplified_abstract_(nvidia corporation)
Inventor(s): Xingqin Lin of San Jose CA (US) for nvidia corporation, Lopamudra Kundu of Sunnyvale CA (US) for nvidia corporation, Christopher Hans Dick of San Jose CA (US) for nvidia corporation
IPC Code(s): G06N3/08, G06N3/04, H04L41/16
Abstract: apparatuses, systems, and techniques to cause one or more neural networks to be trained. in at least one embodiment, a processor includes one or more circuits to cause one or more neural networks to be trained based, at least in part, on one or more capabilities.
Inventor(s): Shiqiu Liu of Cupertino CA (US) for nvidia corporation, Jussi Rasanen of Helsinki (FI) for nvidia corporation, Michael Ranzinger of Park City UT (US) for nvidia corporation, Guilin Liu of San Jose CA (US) for nvidia corporation, Andrew Tao of Los Altos CA (US) for nvidia corporation, Bryan Christopher Catanzaro of Los Altos Hills CA (US) for nvidia corporation
IPC Code(s): G06T3/40, G06T5/00, G06T5/50
Abstract: apparatuses, systems, and techniques to use one or more neural networks to generate an upsampled version of one or more images based, at least in part, on a denoised version of said one or more images. at least one embodiment pertains to generating an upsampled high-resolution image from a noisy version and denoised version of a low-resolution image. at least one embodiment pertains to separating components of a low-resolution image before denoising an image.
Inventor(s): Robert Thomas Pottorff of Layton UT (US) for nvidia corporation, Karan Sapra of San Jose CA (US) for nvidia corporation, Andrew Leighton Edelsten of Morgan Hill CA (US) for nvidia corporation
IPC Code(s): G06T3/40
Abstract: apparatuses, systems, and techniques to process image frames. in at least one embodiment, an application programming interface (api) is performed to disable frame interpolation to use one or more neural networks.
Inventor(s): Ryan Albright of Beaverton OR (US) for nvidia corporation, Jordan Levy of Portland OR (US) for nvidia corporation, William Andrew Mecham of Elk Grove CA (US) for nvidia corporation, William Ryan Weese of Portland OR (US) for nvidia corporation, Benjamin Goska of Portland OR (US) for nvidia corporation, Aaron Richard Carkin of Hillsboro OR (US) for nvidia corporation, Michael Thompson of Wilsonville OR (US) for nvidia corporation
IPC Code(s): G06T7/00, G06F30/10, G06T15/00
Abstract: systems and methods integrate different portions of a design review, such as files from a variety of different sources, into an interaction environment for review and interaction by a number of reviewing parties. the reviewing parties interact through an interface that is different from a native software of the files. an automated design review may be performed to evaluate a common rendering, formed from the files, for one or more conflicts, including interferences or version errors.
20240095986.OBJECT ANIMATION USING NEURAL NETWORKS_simplified_abstract_(nvidia corporation)
Inventor(s): Jordan Benjamin Juravsky of Thornhill (CA) for nvidia corporation, Xue Bin Peng of Vancouver (CA) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation
IPC Code(s): G06T13/00, G06F40/20, G10L15/06, G10L15/16, G10L15/18, G10L15/22
Abstract: apparatuses, systems, and techniques to generate animations. in at least one embodiment, one or more neural networks control motion of one or more animated objects based, at least in part, on natural language inputs.
20240095989.VIDEO GENERATION TECHNIQUES_simplified_abstract_(nvidia corporation)
Inventor(s): Arun Mohanray Mallya of Mountain View CA (US) for nvidia corporation, Ting-Chun Wang of Santa Clara CA (US) for nvidia corporation, Ming-Yu Liu of San Jose CA (US) for nvidia corporation
IPC Code(s): G06T13/20, G06T7/20, G06V10/25, G06V10/44, G06V10/74, G06V10/771, G06V10/82
Abstract: apparatuses, systems, and techniques to generate a video using two or more images comprising objects to be included in the video. in at least one embodiment, objects are identified in two or more images using one or more neural networks, to generate a video to include the objects in the video.
Inventor(s): Gregory MUTHLER of Chapel Hill NC (US) for nvidia corporation, John BURGESS of Austin TX (US) for nvidia corporation, Magnus ANDERSSON of Lund (SE) for nvidia corporation, Ian KWONG of Santa Clara CA (US) for nvidia corporation, Edward BIDDULPH of Helsinki (FI) for nvidia corporation
IPC Code(s): G06T15/06, G06T15/00
Abstract: techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. the reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
Inventor(s): Gregory MUTHLER of Chapel Hill NC (US) for nvidia corporation, John BURGESS of Austin TX (US) for nvidia corporation, Magnus ANDERSSON of Lund (SE) for nvidia corporation, Ian KWONG of Santa Clara CA (US) for nvidia corporation, Edward BIDDULPH of Helsinki (FI) for nvidia corporation
IPC Code(s): G06T15/06, G06T15/00, G06T15/40
Abstract: techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. the reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
Inventor(s): Gregory MUTHLER of Chapel Hill NC (US) for nvidia corporation, John BURGESS of Austin TX (US) for nvidia corporation, Magnus ANDERSSON of Lund (SE) for nvidia corporation, Ian KWONG of Santa Clara CA (US) for nvidia corporation, Edward BIDDULPH of Helsinki (FI) for nvidia corporation
IPC Code(s): G06T15/06, G06T15/00, G06T15/30
Abstract: techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. the reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
20240095996.EFFICIENCY OF RAY-BOX TESTS_simplified_abstract_(nvidia corporation)
Inventor(s): Gregory MUTHLER of Chapel Hill NC (US) for nvidia corporation, John BURGESS of Austin TX (US) for nvidia corporation, Eric ENDERTON of Berkeley CA (US) for nvidia corporation, Nikhil DIXIT of Austin TX (US) for nvidia corporation, Josh NOEL of San Jose CA (US) for nvidia corporation
IPC Code(s): G06T15/06
Abstract: to improve the efficiency of bounding volumes in a hardware based ray tracer, we employ a sheared axis-aligned bounding box to approximate an oriented bounding box typically defined by rotations. to achieve this, the bounding volume hierarchy builder shears an axis-aligned box to fit tightly around its enclosed oriented geometry in top level or bottom level space, then computes the inverse shear transform. the bounds are still stored as axis-aligned boxes in memory, now defined in the new sheared coordinate system, along with the derived parameters to transform a ray into the sheared coordinate system before testing intersection with the boxes. the ray-bounding volume intersection test is performed as usual, just in the new sheared coordinate system. additional efficiencies are gained by constraining the number of shear dimensions, constraining the shear transform coefficients to a quantized list, sharing a shear transform across a collection of bounds, performing a shear transform only for ray-bounds testing and not for ray-geometry intersection testing, and adding a specialized shear transform calculator/accelerator to the hardware.
Inventor(s): Jun Gao of Markham (CA) for nvidia corporation, Tianchang Shen of Markham (CA) for nvidia corporation, Zan Gojcic of Schlieren (CH) for nvidia corporation, Wenzheng Chen of Toronto (CA) for nvidia corporation, Zian Wang of Toronto (CA) for nvidia corporation, Daiqing Li of Oakville (CA) for nvidia corporation, Or Litany of Sunnyvale CA (US) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation
IPC Code(s): G06T17/20
Abstract: apparatuses, systems, and techniques are presented to generate digital content. in at least one embodiment, one or more neural networks are used to generate one or more textured three-dimensional meshes corresponding to one or more objects based, at least in part, one or more two-dimensional images of the one or more objects.
Inventor(s): Yaobin Ouyang of Toronto (CA) for nvidia corporation
IPC Code(s): G06V10/60, G06T3/40, G06T5/00
Abstract: approaches presented herein provide for the maintaining of fine details that might be removed by a denoiser used to reduce an amount of noise in an image. an input image can be provided to a denoiser, and can also can be simultaneously processed to extract pixel data that may correspond to fine detail or high frequency features. individual pixels of an image can have a value determined for a material property sampled for that pixel location, and that value can be compared against an average material property value determined for neighboring pixels. the ratio of material values can be multiplied by the value of a corresponding pixel of the denoised image, for any or all pixel locations, to obtain final pixel values for an output image that include less noise than the original image but represent fine detail that may otherwise have been lost during the denoising process.
20240096064.GENERATING MASK INFORMATION_simplified_abstract_(nvidia corporation)
Inventor(s): Daiqing Li of Oakville (CA) for nvidia corporation, Huan Ling of Toronto (CA) for nvidia corporation, Seung Wook Kim of Toronto (CA) for nvidia corporation, Karsten Julian Kreis of Vancouver (CA) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation, Antonio Torralba Barriuso of Somerville MA (US) for nvidia corporation
IPC Code(s): G06V10/774, G06V10/764, G06V10/82
Abstract: apparatuses, systems, and techniques to annotate images using neural models. in at least one embodiment, neural networks generate mask information from labels of one or more objects within one or more images identified by one or more other neural networks.
Inventor(s): Brian Okorn of Pittsburgh PA (US) for nvidia corporation, Arsalan Mousavian of Seattle WA (US) for nvidia corporation, Lucas Manuelli of Seattle WA (US) for nvidia corporation, Dieter Fox of Seattle WA (US) for nvidia corporation
IPC Code(s): G06V10/82, G06V10/26, G06V10/77
Abstract: apparatuses, systems, and techniques are presented to identify one or more objects. in at least one embodiment, one or more neural networks can be used to identify one or more objects based, at least in part, on one or more descriptors of one or more segments of the one or more objects.
Inventor(s): Alexander POPOV of Kirkland WA (US) for nvidia corporation, David NISTER of Bellevue WA (US) for nvidia corporation, Nikolai SMOLYANSKIY of Seattle WA (US) for nvidia corporation, PATRIK GEBHARDT of Cupertino CA (US) for nvidia corporation, Ke CHEN of Mountain View CA (US) for nvidia corporation, Ryan OLDJA of Issaquah WA (US) for nvidia corporation, Hee Seok LEE of Bundang-gu (KR) for nvidia corporation, Shane MURRAY of San Jose CA (US) for nvidia corporation, Ruchi BHARGAVA of Redmond WA (US) for nvidia corporation, Tilman WEKEL of San Jose CA (US) for nvidia corporation, Sangmin OH of San Jose CA (US) for nvidia corporation
IPC Code(s): G06V20/56, G01S13/89, G01S17/89, G06V10/774
Abstract: systems and methods are disclosed that relate to freespace detection using machine learning models. first data that may include object labels may be obtained from a first sensor and freespace may be identified using the first data and the object labels. the first data may be annotated to include freespace labels that correspond to freespace within an operational environment. freespace annotated data may be generated by combining the one or more freespace labels with second data obtained from a second sensor, with the freespace annotated data corresponding to a viewable area in the operational environment. the viewable area may be determined by tracing one or more rays from the second sensor within the field of view of the second sensor relative to the first data. the freespace annotated data may be input into a machine learning model to train the machine learning model to detect freespace using the second data.
Inventor(s): Pavlo Molchanov of Mountain View CA (US) for nvidia corporation, Jan Kautz of Lexington MA (US) for nvidia corporation, Arash Vahdat of San Mateo CA (US) for nvidia corporation, Hongxu Yin of San Jose CA (US) for nvidia corporation, Paul Micaelli of Edinburgh (GB) for nvidia corporation
IPC Code(s): G06V20/59, G06T7/70, G06V10/82, G06V20/70, G06V40/16
Abstract: landmark detection refers to the detection of landmarks within an image or a video, and is used in many computer vision tasks such emotion recognition, face identity verification, hand tracking, gesture recognition, and eye gaze tracking. current landmark detection methods rely on a cascaded computation through cascaded networks or an ensemble of multiple models, which starts with an initial guess of the landmarks and iteratively produces corrected landmarks which match the input more finely. however, the iterations required by current methods typically increase the training memory cost linearly, and do not have an obvious stopping criteria. moreover, these methods tend to exhibit jitter in landmark detection results for video. the present disclosure improves current landmark detection methods by providing landmark detection using an iterative neural network. furthermore, when detecting landmarks in video, the present disclosure provides for a reduction in jitter due to reuse of previous hidden states from previous frames.
Inventor(s): Shawn Xiao of Santa Clara CA (US) for nvidia corporation, Justin Jiang of Santa Clara CA (US) for nvidia corporation, Henry Li of Santa Clara CA (US) for nvidia corporation, Jerry Zhou of Santa Clara CA (US) for nvidia corporation, Joey Jiao of Santa Clara CA (US) for nvidia corporation
IPC Code(s): H01L23/528, H01L21/56, H01L21/768, H01L23/00, H01L23/29, H01L23/48, H01L23/522, H01L25/16
Abstract: a die including a die body having a first body surface, a second body surface on an opposite side of the die body as the first body surface, an interconnect region adjacent to the first body surface including interconnect dielectric layers with metal lines and vias, a transistor region above the interconnect region, the metal lines and vias making electrical connections to one or more power rails of the transistor region and electrically connected to transistors of the transistor region, a power region above the transistor region including an electro-conductive film on the second body surface and tsvs in the power region, an outer end of the tsv contacting the film and an embedded end of the tsvs contacting one of the power rails. a method of manufacturing an ic package and computer with the ic package are also disclosed.
Inventor(s): Jakob Richard Hoydis of Paris (DE) for nvidia corporation, Sebastain Cammerer of Tuebingen (DE) for nvidia corporation, Alexander Keller of Berlin (DE) for nvidia corporation, Fayçal Aït Aoudia of Saint-Cloud (FR) for nvidia corporation
IPC Code(s): H04B7/0452, G06N3/045, G06N3/084
Abstract: disclosed are apparatuses, systems, and techniques that may use machine learning for determining transmitted signals in communication systems that deploy orthogonal frequency division multiplexing. a system for performing the disclosed techniques includes receiving (rx) antennas to receive rx signals, each rx signal received over a respective resource element of a resource grid. individual resource elements of the resource grid are associated with different radio subcarriers and/or data symbols. the rx signals include a combination of a plurality of transmitted (tx) streams. the system further includes a processing device to process the rx signals using one or more neural network models to determine tx data symbols transmitted via the plurality of tx streams.
20240097774.WIRELESS BEAM SELECTION_simplified_abstract_(nvidia corporation)
Inventor(s): Xingqin Lin of San Jose CA (US) for nvidia corporation
IPC Code(s): H04B7/08
Abstract: apparatuses, systems, and techniques to select one or more beams to transmit signals. in at least one embodiment, a system includes one or more circuits to select one or more wireless signal beams based, at least in part, on measuring one or more received reference signals.
Inventor(s): Xingqin Lin of San Jose CA (US) for nvidia corporation
IPC Code(s): H04L5/00
Abstract: apparatuses, systems, and techniques to transmit configuration information. in at least one embodiment, a processor includes one or more circuits to wirelessly transmit reference signal configuration information corresponding to one or more reference signals.
Inventor(s): Rachel Allen of Arlington VA (US) for nvidia corporation, Gorkem Batmaz of Cambridge (GB) for nvidia corporation, Michael Demoret of Denver CO (US) for nvidia corporation, Ryan Kraus of Cumming GA (US) for nvidia corporation, Hsin Chen of San Jose CA (US) for nvidia corporation, Bartley Richardson of Alexandria VA (US) for nvidia corporation
IPC Code(s): H04L9/40
Abstract: technologies for generating a set of models for each account, where each model is a fine-grained, unsupervised behavior model trained for each user to monitor and detect anomalous patterns are described. an unsupervised training pipeline can generate user models, each being associated with one of multiple accounts and is trained to detect an anomalous pattern using feature data associated with the one account. each account is associated with at least one of a user, a machine, or a service. an inference pipeline can detect a first anomalous pattern in first data associated with a first account using a first user model. the inference pipeline can detect a second anomalous pattern in second data associated with a second account using a second user model.
20240098139.MULTICAST-REDUCTION ASSISTED BY NETWORK DEVICES_simplified_abstract_(nvidia corporation)
Inventor(s): Glenn Dearth of Groton MA (US) for nvidia corporation, Mark Hummel of Franklin MA (US) for nvidia corporation, Nan Jiang of Sudbury MA (US) for nvidia corporation, Gregory Thorson of Eau Claire WI (US) for nvidia corporation
IPC Code(s): H04L67/1008, H04L67/1012, H04L67/1014
Abstract: systems and techniques for performing multicast-reduction operations. in at least one embodiment, a network device receives first network data associated with a multicast operation to be collectively performed by at least a plurality of endpoints. the network device reserves resources to process second network data to be received from the endpoints, and sends the first network data to a plurality of additional network devices. the network device receives the second network data, and processes the second network data using the reserved resources.
20240098216.VIDEO FRAME BLENDING_simplified_abstract_(nvidia corporation)
Inventor(s): Robert Thomas Pottorff of Layton UT (US) for nvidia corporation, Karan Sapra of San Jose CA (US) for nvidia corporation, Zhekun Luo of Santa Clara CA (US) for nvidia corporation, Andrew J. Tao of Los Altos CA (US) for nvidia corporation, Bryan Christopher Catanzaro of Los Altos Hills CA (US) for nvidia corporation
IPC Code(s): H04N7/01, G06T5/50, G06T7/20, G06T7/579, G06T7/70, G06V10/82, H04N19/132
Abstract: apparatuses, systems, and techniques to process image frames. in at least one embodiment, one or more neural networks are used to blend two or more video frames between a first video frame and a second video frame. in at least one embodiment, a blended video frame is used to generate an intermediate video frame between the first video frame and the second video frame.
Inventor(s): Prabindh Sundareson of Bangalore (IN) for nvidia corporation, Sachin Pandhare of Bangalore (IN) for nvidia corporation, Shyam Raikar of Pune (IN) for nvidia corporation
IPC Code(s): H04N19/59, H04N19/105, H04N19/146
Abstract: in various examples, the decoding and upscaling capabilities of a client device are analyzed to determine encoding parameters and operations used by a content streaming server to generate encoded video streams. the quality of the upscaled content of the client device may be monitored by the streaming servers such that the encoding parameters may be updated based on the monitored quality. in this way, the encoding operations of one or more streaming servers may be more effectively matched to the decoding and upscaling abilities of one or more client devise such that an increased number of client devices may be served by the streaming servers.
Inventor(s): Lopamudra Kundu of Sunnyvale CA (US) for nvidia corporation, Timothy James Martin of San Marcos CA (US) for nvidia corporation, Harsha Deepak Banuli Nanje Gowda of Santa Clara CA (US) for nvidia corporation
IPC Code(s): H04W4/70, G06T1/20, H04L67/133, H04W4/40, H04W36/00
Abstract: apparatuses, systems, and techniques to perform one or more apis. in at least one embodiment, a processor is to perform an api to indicate a number of 5g-nr cells that are able to be performed concurrently by one or more processors; a processor is to perform an api to indicate whether one or more processors are able to perform a first number of 5g-nr cells concurrently; a processor comprising one or more circuits is to perform an api to indicate whether one or more resources of one or more processors are allocated to perform 5g-nr cells; and/or a processor comprises one or more circuits to perform an api to indicate one or more techniques to be used by one or more processors in performing one or more 5g-nr cells.
Inventor(s): Ali Heydari of Albany CA (US) for nvidia corporation, Pardeep Shahi of Arlington TX (US) for nvidia corporation
IPC Code(s): H05K7/20, G01F1/34
Abstract: systems and methods include pressure sensors that measure a pressure differential of coolant between a first coolant line and a second coolant line. coolant flow control valves control respective valve flow rates. a processor selects a valve from the flow control valves to provide coolant to a coolant output, responsive to the measured pressure differential.
20240098945.INTELLIGENT TWO-PHASE PUMPED COOLING_simplified_abstract_(nvidia corporation)
Inventor(s): Ali Heydari of Albany CA (US) for nvidia corporation
IPC Code(s): H05K7/20, G06F1/20
Abstract: systems and methods include a first valve that controls a flow rate of a coolant. a processor is configured to set the flow rate of the coolant to a rate that maintains a vapor quality, measured at an outlet of the coolant, within a predetermined quality range.
- NVIDIA Corporation
- G06V10/82
- G06T15/06
- G06T1/20
- G06T7/20
- G06N3/084
- B60W60/00
- B60W30/095
- B60W50/00
- B60W50/14
- Nvidia corporation
- G01R31/3185
- G01R31/317
- G05B13/04
- G06F1/30
- G06F11/07
- G06F1/324
- G06F1/3237
- G06F1/3296
- G06F8/71
- G06F9/445
- G06F8/51
- G06F9/54
- G06F9/48
- G06F12/1081
- G06F9/50
- G06N20/00
- H04N7/01
- G06F15/78
- G06F17/16
- G06F7/544
- G06F40/279
- G06F40/205
- G06F40/55
- G06F40/35
- G06F40/40
- G06F40/284
- G06N3/08
- G06N3/045
- G06N3/04
- H04L41/16
- G06T3/40
- G06T5/00
- G06T5/50
- G06T7/00
- G06F30/10
- G06T15/00
- G06T13/00
- G06F40/20
- G10L15/06
- G10L15/16
- G10L15/18
- G10L15/22
- G06T13/20
- G06V10/25
- G06V10/44
- G06V10/74
- G06V10/771
- G06T15/40
- G06T15/30
- G06T17/20
- G06V10/60
- G06V10/774
- G06V10/764
- G06V10/26
- G06V10/77
- G06V20/56
- G01S13/89
- G01S17/89
- G06V20/59
- G06T7/70
- G06V20/70
- G06V40/16
- H01L23/528
- H01L21/56
- H01L21/768
- H01L23/00
- H01L23/29
- H01L23/48
- H01L23/522
- H01L25/16
- H04B7/0452
- H04B7/08
- H04L5/00
- H04L9/40
- H04L67/1008
- H04L67/1012
- H04L67/1014
- G06T7/579
- H04N19/132
- H04N19/59
- H04N19/105
- H04N19/146
- H04W4/70
- H04L67/133
- H04W4/40
- H04W36/00
- H05K7/20
- G01F1/34
- G06F1/20
