NVIDIA Corporation patent applications on June 27th, 2024
Patent Applications by NVIDIA Corporation on June 27th, 2024
NVIDIA Corporation: 11 patent applications
NVIDIA Corporation has applied for patents in the areas of G06F9/30 (2), G06F3/06 (1), H04W72/21 (1), H04W72/1263 (1), H04W72/044 (1) G06F3/0655 (1), G06F9/3004 (1), G06F15/17331 (1), G06N3/08 (1), G06T15/08 (1)
With keywords such as: data, memory, network, optical, systems, configuration, receiver, methods, processing, and fec in patent application abstracts.
Patent Applications by NVIDIA Corporation
20240211166.HIERARCHICAL NETWORK FOR STACKED MEMORY SYSTEM_simplified_abstract_(nvidia corporation)
Inventor(s): William James Dally of Incline Village NV (US) for nvidia corporation, Carl Thomas Gray of Apex NC (US) for nvidia corporation, Stephen W. Keckler of Austin TX (US) for nvidia corporation, James Michael O'Connor of Austin TX (US) for nvidia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. the processor die includes multiple processing tiles that are stacked with the one or more memory die. the memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. the hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. the ratio of memory bandwidth (byte) to floating-point operation (b:f) may improve 50� for accessing the local memory block compared with conventional memory. additionally, the energy consumed to transfer each bit may be reduced by 10�.
Inventor(s): Ronald Charles BABICH, JR. of Murrysville PA (US) for nvidia corporation, John BURGESS of Austin TX (US) for nvidia corporation, Jack CHOQUETTE of Palo Alto CA (US) for nvidia corporation, Tero KARRAS of Uusimaa (FI) for nvidia corporation, Samuli LAINE of Uusimaa (FI) for nvidia corporation, Ignacio LLAMAS of Palo Alto CA (US) for nvidia corporation, Gregory MUTHLER of Austin TX (US) for nvidia corporation, William Parsons NEWHALL, JR. of Woodside CA (US) for nvidia corporation
IPC Code(s): G06F9/30, G06F9/38, G06F9/48, G06F15/163, G06T1/20, G06T1/60
CPC Code(s): G06F9/3004
Abstract: systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a gpu are provided. according to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.
Inventor(s): Ryan Olson of Golden CO (US) for nvidia corporation, Michael Demoret of Denver CO (US) for nvidia corporation, Bartley Richardson of Alexandria VA (US) for nvidia corporation
IPC Code(s): G06F15/173, G06F9/30, H04L67/025, H04L67/1097
CPC Code(s): G06F15/17331
Abstract: technologies for enabling downstream components to update upstream states in streaming pipelines are described. one method of a first computing device receives a remote promise object assigned to a first serialized object from a second computing device in the data center over a network fabric. the remote promise object uniquely identifies a first contiguous block of the first serialized object stored in a memory associated with the second computing device. the method obtains contents of the first contiguous block and sends contents of a second serialized object back to the second computing device to release the remote promise object.
Inventor(s): Neeraj Sajjan of Sunnyvale CA (US) for nvidia corporation, Mehmet Kocamaz of San Jose CA (US) for nvidia corporation, Parthiv Parikh of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06N3/08
CPC Code(s): G06N3/08
Abstract: in various examples, systems and methods are disclosed relating to determining associations between objects represented in sensor data and predicted states of the objects in multi-sensor systems such as autonomous or semi-autonomous vehicle perception systems. systems and methods are disclosed that employ neural network models, such as multi-layer perceptron (mlp) models or other deep neural network (dnn) models, in learning association costs between sensor measurements and predicted states of objects. during training, the systems and methods can generate data for updating parameters of the neural network models such that, during deployment, the neural network models can receive sensor data and predicted states, and provide corresponding association costs.
20240212261.REAL-TIME RENDERING WITH IMPLICIT SHAPES_simplified_abstract_(nvidia corporation)
Inventor(s): Towaki Alan Takikawa of Toronto (CA) for nvidia corporation, Joey Litalien of Quebec (CA) for nvidia corporation, Kangxue Yin of Toronto (CA) for nvidia corporation, Karsten Julian Kreis of Vancover (CA) for nvidia corporation, Charles Loop of Mercer Island WA (US) for nvidia corporation, Morgan McGuire of Waterloo (CA) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation
IPC Code(s): G06T15/08, G06T15/00, G06T17/00
CPC Code(s): G06T15/08
Abstract: systems and methods are described for rendering complex surfaces or geometry. in at least one embodiment, neural signed distance functions (sdfs) can be used that efficiently capture multiple levels of detail (lods), and that can be used to reconstruct multi-dimensional geometry or surfaces with high image quality. an example architecture can represent complex shapes in a compressed format with high visual fidelity, and can generalize across different geometries from a single learned example. extremely small multi-layer perceptrons (mhlps) can be used with an octree-based feature representation for the learned neural sdfs.
20240214028.SIGNALING OVER RC-DOMINATED TRANSMISSION LINES_simplified_abstract_(nvidia corporation)
Inventor(s): John Poulton of Durham NC (US) for nvidia corporation, Sanquan Song of Santa Clara CA (US) for nvidia corporation, Xi Chen of Santa Clara CA (US) for nvidia corporation, Walker Turner of Durham NC (US) for nvidia corporation, Yoshinori Nishi of Santa Clara CA (US) for nvidia corporation, John M. Wilson of Durham NC (US) for nvidia corporation
IPC Code(s): H04B3/04
CPC Code(s): H04B3/04
Abstract: the disclosure provides a signaling link that overcomes or at least reduces the limitations of rc-dominated signaling wires, improving both the bandwidth and the power consumption of signaling circuits. both an ac and a dc signaling link are disclosed. in one example, a signaling link is provided that includes: (1) a transmitter including a passive equalizer, (2) an over-terminated receiver, and (3) a lossy channel having a first end connected to the passive equalizer and a second end connected to the receiver, wherein the lossy channel has a channel characteristic impedance that is lower than a terminating impedance of the passive equalizer and a termination impedance of the receiver.
Inventor(s): Ashkan Seyedi of Atlanta GA (US) for nvidia corporation
IPC Code(s): H04B10/25
CPC Code(s): H04B10/25891
Abstract: apparatuses, devices, modules, cables, and systems are provided for bi-directional optical communication. an example module includes a substrate, a first band pass filter, a first optical transmitter, and a first optical receiver each supported by the substrate. the first optical transmitter is communicably coupled with the first band pass filter and configured to generate optical signals having a first wavelength. the first optical receiver is communicably coupled with the first band pass filter and configured to receive optical signals having a second wavelength. the first band pass filter passes optical signals received from the first optical transmitter having the first wavelength into an optical communication medium and directs optical signals received from the optical communication medium having the second wavelength into the first optical receiver.
Inventor(s): Pervez Mirza Aziz of Dallas TX (US) for nvidia corporation, Vishnu Balan of Saratoga CA (US) for nvidia corporation, Rohit Rathi of Milpitas CA (US) for nvidia corporation
IPC Code(s): H04L1/20, H04L1/00
CPC Code(s): H04L1/203
Abstract: technologies for optimizing post-fec bit error rate performance of a forward error correction (fec) system are described. a controller is coupled to an fec circuit and a receiver circuit. the controller receives fec symbol error data from the receiver circuit and determines, using the fec symbol error data, a post-fec correlated performance metric indicative of an estimated post-fec ber of the fec circuit. the controller adjusts, based on the post-fec correlated performance metric, at least one of a fec parameter of the fec circuit or a link parameter of the receiver circuit to decrease the estimated post-fec ber. this improves the post-fec ber performance of the fec circuit.
Inventor(s): Rohith Basavaraja of Bangalore (IN) for nvidia corporation, Vinay Prasad V of Bangalore (IN) for nvidia corporation, Sharath Ramamurthy of Bangalore (IN) for nvidia corporation
IPC Code(s): H04L41/0853, H04L41/0859, H04L41/0869
CPC Code(s): H04L41/0853
Abstract: systems and methods are described for collecting configuration data associated with one or more devices of a network, in association with a configuration of the network. the systems and methods include validating the configuration of the network. validating the configuration includes determining a stability status associated with the network and the configuration. the systems and methods include generating a data record corresponding to the configuration of the network and storing the data record to a data repository. the data record includes the configuration data and results associated with validating the configuration of the network. the systems and methods include generating a second configuration and simulating the second network based on the second configuration. the second configuration includes the one or more devices, one or more second devices included in the data repository, or both.
20240214931.DISCONTINUOUS TRANSMISSION DETECTION_simplified_abstract_(nvidia corporation)
Inventor(s): Yan Huang of Santa Clara CA (US) for nvidia corporation, Xiangguo Tang of Pleasanton CA (US) for nvidia corporation, James Hansen Delfeld of Austin TX (US) for nvidia corporation, Christian Ibars Casas of San Jose CA (US) for nvidia corporation
IPC Code(s): H04W52/02, H04W72/044, H04W72/1263, H04W72/21
CPC Code(s): H04W52/0229
Abstract: apparatuses, systems, and techniques to detect whether fifth-generation new radio (5g-nr) devices are transmitting data. in at least one embodiment, a receiver detects whether 5g-nr devices are transmitting 5g-nr signals based on a number of 5g-nr devices sharing a same time and frequency.
20240215205.DUAL-MODE DATACENTER COOLING SYSTEM_simplified_abstract_(nvidia corporation)
Inventor(s): Pardeep Shahi of Arlington TX (US) for nvidia corporation, Ali Heydari of Napa CA (US) for nvidia corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20781
Abstract: a system includes one or more first cooling loops to cool one or more first components within one or more servers having a first power density, and one or more second cooling loops to cool one or more second components within the one or more servers having a second power density. the system can flow first coolant to cold plates to cool high-power server components and flow second coolant to cool low-power server components by immersion cooling.
- NVIDIA Corporation
- G06F3/06
- CPC G06F3/0655
- Nvidia corporation
- G06F9/30
- G06F9/38
- G06F9/48
- G06F15/163
- G06T1/20
- G06T1/60
- CPC G06F9/3004
- G06F15/173
- H04L67/025
- H04L67/1097
- CPC G06F15/17331
- G06N3/08
- CPC G06N3/08
- G06T15/08
- G06T15/00
- G06T17/00
- CPC G06T15/08
- H04B3/04
- CPC H04B3/04
- H04B10/25
- CPC H04B10/25891
- H04L1/20
- H04L1/00
- CPC H04L1/203
- H04L41/0853
- H04L41/0859
- H04L41/0869
- CPC H04L41/0853
- H04W52/02
- H04W72/044
- H04W72/1263
- H04W72/21
- CPC H04W52/0229
- H05K7/20
- CPC H05K7/20781
