NVIDIA Corporation patent applications on June 20th, 2024
Patent Applications by NVIDIA Corporation on June 20th, 2024
NVIDIA Corporation: 14 patent applications
NVIDIA Corporation has applied for patents in the areas of G06T1/20 (3), G06F9/54 (3), B60W60/00 (2), G10L25/30 (1), H04W52/54 (1) B60W60/001 (1), B60W60/0011 (1), G06F1/12 (1), G06T1/20 (1), G06T7/20 (1)
With keywords such as: generation, object, information, fifth, new, radio, packaging, synchronization, management, and techniques in patent application abstracts.
Patent Applications by NVIDIA Corporation
20240199068.OBJECT POSE ESTIMATION_simplified_abstract_(nvidia corporation)
Inventor(s): Marco Pavone of San Jose CA (US) for nvidia corporation, Heng Yang of Cambridge MA (US) for nvidia corporation
IPC Code(s): B60W60/00, B60W50/00, G06T7/73
CPC Code(s): B60W60/001
Abstract: apparatuses, systems, and techniques to obtain prediction set(s) (e.g., region(s)) for keypoint prediction(s) based at least in part on data associated with an object, compute a set of candidate poses for the object based at least in part on the prediction set(s), and estimate an estimated object pose based at least in part on the set of candidate poses. the estimated object pose may be used to move a device. for example the estimated object pose may be used to provide collision-free motion generation for a real-world or virtual device (e.g., a robot, an autonomous machine, or a semi-autonomous machine). in at least one embodiment, at least a portion of the object pose estimation and/or at least a portion of the collision-free motion generation is performed in parallel.
Inventor(s): Sushant Veer of Santa Clara CA (US) for nvidia corporation, Karen Leung of Santa Clara CA (US) for nvidia corporation, Ryan Cosner of Altadena CA (US) for nvidia corporation, Yuxiao Chen of Santa Clara CA (US) for nvidia corporation, Marco Pavone of Santa Clara CA (US) for nvidia corporation
IPC Code(s): B60W60/00, B60W40/02
CPC Code(s): B60W60/0011
Abstract: autonomous vehicles (avs) may need to contend with conflicting traveling rules and the av controller would need to select the least objectionable control action. a rank-preserving reward function can be applied to trajectories derived from a rule hierarchy. the reward function can be correlated to a robustness vector derived for each trajectory. thereby the highest ranked rules would result in the highest reward, and the lower ranked rules would result in lower reward. in some aspects, one or more optimizers, such as a stochastic optimizer can be utilized to improve the results of the reward calculation. in some aspects, a sigmoid function can be applied to the calculation to smooth out the step function used to calculate the robustness vector. the preferred trajectory selected using the results from the reward function can be communicated to an av controller for implementation as a control action.
Inventor(s): Joseph Boccuzzi of Houston TX (US) for nvidia corporation, Lopamudra Kundu of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G06F1/12, G06F9/54
CPC Code(s): G06F1/12
Abstract: apparatuses, systems, and techniques including apis to enable one or more fifth generation new radio (5g-nr) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. for example, a processor comprising one or more circuits to perform an application programming interface (api) to cause fifth generation new radio (5g-nr) packaging, synchronization, or management information to be indicated to one or more accelerators.
Inventor(s): Sau Yan Keith Li of San Jose CA (US) for nvidia corporation, Seth Schneider of San Jose CA (US) for nvidia corporation, Cody Robson of Portland OR (US) for nvidia corporation, Lars Nordskog of Corte Madera CA (US) for nvidia corporation, Charles Hansen of San Francisco CA (US) for nvidia corporation, Rouslan Dimitrov of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T1/20, G06F9/38, G06F9/48
CPC Code(s): G06T1/20
Abstract: a weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. the processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. a first largest weighted average execution time associated with one of the plurality of execution stages is determined. a delay to the initial execution stage prior to processing a first next frame is applied. the delay is determined based on the first largest weighted average execution time.
Inventor(s): Joonhwa Shin of Santa Clara CA (US) for nvidia corporation, Fangyu Li of San Jose CA (US) for nvidia corporation, Hugo Maxence Verjus of Zurich (CH) for nvidia corporation, Zheng Liu of Los Altos CA (US) for nvidia corporation, Kaustubh Purandare of San Jose CA (US) for nvidia corporation
IPC Code(s): G06T7/20, G06V10/74
CPC Code(s): G06T7/20
Abstract: a first visual appearance descriptor associated with a first object in an environment is obtained based on a first set of images of a first time period. the first object is subsequently absent from the environment in a second set of images of a second time period. a second visual appearance descriptor associated with a second object is obtained based on a third set of images, of a third time period subsequent to the second time period. a compound similarity metric between the first and second objects is obtained in view of visual appearance similarity and motion similarity metrics. the visual appearance similarity metric corresponds to a degree of similarity between the first and second visual appearance descriptors. an identifier associated with the second object is updated to correspond to an identifier associated with the first object in response to determining that the compound similarity metric meets a threshold value.
Inventor(s): Marco Foco of Origlio (CH) for nvidia corporation, András Bódis-Szomorú of Zurich (CH) for nvidia corporation, Isaac Deutsch of Zurich (CH) for nvidia corporation, Artem Rozantsev of Zurich (CH) for nvidia corporation, Michael Shelley of Munich (DE) for nvidia corporation, Gavriel State of Toronto (CA) for nvidia corporation, Jiehan Wang of Toronto (CA) for nvidia corporation, Anita Hu of New Market (CA) for nvidia corporation, Jean-Francois Lafleche of Toronto (CA) for nvidia corporation
IPC Code(s): G06T17/20, G06T7/33, G06V10/82
CPC Code(s): G06T17/20
Abstract: approaches presented herein can provide for the automatic generation of a digital representation of an environment that may include multiple objects of various object types. an initial representation (e.g., a point cloud) of the environment can be generated from registered image or scan data, for example, and objects in the environment can be segmented and identified based at least on that initial representation. for objects that are recognized based on these segmentations, stored accurate representations can be substituted for those objects in the representation of the environment, and if no such model is available then a mesh or other representation of that object can be generated and positioned in the environment. a result can then include a 3d representation of a scene or environment in which objects are identified and segmented as individual objects, and representations of the scene or environment can be viewed, and interacted with, through various viewports, positions, and perspectives.
Inventor(s): Suchitra Mandar JJoshi of Pune (IN) for nvidia corporation, Mihir Manohar Nyayate of Pune (IN) for nvidia corporation, Nitin Mahesh Gode of Pune (IN) for nvidia corporation
IPC Code(s): G10L21/14, G10L21/0232, G10L25/30
CPC Code(s): G10L21/14
Abstract: systems and methods described relate to the enhancement of audio, such as through machine learning-based audio super-resolution processing. an efficient resampling approach can be used for audio data received at a lower frequency than is needed for an audio enhancement neural network. this audio data can be converted into the frequency domain using, and once in the frequency domain (e.g., represented using a spectrogram) this lower frequency data can be resampled to provide a frequency-based representation that is at the target input resolution for the neural network. to keep this resampling process lightweight, the upper frequency bands can be padded with zero value entries (or other such padding values). this resampled, higher frequency spectrogram can be provided as input to the neural network, which can perform an enhancement operation such as audio upsampling or super-resolution.
Inventor(s): Sanquan Song of Los Altos CA (US) for nvidia corporation, Stephen G. Tell of Chapel Hill NC (US) for nvidia corporation, Nikola Nedovic of San Jose CA (US) for nvidia corporation
IPC Code(s): H03L7/099, H03L7/089
CPC Code(s): H03L7/099
Abstract: a glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. the device further includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.
Inventor(s): Dhruva Lakshmana Rao Batni of Bothell WA (US) for nvidia corporation
IPC Code(s): H04L9/40, H04W12/08
CPC Code(s): H04L63/107
Abstract: disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of processing of authorization requests by cloud-based access servers that evaluate access rights to access various cloud-based services. the techniques include but are not limited to using location tracking data to predict that a user is to move from an area served by a first access point of the cloud-based services to an area served by a second access point of the cloud-based services. the techniques further include proactively providing policy data and policy dependencies to the second access point to minimize latency of processing of access requests generated by the user.
Inventor(s): Joseph Boccuzzi of Houston TX (US) for nvidia corporation, Lopamudra Kundu of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): H04L67/133, G06T1/20
CPC Code(s): H04L67/133
Abstract: apparatuses, systems, and techniques including apis to enable one or more fifth generation new radio (5g-nr) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. for example, a processor comprising one or more circuits to perform an application programming interface (api) to cause fifth generation new radio (5g-nr) packaging, synchronization, or management information to be indicated to one or more accelerators.
Inventor(s): Joseph Boccuzzi of Houston TX (US) for nvidia corporation, Lopamudra Kundu of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): H04L69/28, G06F9/52, H04W56/00
CPC Code(s): H04L69/28
Abstract: apparatuses, systems, and techniques including apis to enable one or more fifth generation new radio (5g-nr) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. for example, a processor comprising one or more circuits to perform an application programming interface (api) to cause fifth generation new radio (5g-nr) packaging, synchronization, or management information to be indicated to one or more accelerators.
Inventor(s): Joseph Boccuzzi of Houston TX (US) for nvidia corporation, Lopamudra Kundu of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): H04W28/06, G06F9/54
CPC Code(s): H04W28/06
Abstract: apparatuses, systems, and techniques including apis to enable one or more fifth generation new radio (5g-nr) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. for example, a processor comprising one or more circuits to perform an application programming interface (api) to cause fifth generation new radio (5g-nr) packaging, synchronization, or management information to be indicated to one or more accelerators.
Inventor(s): Joseph Boccuzzi of Houston TX (US) for nvidia corporation, Lopamudra Kundu of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): H04W28/16, G06F9/54, G06T1/20, H04W52/54
CPC Code(s): H04W28/16
Abstract: apparatuses, systems, and techniques including apis to enable one or more fifth generation new radio (5g-nr) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. for example, a processor comprising one or more circuits to perform an application programming interface (api) to cause fifth generation new radio (5g-nr) packaging, synchronization, or management information to be indicated to one or more accelerators.
Inventor(s): Joseph Boccuzzi of Houston TX (US) for nvidia corporation, Lopamudra Kundu of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): H04W48/18
CPC Code(s): H04W48/18
Abstract: apparatuses, systems, and techniques including apis to enable one or more fifth generation new radio (5g-nr) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. for example, a processor comprising one or more circuits to perform an application programming interface (api) to cause fifth generation new radio (5g-nr) packaging, synchronization, or management information to be indicated to one or more accelerators.
- NVIDIA Corporation
- B60W60/00
- B60W50/00
- G06T7/73
- CPC B60W60/001
- Nvidia corporation
- B60W40/02
- CPC B60W60/0011
- G06F1/12
- G06F9/54
- CPC G06F1/12
- G06T1/20
- G06F9/38
- G06F9/48
- CPC G06T1/20
- G06T7/20
- G06V10/74
- CPC G06T7/20
- G06T17/20
- G06T7/33
- G06V10/82
- CPC G06T17/20
- G10L21/14
- G10L21/0232
- G10L25/30
- CPC G10L21/14
- H03L7/099
- H03L7/089
- CPC H03L7/099
- H04L9/40
- H04W12/08
- CPC H04L63/107
- H04L67/133
- CPC H04L67/133
- H04L69/28
- G06F9/52
- H04W56/00
- CPC H04L69/28
- H04W28/06
- CPC H04W28/06
- H04W28/16
- H04W52/54
- CPC H04W28/16
- H04W48/18
- CPC H04W48/18
