NVIDIA Corporation patent applications on July 4th, 2024
Patent Applications by NVIDIA Corporation on July 4th, 2024
NVIDIA Corporation: 13 patent applications
NVIDIA Corporation has applied for patents in the areas of G06T11/00 (2), G06V10/764 (2), B60W60/00 (1), H01L21/786 (1), H01L23/00 (1) B60W60/0027 (1), G06F9/4887 (1), G06N5/04 (1), G06T7/12 (1), G06T11/001 (1)
With keywords such as: such, content, images, side, network, audio, location, module, vehicle, and device in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Fangkai Yang of Seattle WA (US) for nvidia corporation, David Nister of Bellevue WA (US) for nvidia corporation, Yizhou Wang of San Ramon CA (US) for nvidia corporation, Rotem Aviv of San Diego CA (US) for nvidia corporation, Julia Ng of San Jose CA (US) for nvidia corporation, Birgit Henke of Seattle WA (US) for nvidia corporation, Hon Leung Lee of Bellevue WA (US) for nvidia corporation, Yunfei Shi of Santa Clara CA (US) for nvidia corporation
IPC Code(s): B60W60/00, B60W30/18, G08G1/0967
CPC Code(s): B60W60/0027
Abstract: in various examples, a yield scenario may be identified for a first vehicle. a wait element is received that encodes a first path for the first vehicle to traverse a yield area and a second path for a second vehicle to traverse the yield area. the first path is employed to determine a first trajectory in the yield area for the first vehicle based at least on a first location of the first vehicle at a time and the second path is employed to determine a second trajectory in the yield area for the second vehicle based at least on a second location of the second vehicle at the time. to operate the first vehicle in accordance with a wait state, it may be determined whether there is a conflict between the first trajectory and the second trajectory, where the wait state defines a yielding behavior for the first vehicle.
Inventor(s): Peter Alexander Boonstoppel of Pleasanton CA (US) for nvidia corporation, Michael Cox of Menlo Park CA (US) for nvidia corporation, Daniel Perrin of Fort Collins CO (US) for nvidia corporation
IPC Code(s): G06F9/48, G06F9/50, G06F9/54, G06F11/30, G06F11/34
CPC Code(s): G06F9/4887
Abstract: in various examples, a system is provided for monitoring and controlling program flow in an event-triggered system. a program (e.g., application, algorithm, routine, etc.) may be organized into operational units (e.g., nodes executed by one or more processors), each of which tasked with executing one or more respective events (e.g., tasks) within the larger program. at least some of the events of the larger program may be successively executed in a flow, one after another, using triggers sent directly from one node to the next. in addition, the system of the present disclosure may include a manager that may exchange communications with the nodes to monitor or assess a status of the system (e.g., determine when a node has completed an event) or to control or trigger a node to initiate an event.
Inventor(s): J Wyman of Cary NC (US) for nvidia corporation, Pritish Nahar of Sunnyvale CA (US) for nvidia corporation, Dana Groff of Seattle WA (US) for nvidia corporation
IPC Code(s): G06N5/04, G06N20/00
CPC Code(s): G06N5/04
Abstract: approaches presented herein provide for the management of artificial intelligence (ai)-related resources in a distributed resource environment, such as may be used to support accelerated machine learning (ml) applications on behalf of different users. management functionality can be provided using an ai manager, such as a management service, that can determine the requirements, capabilities, and limitations of various available ai-related components, such as those of a plurality of ai models, engines, and accelerators, as well as the hardware (e.g., graphics processing units (gpus)) that run or make up these ai-related resources. an ai manager can determine a selection and configuration of resources that is not only appropriate for use with a specific ai model, but that can also be optimized for factors such as throughput, resource utilization, and inference latency. an ai manager can ensure compatibility of resources and configuration, and can enforce access control to models and data.
Inventor(s): Zhiding Yu of Cupertino CA (US) for nvidia corporation, Shuaiyi Huang of Greenbelt MD (US) for nvidia corporation, De-An Huang of Cupertino CA (US) for nvidia corporation, Shiyi Lan of Sunnyvale CA (US) for nvidia corporation, Subhashree Radhakrishnan of Milpitas CA (US) for nvidia corporation, Jose M. Alvarez Lopez of Mountain View CA (US) for nvidia corporation, Anima Anandkumar of Pasadena CA (US) for nvidia corporation
IPC Code(s): G06T7/12, G06V10/764, G06V20/70
CPC Code(s): G06T7/12
Abstract: video instance segmentation is a computer vision task that aims to detect, segment, and track objects continuously in videos. it can be used in numerous real-world applications, such as video editing, three-dimensional (3d) reconstruction, 3d navigation (e.g. for autonomous driving and/or robotics), and view point estimation. however, current machine learning-based processes employed for video instance segmentation are lacking, particularly because the densely annotated videos needed for supervised training of high-quality models are not readily available and are not easily generated. to address the issues in the prior art, the present disclosure provides point-level supervision for video instance segmentation in a manner that allows the resulting machine learning model to handle any object category.
Inventor(s): Alex Greenen of Los Altos CA (US) for nvidia corporation, Manuel Kraemer of San Jose CA (US) for nvidia corporation
IPC Code(s): G06T11/00, G06T5/00, G06T7/13, G06V10/82
CPC Code(s): G06T11/001
Abstract: approaches presented herein can utilize a network that learns to generate a set of content tiles that represent a type of content (e.g., texture) and satisfy a set of rules or boundary conditions. the network can be a diffusion network that learns or adapts to the boundary conditions over several iterations. an indication of a type of content, along with a set of noisy prior images, can then be provided as input to the trained diffusion network, which can generate a set of content images. the content images can then be placed using a random (or other) selection process, as long as each selection satisfies the respective boundary conditions. such an approach enables a small number of content tiles to be used for a texture region with a repeatability or pattern that may not be obviously detectable by a typical human viewer.
Inventor(s): Marco Foco of Plainsboro NJ (US) for nvidia corporation, Michael Kass of San Jose CA (US) for nvidia corporation, Gavriel State of Toronto (CA) for nvidia corporation, Artem Rozantsev of Zurich (CH) for nvidia corporation
IPC Code(s): G06T15/20, G06T7/55, G06T11/00, G06V10/764
CPC Code(s): G06T15/205
Abstract: approaches presented herein provide for automatic generation of representative two-dimensional (2d) images for three-dimensional (3d) objects or assets. in generating these 2d images, a set of options is determined such as may relate to viewpoint or other parameters of a virtual camera. a set of sample points is determined from which to generate 2d images of a 3d model, for example, with 2d images being processed using a classifier to determine which of these images generates a classification with highest confidence or probability, individually or with respect to other classifications. the sample point for this selected image can then be used to select nearby sample points as part of a refinement or optimization process, where 2d images can again be generated and processed using a classifier to identify a 2d image with highest classification probability or confidence, which can be selected as representative of the 3d object or asset.
Inventor(s): Boris Ginsburg of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G10L19/018, G10L13/04
CPC Code(s): G10L19/018
Abstract: approaches presented herein provide for insertion of watermarks into synthesized content, such as audio content that may include synthesized speech to appear to be spoken by a digital avatar in a 3d virtual environment. a text-to-speech (tts) generator, such as a trained neural network, can be used to produce synthetic speech audio, which can have an audio watermark inserted therein. this watermark can be detected by a process of a collaborative content generation platform, for example, and an indication can be provided that the content contains synthesized speech. the presence of the audio watermark will generally not be detectable by the human ear during presentation. to make it difficult to remove or modify the watermark, the watermark can be generated using a key or other unique piece of data known only to authorized entities.
Inventor(s): Ronilo Boja of Santa Clara CA (US) for nvidia corporation, Padam Jain of Santa Clara CA (US) for nvidia corporation
IPC Code(s): H01L23/31, H01L21/683, H01L21/768, H01L21/786, H01L23/00, H01L23/36, H01L23/498, H01L25/10
CPC Code(s): H01L23/3121
Abstract: an integrated circuit package including a package substrate including a monolithic core, the monolithic core having a first substrate side, a second substrate side opposite the first substrate side, a thickness in a range from 800 to 2000 microns and a through-cavity that passes through the first and second substrate sides. the package includes a device module, the device module having a first module side and a second module side opposite the first module side. the device module is embedded in the through-cavity, the first module side is aligned with the first substrate side, the second module side is aligned with the second substrate side, and the device module includes one or more silicon-based passive or silicon-based active device component. a method of manufacture of the integrated circuit package is also disclosed.
Inventor(s): Padam Jain of Santa Clara CA (US) for nvidia corporation, Ronilo Boja of Santa Clara CA (US) for nvidia corporation
IPC Code(s): H01L23/427, H01L21/48, H01L23/433
CPC Code(s): H01L23/427
Abstract: an ic package including an ic and a tim assembly located on the ic. the tim assembly includes a lid defining a compartment, a mixed-phase material located in the compartment, the mixed-phase material including nanostructures, and a liquid metal occupying open spaces in the compartment that are not occupied by the nanostructures. a method of manufacturing an ic package, including providing the ic and placing the tim assembly on the ic. a computer having one or more circuits that include the ic package.
Inventor(s): Misel Myrto Papadopoulou of Zurich (CH) for nvidia corporation, Timothy James Martin of San Marcos CA (US) for nvidia corporation
IPC Code(s): H04L1/00, H03M13/00, H03M13/11
CPC Code(s): H04L1/0061
Abstract: apparatuses, systems, and techniques to select fifth-generation (5g) new radio data. in at least one embodiment, a processor includes one or more circuits to select 5g new radio signal information in parallel.
Inventor(s): Yan Huang of Santa Clara CA (US) for nvidia corporation, James Delfeld of Austin TX (US) for nvidia corporation, Yuan Gao of Austin TX (US) for nvidia corporation, Xingqin Lin of San Jose CA (US) for nvidia corporation, Christian Ibars Casas of San Jose CA (US) for nvidia corporation
IPC Code(s): H04L5/00, H04W72/12
CPC Code(s): H04L5/0073
Abstract: apparatuses, systems, and techniques to allocate one or more compute resources to a user device. in at least one embodiment, one or more circuits cause one or more compute resources to be allocated to two or more fifth-generation (5g) radio access network (ran) cells based, at least in part, on interference between the two or more 5g ran cells.
Inventor(s): Sudharsan Dhamal Gopalarathnam of Bothell WA (US) for nvidia corporation
IPC Code(s): H04L45/02
CPC Code(s): H04L45/026
Abstract: approaches in accordance with various illustrative embodiments provide for the management of active connections in a network environment. in particular, various embodiments implement keep alive functionality in components such as network processing units (npus) of network devices such as routers and switches, instead of host processors for those devices. when a status message is received, such as a hello message, the npu can set or refresh a hit bit in a table entry for a given connection with a peer device. if a subsequent status message is not received within a keep alive interval of the last received status message, then the npu can determine that the connection with the peer device is stale and can inform the host processor that the connection is no longer available for routing network traffic. the status messages are terminated in the npu and prevented from being received and processed by the host processor.
Inventor(s): Michael Stengel of Santa Clara CA (US) for nvidia corporation, Ward Lopes of Santa Clara CA (US) for nvidia corporation, Joohwan Kim of Santa Clara CA (US) for nvidia corporation, David Luebke of Santa Clara CA (US) for nvidia corporation
IPC Code(s): H04S7/00, G01S17/86, G01S17/89
CPC Code(s): H04S7/40
Abstract: the disclosure provides a method for audio calibration that uses audio simulation and reconstructed surface information from images or video recordings along with recorded sound. the surface component of the method introduces knowledge that enables audio wave propagation simulation for a particular location. using the simulation results the sound distribution can be optimized. for example, unwanted audio reflection and occlusion can be recognized and resolved. in one example, the disclosure provides a method for improving acoustics at a location that includes: (1) generating a geometric model of a location using visual data obtained from the location, wherein the location includes an audio system, and (2) simulating, using the geometric model, movement of sound waves in the location that originate from the audio system. the disclosure also provides a computer system, a computer program product, and a mobile computing device that include features for improving acoustics at a location.
- NVIDIA Corporation
- B60W60/00
- B60W30/18
- G08G1/0967
- CPC B60W60/0027
- Nvidia corporation
- G06F9/48
- G06F9/50
- G06F9/54
- G06F11/30
- G06F11/34
- CPC G06F9/4887
- G06N5/04
- G06N20/00
- CPC G06N5/04
- G06T7/12
- G06V10/764
- G06V20/70
- CPC G06T7/12
- G06T11/00
- G06T5/00
- G06T7/13
- G06V10/82
- CPC G06T11/001
- G06T15/20
- G06T7/55
- CPC G06T15/205
- G10L19/018
- G10L13/04
- CPC G10L19/018
- H01L23/31
- H01L21/683
- H01L21/768
- H01L21/786
- H01L23/00
- H01L23/36
- H01L23/498
- H01L25/10
- CPC H01L23/3121
- H01L23/427
- H01L21/48
- H01L23/433
- CPC H01L23/427
- H04L1/00
- H03M13/00
- H03M13/11
- CPC H04L1/0061
- H04L5/00
- H04W72/12
- CPC H04L5/0073
- H04L45/02
- CPC H04L45/026
- H04S7/00
- G01S17/86
- G01S17/89
- CPC H04S7/40
