NVIDIA Corporation patent applications on July 11th, 2024
Patent Applications by NVIDIA Corporation on July 11th, 2024
NVIDIA Corporation: 18 patent applications
NVIDIA Corporation has applied for patents in the areas of G06T3/40 (3), G06V10/82 (3), G06V10/762 (2), G06N20/00 (2), G06N3/08 (2) B60W50/0205 (1), G06T7/11 (1), G10L15/16 (1), G06V20/54 (1), G06V10/56 (1)
With keywords such as: processing, data, image, various, used, audio, include, test, examples, and device in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Anitha Kalva of San Jose CA (US) for nvidia corporation, Jae Wu of Los Gatos CA (US) for nvidia corporation, Shantanu Sarangi of Saratoga CA (US) for nvidia corporation, Sailendra Chadalavada of Saratoga CA (US) for nvidia corporation, Milind Sonawane of Santa Clara CA (US) for nvidia corporation, Chen Fang of Shanghai (CN) for nvidia corporation, Abilash Nerallapally of Newark CA (US) for nvidia corporation
IPC Code(s): B60W50/02
CPC Code(s): B60W50/0205
Abstract: systems and methods are disclosed that relate to testing processing elements of an integrated processing system. a first system test may be performed on a first processing element of an integrated processing system. the first system test may be based at least on accessing a test node associated with the first processing element. the first system test may be accessed using a first local test controller. a second system test may be performed on a second processing element of the integrated processing system. the second system test may be based at least on accessing a second test node associated with the second processing element. the second system test may be accessed using a second local test controller.
Inventor(s): Trung Pham of Santa Clara CA (US) for nvidia corporation, Hang Dou of Fremont CA (US) for nvidia corporation, Berta Rodriguez Hervas of San Francisco CA (US) for nvidia corporation, Minwoo Park of Saratoga CA (US) for nvidia corporation, Neda Cvijetic of East Palo Alto CA (US) for nvidia corporation, David Nister of Bellevue CA (US) for nvidia corporation
IPC Code(s): G01C21/26, G06N3/04, G06N3/08, G06V10/44, G06V10/46, G06V10/764, G06V10/82, G06V20/56
CPC Code(s): G01C21/26
Abstract: in various examples, live perception from sensors of a vehicle may be leveraged to generate potential paths for the vehicle to navigate an intersection in real-time or near real-time. for example, a deep neural network (dnn) may be trained to compute various outputs—such as heat maps corresponding to key points associated with the intersection, vector fields corresponding to directionality, heading, and offsets with respect to lanes, intensity maps corresponding to widths of lanes, and/or classifications corresponding to line segments of the intersection. the outputs may be decoded and/or otherwise post-processed to reconstruct an intersection—or key points corresponding thereto—and to determine proposed or potential paths for navigating the vehicle through the intersection.
Inventor(s): Shridhar Rasal of Pune (IN) for nvidia corporation, Oren Duer of Kohav Yair (IL) for nvidia corporation, Aviv Kfir of Nili (IL) for nvidia corporation, Liron Mula of Hertzlia (IL) for nvidia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: a system includes a hardware circuitry having a device coupled with one or more external memory devices. the device is to detect an input/output (i/o) request associated with an external memory device of the one or more external memory devices. the device is to record a first timestamp in response to detecting the i/o request transmitted to the external memory device. the device is further to detect an indication from the external memory device of a completion of the i/o request associated with the external memory device and record a second timestamp in response to detecting the indication. the device is also to determine a latency associated with the i/o request based on the first timestamp and the second timestamp.
20240231830. WORKLOAD ASSIGNMENT TECHNIQUE_simplified_abstract_(nvidia corporation)
Inventor(s): Federico Busato of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06F9/38
CPC Code(s): G06F9/3824
Abstract: apparatuses, systems, and techniques to distribute workloads in parallel computing. in at least one embodiment, threads of a group are assigned equal numbers of items based, at least in part, on locations of non-zero values in a data structure that contains mostly zeros.
Inventor(s): Jason Lavar CLEMONS of Leander TX (US) for nvidia corporation, Kavya SREEDHAR of Oakland CA (US) for nvidia corporation
IPC Code(s): G06F9/50, G06N20/00
CPC Code(s): G06F9/5038
Abstract: techniques are disclosed herein for allocating computational resources when executing trained machine learning models. the techniques include determining one or more available computational resources that are usable by one or more trained machine learning models to perform one or more tasks, allocating one or more computational resources to the one or more tasks based on the one or more available computational resources and one or more performance requirements associated with the one or more tasks, and causing the one or more trained machine learning models to perform the one or more tasks using the one or more computational resources allocated to the one or more tasks.
Inventor(s): Ronald N. Isaac of San Ramon CA (US) for nvidia corporation
IPC Code(s): G06F11/34, G06N20/00
CPC Code(s): G06F11/3409
Abstract: apparatuses, systems, and techniques for assigning execution of applications to various processing units using machine learning are disclosed herein. usage data for an application to be executed using a computing system including an integrated processing unit and a discrete processing unit is identified. at least a portion of operations of the application to be executed using the integrated processing unit or the discrete processing unit based on the usage data and in view of at least one of one or more system performance metrics or one or more user experience metrics associated with executing the application using the integrated processing unit and the discrete processing unit.
Inventor(s): Saumya Nair of Bangalore (IN) for nvidia corporation, Yogesh Kini of Bangalore (IN) for nvidia corporation, Ashutosh Jain of SPSR Nellore (IN) for nvidia corporation, Neeraja Gubba of Bangalore (IN) for nvidia corporation
IPC Code(s): G06F11/36
CPC Code(s): G06F11/3644
Abstract: one or more embodiments of the present disclosure relate to executing a software testing tool to identify function calls—internal and/or external—of software code and their corresponding errors. once identified—such as during an information gathering operation—the error codes may be returned in place of actual outputs of the function during testing, and the downstream processing of the software as a result of the errors may be evaluated. as such, an automatic software testing tool may be implemented that not only identifies functions calls and corresponding errors, but also evaluates performance of the software in view of the various different error types associated with the function calls.
Inventor(s): Lucien Dunning of Ramsey NJ (US) for nvidia corporation, Seth Schneider of San Jose CA (US) for nvidia corporation, Dwayne Swoboda of San Jose CA (US) for nvidia corporation, Marko Mitic of San Jose CA (US) for nvidia corporation, Adam Zabrocki of Kings Park NY (US) for nvidia corporation
IPC Code(s): G06F21/57, A63F13/73
CPC Code(s): G06F21/57
Abstract: in examples, a vm may receive and aggregate a first attestation report corresponding to a
Inventor(s): Lucien Dunning of Ramsey NJ (US) for nvidia corporation, Seth Schneider of San Jose CA (US) for nvidia corporation, Dwayne Swoboda of San Jose CA (US) for nvidia corporation, Marko Mitic of San Jose CA (US) for nvidia corporation, Adam Zabrocki of Kings Park NY (US) for nvidia corporation
IPC Code(s): G06F21/57, A63F13/73
CPC Code(s): G06F21/57
Abstract: cpu and a second attestation report corresponding to a gpu. the aggregated data may be provided to an attestation service, which may verify the attestation reports indicate a tcb is to include the vm and gpu state data and is to isolate the gpu state data and the vm from an untrusted host os. based at least on the tcb being verified, the vm may perform one or more operations using the tcb. the tcb may include a trusted hypervisor to isolate the vm and gpu state data within the gpu(s) from the untrusted host os. the trusted hypervisor may prevent the host os from accessing device memory assigned to the vm based at least on controlling an iommu and/or second-level address translation (slat) used to access the data.
Inventor(s): Yilin Yang of Santa Clara CA (US) for nvidia corporation, Bala Siva Sashank Jujjavarapu of Sunnyvale CA (US) for nvidia corporation, Pekka Janis of Uusimaa (FI) for nvidia corporation, Zhaoting Ye of Santa Clara CA (US) for nvidia corporation, Sangmin Oh of San Jose CA (US) for nvidia corporation, Minwoo Park of Saratoga CA (US) for nvidia corporation, Daniel Herrera Castro of Uusimaa (FI) for nvidia corporation, Tommi Koivisto of Uusimaa (FI) for nvidia corporation, David Nister of Bellevue WA (US) for nvidia corporation
IPC Code(s): G06N3/08, B60W30/14, B60W60/00, G06F18/214, G06V10/762, G06V20/56
CPC Code(s): G06N3/08
Abstract: in various examples, a deep neural network (dnn) is trained to accurately predict, in deployment, distances to objects and obstacles using image data alone. the dnn may be trained with ground truth data that is generated and encoded using sensor data from any number of depth predicting sensors, such as, without limitation, radar sensors, lidar sensors, and/or sonar sensors. camera adaptation algorithms may be used in various embodiments to adapt the dnn for use with image data generated by cameras with varying parameters—such as varying fields of view. in some examples, a post-processing safety bounds operation may be executed on the predictions of the dnn to ensure that the predictions fall within a safety-permissible range.
Inventor(s): Steen KRISTENSEN of Santa Clara CA (US) for nvidia corporation, Simon KIEFHABER of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T3/40, G06F3/01
CPC Code(s): G06T3/4038
Abstract: in various examples, a stitched image may be generated from overlapping image frames using a dynamic seam placement that depends on scene content and/or other factors. since an optimized seam placement may jump from a previous location from time slice to time slice, one or more constraints may be applied to limit the movement of dynamically placed seams such that any given seam moves gradually over time, limiting potential discontinuities in a visualization of the stitched image on a display. eye tracking may be used to detect a saccade of a monitored person and/or detect that the monitored person is not looking at the display, and one or more of the constraints used to limit the movement of dynamically placed seams may be relaxed or lifted when the monitored person is experiencing a saccade and/or is looking away from the display.
Inventor(s): Shekhar Dwivedi of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T7/11, G06T7/187, G06V10/36, G06V10/94
CPC Code(s): G06T7/11
Abstract: apparatuses, systems, and techniques for improved object detection and/or segmentation are disclosed. in at least one embodiment, an object is detected in input data via iterative transformation and processing of the input data and aggregation of a result of each iteration into a combined object detection result.
Inventor(s): Kenneth Turkowski of Menlo Park CA (US) for nvidia corporation
IPC Code(s): G06T7/30, G06T3/00, G06T3/40, G06V10/44, G06V10/82
CPC Code(s): G06T7/30
Abstract: in various examples, systems and methods are disclosed relating to registering image processing with image registration for image generation and content stream applications. systems and methods are disclosed for registering portions of images that are modified to incorporate content or features, with references images from which the portions of the images are identified. the systems and methods can transform the modified portions to more realistically and precisely merge back into the reference images, such as for presentation as a content stream.
Inventor(s): Evgeny Aleksandrovich Tumanov of Moscow (RU) for nvidia corporation, Dmitry Aleksandrovich Korobchenko of Moscow (RU) for nvidia corporation, Simon Yuen of Playa Vista CA (US) for nvidia corporation, Kevin Margo of Los Gatos CA (US) for nvidia corporation
IPC Code(s): G06T13/20, G06T13/40
CPC Code(s): G06T13/205
Abstract: in various examples, animations may be generated using audio-driven body animation synthesized with voice tempo. for example, full body animation may be driven from an audio input representative of recorded speech, where voice tempo (e.g., a number of phonemes per unit time) may be used to generate a 1d audio signal for comparing to datasets including data samples that each include an animation and a corresponding 1d audio signal. one or more loss functions may be used to compare the 1d audio signal from the input audio to the audio signals of the datasets, as well as to compare joint information of joints of an actor between animations of two or more data samples, in order to identify optimal transition points between the animations. the animations may then be stitched together—e.g., using interpolation and/or a neural network trained to seamlessly stitch sequences together—using the transition points.
Inventor(s): Tianyi Zhang of Santa Clara CA (US) for nvidia corporation, Blagovest Borislavov Taskov of Saratoga CA (US) for nvidia corporation
IPC Code(s): G06T15/50, G06T15/06
CPC Code(s): G06T15/506
Abstract: light transport simulation algorithms or techniques may be used to generate a sample for a subsurface scattering of light, then a target function may be used to improve the sample. the target function may correspond to an amount of energy transported to the surface from within the object. the sample may be resampled using the sample and the target function to update a reservoir of samples. a resampled sample may be selected and used as a lighting sample for the subsurface scattering. rather than using the resampled sample, it may be used with the target function to again update the reservoir and select another resampled sample from the updated reservoir. this may be performed for any number of iterations to determine the lighting sample for the frame. a backside lighting cache may be used in the ray tracing to determine lighting at the backside of the object.
Inventor(s): Andrew Russell of Weston FL (US) for nvidia corporation, Prabindh Sundareson of Bangalore (IN) for nvidia corporation
IPC Code(s): G06V10/56, G06T3/40, G06T7/13, G06T7/90
CPC Code(s): G06V10/56
Abstract: in various examples, processing pipelines for removing artifacts from images are described herein. systems and methods are disclosed that use one or more multi-pass techniques to identify and process areas in an image that have artifacts. for instance, using a series of forward passes, the image is processed to generate multiple levels of images, where the levels of images are used to identify at least areas of the original image that include artifacts and areas of the original image that include true color edges. next, using a series of backward passes, processing is performed on color values associated with the areas that include artifacts to determine new color values for the pixels within the areas. in some examples, dithering may then be performed on the new color values to distribute errors in quantization across the pixels and remove the artifacts.
Inventor(s): Parthasarathy Sriram of Los Altos CA (US) for nvidia corporation, Ratnesh Kumar of Campbell CA (US) for nvidia corporation, Farzin Aghdasi of East Palo Alto CA (US) for nvidia corporation, Arman Toorians of San Jose CA (US) for nvidia corporation, Milind Naphade of Cupertino CA (US) for nvidia corporation, Sujit Biswas of San Jose CA (US) for nvidia corporation, Vinay Kolar of Cupertino CA (US) for nvidia corporation, Bhanu Pisupati of Santa Clara CA (US) for nvidia corporation, Aaron Bartholomew of San Francisco CA (US) for nvidia corporation
IPC Code(s): G06V20/54, G06F18/231, G06F18/2413, G06T7/246, G06T7/292, G06T7/70, G06T7/73, G06V10/147, G06V10/20, G06V10/25, G06V10/762, G06V10/764, G06V10/82, G06V20/52, G06V20/58, G06V20/62, G06V40/20, H04N23/90
CPC Code(s): G06V20/54
Abstract: the present disclosure provides various approaches for smart area monitoring suitable for parking garages or other areas. these approaches may include roi-based occupancy detection to determine whether particular parking spots are occupied by leveraging image data from image sensors, such as cameras. these approaches may also include multi-sensor object tracking using multiple sensors that are distributed across an area that leverage both image data and spatial information regarding the area, to provide precise object tracking across the sensors. further approaches relate to various architectures and configurations for smart area monitoring systems, as well as visualization and processing techniques. for example, as opposed to presenting video of an area captured by cameras, 3d renderings may be generated and played from metadata extracted from sensors around the area.
Inventor(s): Vladimir Bataev of Yerevan (AM) for nvidia corporation, Roman Korostik of Yerevan (AM) for nvidia corporation, Evgenii Shabalin of Moskva (RU) for nvidia corporation, Vitaly Sergeyevich Lavrukhin of Campbell CA (US) for nvidia corporation, Boris Ginsburg of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G10L15/16, G10L15/065
CPC Code(s): G10L15/16
Abstract: in various examples, first textual data may be applied to a first mlm to generate an intermediate speech representation (e.g., a frequency-domain representation), the intermediate audio representation and a second mlm may be used to generate output data indicating second textual data, and parameters of the second mlm may be updated using the output data and ground truth data associated with the first textual data. the first mlm may include a trained text-to-speech (tts) model and the second mlm may include an automatic speech recognition (asr) model. a generator from a generative adversarial networks may be used to enhance an initial intermediate audio representation generated using the first mlm and the enhanced intermediate audio representation may be provided to the second mlm. the generator may include generator blocks that receive the initial intermediate audio representation to sequentially generate the enhanced intermediate audio representation.
Inventor(s): Jiwang Lee of San Jose CA (US) for nvidia corporation, Jaewon Lee of San Jose CA (US) for nvidia corporation, Hsuche Nee of Zhubei City (TW) for nvidia corporation, Po-Chien Chiang of Hsinchu (TW) for nvidia corporation, Wen-Hung Lo of Saratoga CA (US) for nvidia corporation, Michael Ivan Halfen of San Francisco CA (US) for nvidia corporation, Abhishek Dhir of Oakville (CA) for nvidia corporation
IPC Code(s): H03K19/1776, H03K19/17736, H03K19/17784
CPC Code(s): H03K19/1776
Abstract: a multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (io) channel and a unified receiver coupled to a second end of the shared io channel. the unified receiver is coupled to apply an analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared io channel.
- NVIDIA Corporation
- B60W50/02
- CPC B60W50/0205
- Nvidia corporation
- G01C21/26
- G06N3/04
- G06N3/08
- G06V10/44
- G06V10/46
- G06V10/764
- G06V10/82
- G06V20/56
- CPC G01C21/26
- G06F3/06
- CPC G06F3/0613
- G06F9/38
- CPC G06F9/3824
- G06F9/50
- G06N20/00
- CPC G06F9/5038
- G06F11/34
- CPC G06F11/3409
- G06F11/36
- CPC G06F11/3644
- G06F21/57
- A63F13/73
- CPC G06F21/57
- B60W30/14
- B60W60/00
- G06F18/214
- G06V10/762
- CPC G06N3/08
- G06T3/40
- G06F3/01
- CPC G06T3/4038
- G06T7/11
- G06T7/187
- G06V10/36
- G06V10/94
- CPC G06T7/11
- G06T7/30
- G06T3/00
- CPC G06T7/30
- G06T13/20
- G06T13/40
- CPC G06T13/205
- G06T15/50
- G06T15/06
- CPC G06T15/506
- G06V10/56
- G06T7/13
- G06T7/90
- CPC G06V10/56
- G06V20/54
- G06F18/231
- G06F18/2413
- G06T7/246
- G06T7/292
- G06T7/70
- G06T7/73
- G06V10/147
- G06V10/20
- G06V10/25
- G06V20/52
- G06V20/58
- G06V20/62
- G06V40/20
- H04N23/90
- CPC G06V20/54
- G10L15/16
- G10L15/065
- CPC G10L15/16
- H03K19/1776
- H03K19/17736
- H03K19/17784
- CPC H03K19/1776
