NVIDIA Corporation patent applications on January 30th, 2025
Patent Applications by NVIDIA Corporation on January 30th, 2025
NVIDIA Corporation: 16 patent applications
NVIDIA Corporation has applied for patents in the areas of G06T7/60 (2), G06F9/38 (2), G06N3/084 (2), G06T7/73 (2), G06T17/20 (2) G06T7/73 (2), A63F13/87 (1), B60W60/001 (1), G06F9/3869 (1), G06F11/079 (1)
With keywords such as: information, processing, systems, include, determine, within, such, shape, object, and processor in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Jithin Thomas of Yerwada (IN) for nvidia corporation, Neilesh Chorakhalikar of San Jose CA (US) for nvidia corporation, Ambrish Dantrey of Dhanori (IN) for nvidia corporation, Revanth Reddy Nalla of Viman Nagar (IN) for nvidia corporation, Prakshep Mehta of Wakad (IN) for nvidia corporation
IPC Code(s): A63F13/87, A63F13/355, A63F13/71, A63F13/77, A63F13/79
CPC Code(s): A63F13/87
Abstract: in various examples, game session audio data—e.g., representing speech of users participating in the game—may be monitored and/or analyzed to determine whether inappropriate language is being used. where inappropriate language is identified, the portions of the audio corresponding to the inappropriate language may be edited or modified such that other users do not hear the inappropriate language. as a result, toxic behavior or language within instances of gameplay may be censored—thereby enhancing the user experience and making online gaming environments safer for more vulnerable populations. in some embodiments, the inappropriate language may be reported—e.g., automatically—to the game developer or game application host in order to suspend, ban, or otherwise manage users of the system that have a proclivity for toxic behavior.
Inventor(s): Robin JENKIN of Morgan Hill CA (US) for nvidia corporation, Balaji HOLUR of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): B60W60/00, B60W40/02
CPC Code(s): B60W60/001
Abstract: embodiments of the present disclosure relate to adjusting operating parameters, settings, or configurations of a system based on identified factors corresponding to an environment. in some embodiments, the factors may respectively impact operation of a system and the factors may be weighted based on an amount of impact respectively caused to operation of the system. in some embodiments, the factors may additionally correspond to one or more information classes that may correspond to the environment. the one or more operations may additionally include determining one or more performance ability scores that may respectively correspond to the one or more information classes of the one or more factors. the operations may additionally include generating an overall impact score. further, the operations may include modifying one or more operations of the system based at least on the overall impact score.
Inventor(s): Neal Clayton Crago of Amherst MA (US) for nvidia corporation, Stephen William Keckler of Austin TX (US) for nvidia corporation
IPC Code(s): G06F9/38, G06F8/41, G06T1/20
CPC Code(s): G06F9/3869
Abstract: technology advancements in computer processors, including in particular graphics processing units (gpus), have included the introduction of parallel processing capabilities which offer high compute throughput and memory bandwidth. currently, programmers spend considerable time optimizing their code to best exploit the available parallel processor resources. however, some applications are still unable to consistently attain high compute throughput or memory bandwidth despite the presence of abundant parallelism. the present disclosure provides both hardware and software support for accelerating parallel processing pipelines.
Inventor(s): Vito MAGNANIMO of Munchen (DE) for nvidia corporation, Daniel PERRIN of Fort Collins CO (US) for nvidia corporation, Joy JACOBS of Northville MI (US) for nvidia corporation, Hanne BUUR of Boulder CO (US) for nvidia corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/079
Abstract: embodiments of the present disclosure relate to a method of detecting an error corresponding to a monitored system. the method may additionally include determining whether the error corresponds to a safety module associated with the monitored system that may have one or more operations that are deemed to affect safety or whether the error corresponds to a safety process associated with the monitored system that may have one or more operations that are deemed to affect safety. in some embodiments, the method may additionally include determining whether to continue operations of the monitored system, where the determination may be based at least on whether the error may correspond to a safety module associated with the monitored system or whether the error corresponds to a safety process associated with the monitored system.
20250036954. DISTRIBUTED INFERENCING TECHNIQUE_simplified_abstract_(nvidia corporation)
Inventor(s): Xiaowei Ren of San Jose CA (US) for nvidia corporation, Kevin Chong Man Siu of San Carlos CA (US) for nvidia corporation, Nitin Nitin of Oakland CA (US) for nvidia corporation, Michael Andersch of Potsdam (DE) for nvidia corporation
IPC Code(s): G06N3/084, G06N3/04
CPC Code(s): G06N3/084
Abstract: apparatuses, systems, and techniques to perform neural networks. in at least one embodiment, a processor is to cause information to be distributed to processing cores. in at least one embodiment, a processor is to cause inferencing of two or more contiguous portions of information to be distributed only between two or more respective processing cores.
20250036975. DISTRIBUTED INFERENCING_simplified_abstract_(nvidia corporation)
Inventor(s): Xiaowei Ren of San Jose CA (US) for nvidia corporation, Nitin Nitin of Oakland CA (US) for nvidia corporation, Michael Andersch of Potsdam (DE) for nvidia corporation
IPC Code(s): G06N5/04
CPC Code(s): G06N5/04
Abstract: apparatuses, systems, and techniques to perform neural networks. in at least one embodiment, a processor is to cause information to be distributed to processing cores. in at least one embodiment, a processor is to cause inferencing of two or more contiguous portions of information to be distributed between two or more respective processing cores based, at least in part, on locations of the two or more contiguous portions within the information relative to one or more terminating portions of the information.
Inventor(s): Hanrui WANG of Cambridge MA (US) for nvidia corporation, James Michael O'CONNOR of Austin TX (US) for nvidia corporation, Donghyuk LEE of Cedar Park TX (US) for nvidia corporation
IPC Code(s): G06Q30/0601, G06F16/901, G06F17/16
CPC Code(s): G06Q30/0631
Abstract: one embodiment sets forth a technique for performing matrix operations. the technique includes traversing a tree structure to access one or more non-empty regions within a matrix. the tree structure includes a first plurality of nodes and a second plurality of nodes corresponding to non-empty regions in the matrix. the first plurality of nodes includes a first node representing a first region and one or more second nodes that are children of the first node and represent second region(s) with an equal size formed within the first region. the second plurality of nodes include a third node representing a third region and one or more fourth nodes that are children of the third node and represent fourth region(s) with substantially equal numbers of non-zero matrix values formed within the third region. the technique also includes performing matrix operation(s) based on the non-empty region(s) to generate a matrix operation result.
Inventor(s): Nathan Vollmer Morrical of Salt Lake City UT (US) for nvidia corporation
IPC Code(s): G06T1/20, G06F9/38, G06F9/50, G06T15/10
CPC Code(s): G06T1/20
Abstract: apparatuses, systems, and techniques to perform a k-nearest-neighbor query. in at least one embodiment, a set of bounding boxes corresponding to a set of primitives is generated that allows the query to be solved using light transport simulation acceleration features of a gpu.
Inventor(s): Jiaxing Geng of Beijing (CN) for nvidia corporation, Yu Zhang of Sunnyvale CA (US) for nvidia corporation, Derek Miller of Oceanside CA (US) for nvidia corporation, Lin Yang of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T7/73, G06T7/60
CPC Code(s): G06T7/73
Abstract: in various examples, three-dimensional (3d) object or feature detection and localization for autonomous and semi-autonomous systems and applications is described herein. systems and methods are disclosed that use different types of sensors, such as an image sensor and a lidar sensor, to determine information associated with objects, such as traffic objects (e.g., traffic signs, traffic signals, traffic markings, etc.). to determine the information for an object, image data is processed to determine a bounding shape associated with the object. the bounding shape is then used to determine a 3d shape, such as a frustum, corresponding to the object. additionally, points data generated using the lidar sensor, such as an occupancy map and/or a point cloud, is processed to identify a portion of the points associated with (e.g., located within) the 3d shape. this portion of the points may then be used to determine the information associated with the object.
Inventor(s): Jiaxing Geng of Beijing (CN) for nvidia corporation, Yu Zhang of Sunnyvale CA (US) for nvidia corporation, Derek Miller of Santa Clara CA (US) for nvidia corporation, Lin Yang of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T7/73, G06T7/60
CPC Code(s): G06T7/73
Abstract: in various examples, three-dimensional (3d) object or feature detection and localization for autonomous and semi-autonomous systems and applications is described herein. systems and methods are disclosed that use different types of sensors, such as an image sensor and a lidar sensor, to determine information associated with objects, such as traffic objects (e.g., traffic signs, traffic signals, traffic markings, etc.). to determine the information for an object, image data is processed to determine a bounding shape associated with the object. the bounding shape is then used to determine a 3d shape, such as a frustum, corresponding to the object. additionally, points data generated using the lidar sensor, such as an occupancy map and/or a point cloud, is processed to identify a portion of the points associated with (e.g., located within) the 3d shape. this portion of the points may then be used to determine the information associated with the object.
Inventor(s): Siddhant Pardeshi of Pune (IN) for nvidia corporation, Pranit P. Kothari of Pune (IN) for nvidia corporation, Vinayak Vilas Gaikwad of Pune (IN) for nvidia corporation
IPC Code(s): G06T11/60, G06N3/045, G06N3/084, G06N5/046, G06T7/70, G06V10/774, G06V10/82
CPC Code(s): G06T11/60
Abstract: apparatuses, systems, and techniques are presented to generate image or video content. in at least one embodiment, one or more neural networks are used to add one or more first objects to an image including one or more second objects, wherein one or more poses of the one or more first objects in the image is determined with respect to the one or more second objects.
Inventor(s): Seyedamirhesam SHAHVARANI of Munich (DE) for nvidia corporation, Shankara Rao Thejaswi NANDITALE of Haar (DE) for nvidia corporation
IPC Code(s): G06T17/20, G06F16/22
CPC Code(s): G06T17/20
Abstract: in various examples, systems and methods are disclosed relating to shape processing using parallel computing systems. a processor can map one or more combinations of a plurality of first polygons identified from a first structure and a plurality of second polygons identified from a second structure, to a grid comprising a plurality of cells. the processor can identify one or more occupied cells of the plurality of cells, to which the one or more combinations are mapped. the processor can output a data structure indicative of the plurality of occupied cells.
Inventor(s): Holger Heinrich Gruen of Bavaria (DE) for nvidia corporation
IPC Code(s): G06T17/20, G06T15/20
CPC Code(s): G06T17/205
Abstract: a method, computer readable medium, and system are disclosed for overlaying a cell onto a polygon meshlet. the polygon meshlet may include a grouping of multiple geometric shapes such as triangles, and the cell may include a square-shaped boundary. additionally, every polygon (e.g., a triangle or other geometric shape) within the polygon meshlet that has at least one edge fully inside the cell is removed to create an intermediate meshlet. a selected vertex is determined from all vertices (e.g., line intersections) of the intermediate meshlet that are located within the cell, based on one or more criteria, and all the vertices of the intermediate meshlet that are located within the cell are replaced with the selected vertex to create a modified meshlet. the modified meshlet is then rendered (e.g., as part of a process to generate a scene to be viewed).
Inventor(s): Dhruva Lakshmana Rao Batni of Bothell WA (US) for nvidia corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/102
Abstract: disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of processing of authorization requests by cloud-based access servers that evaluate access rights to access various cloud-based services. the techniques include but are not limited to generating and processing advanced authorization requests that anticipate future authorization requests that may be generated by cloud-based services. the techniques further include processing of frequently accessed policies and policy data dependencies and preemptive generation and processing of authorization requests that are replicated from existing authorization requests.
20250039264. CLOUD DEFINED STORAGE_simplified_abstract_(nvidia corporation)
Inventor(s): Siamak Nazari of Mountain View CA (US) for nvidia corporation, Sahba Etaati of Los Gatos CA (US) for nvidia corporation
IPC Code(s): H04L67/1097
CPC Code(s): H04L67/1097
Abstract: storage processing units or spus () operate backend storage () to provide scalable storage services, redundancy, and disaster recovery to an enterprise. each spu () may reside in a host server () and may include an processor domain () with backup power () and isolation from a host domain () to allow the spu () to operate after the host () fails or otherwise stops providing power. a cloud-based management system () may assess the storage needs of the enterprise, identify a storage style suited to the enterprise, and direct the spus () to create virtual volumes () having characteristics according to the storage style identified. the cloud based management system () may eliminate the need for the enterprise to have expertise in storage management.
Inventor(s): Malcolm GUTENBURG of San Francisco CA (US) for nvidia corporation, Darryl MOORE of Campbell CA (US) for nvidia corporation
IPC Code(s): H05K7/20, G06F1/20
CPC Code(s): H05K7/20336
Abstract: disclosed is a system that includes an electronic component, a fan arranged to force air in a first direction, a stacked fin assembly, and a three-dimensional vapor chamber. the three-dimensional vapor chamber includes a base that is thermally coupled to the electronic component and a plurality of vapor columns that extend outward from the base towards the stacked fin assembly. a first dimension of a first vapor column that is included in the plurality of vapor columns along the first direction is greater than a second dimension of the first vapor column along a second direction that is perpendicular to the first direction.
NVIDIA Corporation patent applications on January 30th, 2025
- NVIDIA Corporation
- A63F13/87
- A63F13/355
- A63F13/71
- A63F13/77
- A63F13/79
- CPC A63F13/87
- Nvidia corporation
- B60W60/00
- B60W40/02
- CPC B60W60/001
- G06F9/38
- G06F8/41
- G06T1/20
- CPC G06F9/3869
- G06F11/07
- CPC G06F11/079
- G06N3/084
- G06N3/04
- CPC G06N3/084
- G06N5/04
- CPC G06N5/04
- G06Q30/0601
- G06F16/901
- G06F17/16
- CPC G06Q30/0631
- G06F9/50
- G06T15/10
- CPC G06T1/20
- G06T7/73
- G06T7/60
- CPC G06T7/73
- G06T11/60
- G06N3/045
- G06N5/046
- G06T7/70
- G06V10/774
- G06V10/82
- CPC G06T11/60
- G06T17/20
- G06F16/22
- CPC G06T17/20
- G06T15/20
- CPC G06T17/205
- H04L9/40
- CPC H04L63/102
- H04L67/1097
- CPC H04L67/1097
- H05K7/20
- G06F1/20
- CPC H05K7/20336
