NVIDIA Corporation patent applications on January 2nd, 2025
Patent Applications by NVIDIA Corporation on January 2nd, 2025
NVIDIA Corporation: 13 patent applications
NVIDIA Corporation has applied for patents in the areas of F28D15/04 (1), G06V10/26 (1), G06F30/13 (1), G06F30/27 (1), G06N20/00 (1) F28D15/046 (1), G01R23/005 (1), G02B27/0172 (1), G06F1/28 (1), G06F7/22 (1)
With keywords such as: data, signal, circuit, clock, structure, learning, machine, voltage, generate, and frequency in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Ron CHAO of San Diego CA (US) for nvidia corporation, Elad Mentovich of Tel Aviv (IL) for nvidia corporation, Harrison Sangwha Kim of Morgan Hill CA (US) for nvidia corporation, Mark North of Lancaster PA (US) for nvidia corporation, Xinwei Lu of Shenzhen (CN) for nvidia corporation, Tahir Cader of Spokane Valley WA (US) for nvidia corporation, Fei Zhang of Shenzhen (CN) for nvidia corporation, Yunseok Kim of Pleasanton CA (US) for nvidia corporation, David Haley of Beaverton OR (US) for nvidia corporation, Yuezhan Steven Zhu of San Jose CA (US) for nvidia corporation, Lei Huang of Shenzhen (CN) for nvidia corporation
IPC Code(s): F28D15/04, F28D15/02
CPC Code(s): F28D15/046
Abstract: a heat transfer apparatus including a housing and a wick structure is provided that is configured to dissipate heat from a heat source. the housing defines a chamber that holds working fluid. the wick structure includes a body and pores defined by the body. the heat transfer apparatus defines an evaporator section configured to evaporate the working fluid using heat from a heat source and a condenser section configured to dissipate heat carried by the evaporated working fluid through condensation of the evaporated working fluid. the wick structure has a repeatable, configurable, and controlled geometry optimized to move the working fluid from the condenser section to the evaporator section via capillary action. the body of the wick structure may have a gyroidal geometry. associated methods are also provided.
Inventor(s): Ofek Abadi of Nahariya (IL) for nvidia corporation
IPC Code(s): G01R23/00, G01R15/04, G01R19/165, H03K3/037, H03K5/00, H03K5/24, H03K19/20
CPC Code(s): G01R23/005
Abstract: technologies directed to determine whether a frequency of a clock signal is outside a specified frequency range are described. one integrated circuit includes a signal generator circuit, a voltage divider circuit, and digital logic circuitry. the signal generator circuit generates phase signals from a clock signal. the voltage divider circuit converts a frequency of the clock signal to a voltage representing the frequency. the voltage divider circuit includes a first resistor and a first switched-capacitor structure to receive the phase signals. an average resistance of the first switched-capacitor structure is inversely proportional to the frequency of the clock signal. the digital logic circuitry can determine, using the voltage, whether the frequency is outside of a specified frequency range, and output an indication responsive to the frequency being outside the specified frequency range.
Inventor(s): Jonghyun Kim of San Francisco CA (US) for nvidia corporation, Ward Lopes of San Jose CA (US) for nvidia corporation, David Luebke of Charlottesville VA (US) for nvidia corporation
IPC Code(s): G02B27/01, G02B27/28, G03H1/22, G06T19/00
CPC Code(s): G02B27/0172
Abstract: optical systems including an interferometer utilizing a spatial light modulator. a light guide including a first beam splitter and multiple mirrors directs incoherent light through the beam splitter to the interferometer to generate an interference light pattern, and further directs the interference light pattern back to the first beam splitter via the mirrors.
Inventor(s): Jiale Liang of San Jose CA (US) for nvidia corporation, Prashant Singh of Apison TN (US) for nvidia corporation, Nishit Harshad Shah of Sunnyvale CA (US) for nvidia corporation, Daniel Nguyen of San Jose CA (US) for nvidia corporation, Kaushik Krishna Raghuraman of Campbell CA (US) for nvidia corporation, Suhas Satheesh of Sunnyvale CA (US) for nvidia corporation, Ting Lu of Austin TX (US) for nvidia corporation, Roman Surgutchik of Gilbert AZ (US) for nvidia corporation, Tezaswi Raja of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F1/28, G05F1/46, G06F1/24
CPC Code(s): G06F1/28
Abstract: a circuit includes a bandgap circuit configured to generate multiple reference voltages. a first voltage glitching detection circuit utilizes a first one of the reference voltages and a first power rail to generate a first reset signal in response to a voltage glitching attack on the first power rail, and a second voltage glitching detection circuit operates independently of the reference voltages to generate a second reset signal in response to the voltage glitching attack on the first power rail.
Inventor(s): Ariel Szapiro of Kfar Neter (IL) for nvidia corporation, Arye Albahari of Kiryat Motzkin (IL) for nvidia corporation
IPC Code(s): G06F7/22
CPC Code(s): G06F7/22
Abstract: apparatuses, systems, and techniques for efficient computation of rolling window statistics. a first value of a plurality of values bounded by a range of values is received. the first counter corresponds to a first counter of a plurality of counters, and each counter of the plurality of counters corresponds to a respective value within the range of values. in response to reception of the first value, the first counter is reset, and each of the other counters of the plurality of counters is updated. a minimum value or a maximum value within a window of most recently received value of the plurality of values is determined using the plurality of counters.
Inventor(s): Shridhar Rasal of Pune (IN) for nvidia corporation
IPC Code(s): G06F9/38
CPC Code(s): G06F9/5094
Abstract: disclosed are apparatuses, systems, and techniques that use machine learning techniques for determination and tuning of runtime settings of processing units. in one embodiment, a computing device, which includes one or more processing units, processes, using a machine learning model, a runtime activity data to generate settings for the processing unit(s). the runtime activity data characterizes an execution of a computing application on the processing unit(s). the computing device then modifies, using the generated settings, the execution of the computing application on the processing unit(s).
Inventor(s): Gregory A. MUTHLER of Chapel Hill NC (US) for nvidia corporation, Timo AILA of Helsinki (FI) for nvidia corporation, Tero KARRAS of Helsinki (FI) for nvidia corporation, Samuli LAINE of Uusimaa (FI) for nvidia corporation, William Parsons NEWHALL, JR. of Woodside CA (US) for nvidia corporation, Ronald Charles BABICH, JR. of Murrysville PA (US) for nvidia corporation, John BURGESS of Austin TX (US) for nvidia corporation, Ignacio LLAMAS of Palo Alto CA (US) for nvidia corporation
IPC Code(s): G06F12/0875, G06F16/901, G06T15/06
CPC Code(s): G06F12/0875
Abstract: in a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. grouping the requests provides good performance with a smaller number of cache lines.
Inventor(s): Taek RYOO of Pleasanton CA (US) for nvidia corporation, Stephen WOLFE of San Jose CA (US) for nvidia corporation, Akshay SHARAN of Seattle WA (US) for nvidia corporation, Mihir JOSHI of Santa Clara CA (US) for nvidia corporation, Mustafa BILGEN of Brookline MA (US) for nvidia corporation, Mahesh LAGADAPATI of HYDERABAD (IN) for nvidia corporation, Tao YE of San Jose CA (US) for nvidia corporation, Santosh KATVATE of Pune (IN) for nvidia corporation, Arun GONA of Bothell WA (US) for nvidia corporation
IPC Code(s): G06F21/60, G06F21/78
CPC Code(s): G06F21/602
Abstract: embodiments of the present disclosure relate to a method of encrypting a secret storage structure. the method may include storing a secret in a secret storage structure. the secret storage structure may be encrypted by encrypting the secret using a wrap key that is generated based at least on a hardware-based root key and a first context. the secret storage structure may additionally be encrypted by encrypting the secret storage structure using an authentication key that is generated based at least on the hardware-based root key and a second context.
Inventor(s): Siddha Ganju of Santa Clara CA (US) for nvidia corporation, Aastha Jhunjhunwala of Santa Clara CA (US) for nvidia corporation, Elad Mentovich of Tel Aviv (IL) for nvidia corporation, Ryan Albright of Beaverton OR (US) for nvidia corporation, Srikanth Cherukuri of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06F30/13, G06F30/27
CPC Code(s): G06F30/13
Abstract: systems, computer program products, and methods are described herein for intelligent intelligently designing and reconfiguring data centers. for example, a system may be an artificial-intelligence-based system for designing and reconfiguring data centers based on user inquiries. the system may receive inquiries from users requesting a design for a data center having particular performance characteristics (e.g., selected performance characteristics), changes to an existing design of a data center, information about a data center, and/or the like. the inquiries may be text-based or audio and in the form of natural language questions or commands. the system may use two machine learning models, namely a knowledge base model and a ranking model. the system may use the knowledge base model to determine solutions to user inquiries and then use the ranking model to determine rankings for the solutions.
Inventor(s): Sushant VEER of Sunnyvale CA (US) for nvidia corporation, Apoorva SHARMA of Oakland CA (US) for nvidia corporation, Marco PAVONE of Stanford CA (US) for nvidia corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: one embodiment of a method for processing data includes performing one or more operations to determine a performance of one or more predefined rules based on data that is received and one or more first predictions generated using the one or more predefined rules, performing one or more operations to determine a performance of a trained machine learning model based on the data and one or more second predictions generated using the trained machine learning model, processing the data using the one or more predefined rules to generate one or more third predictions, processing the data using the trained machine learning model to generate one or more fourth predictions, and generating one or more fifth predictions based on the one or more third predictions, the one or more fourth predictions, the performance of the one or more predefined rules, and the performance of the trained machine learning model.
Inventor(s): Parthasarathy Sriram of Los Altos CA (US) for nvidia corporation, Fnu Ratnesh Kumar of Campbell CA (US) for nvidia corporation, Anil Ubale of Cupertino CA (US) for nvidia corporation, Farzin Aghdasi of East Palo Alto CA (US) for nvidia corporation, Yan Zhai of Santa Clara CA (US) for nvidia corporation, Subhashree Radhakrishnan of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06V40/10, G06N3/045, G06N3/08, G06T7/246, G06V10/26, G06V10/44, G06V10/82, G06V20/52
CPC Code(s): G06V40/103
Abstract: in various examples, sensor data—such as masked sensor data—may be used as input to a machine learning model to determine a confidence for object to person associations. the masked sensor data may focus the machine learning model on particular regions of the image that correspond to persons, objects, or some combination thereof. in some embodiments, coordinates corresponding to persons, objects, or combinations thereof, in addition to area ratios between various regions of the image corresponding to the persons, objects, or combinations thereof, may be used to further aid the machine learning model in focusing on important regions of the image for determining the object to person associations.
Inventor(s): Ofek Abadi of Nahariya (IL) for nvidia corporation, Omer Wolkovitz of Kfar Saba (IL) for nvidia corporation
IPC Code(s): H03L7/08, H03L7/081, H03L7/099
CPC Code(s): H03L7/0807
Abstract: a receiver includes a multi-phase clock generator to generate phases of a clock signal and a global phase interpolator (pi) circuit coupled to the multi-phase clock generator and to clock and data recovery (cdr) circuitry. the global pi circuit generates initial-adjusted phases from the phases of the clock signal based on a control signal received from the cdr circuitry. a first local pi receives the initial-adjusted phases of the clock signal and applies a first fixed phase shift to the initial-adjusted phases to generate first final-adjusted phases of the clock signal that are useable to sample a first level of multiple levels of a pulse-amplitude-modulated (pam) data stream.
20250008148. SUPERPIXEL GENERATION AND USE_simplified_abstract_(nvidia corporation)
Inventor(s): Vipul Parashar of Pune (IN) for nvidia corporation, Vignesh Ungrapalli of Bengaluru (IN) for nvidia corporation
IPC Code(s): H04N19/513, G06T7/12, H04N19/139, H04N19/176
CPC Code(s): H04N19/521
Abstract: apparatuses, systems, and techniques to interpolate one or more intermediate images from two or more images is disclosed. in at least one embodiment, a processor includes one or more circuits to interpolate one or more intermediate images from two or more images based, at least in part, on one or more inconsistent flow vectors corresponding to the two or more images.
- NVIDIA Corporation
- F28D15/04
- F28D15/02
- CPC F28D15/046
- Nvidia corporation
- G01R23/00
- G01R15/04
- G01R19/165
- H03K3/037
- H03K5/00
- H03K5/24
- H03K19/20
- CPC G01R23/005
- G02B27/01
- G02B27/28
- G03H1/22
- G06T19/00
- CPC G02B27/0172
- G06F1/28
- G05F1/46
- G06F1/24
- CPC G06F1/28
- G06F7/22
- CPC G06F7/22
- G06F9/38
- CPC G06F9/5094
- G06F12/0875
- G06F16/901
- G06T15/06
- CPC G06F12/0875
- G06F21/60
- G06F21/78
- CPC G06F21/602
- G06F30/13
- G06F30/27
- CPC G06F30/13
- G06N20/00
- CPC G06N20/00
- G06V40/10
- G06N3/045
- G06N3/08
- G06T7/246
- G06V10/26
- G06V10/44
- G06V10/82
- G06V20/52
- CPC G06V40/103
- H03L7/08
- H03L7/081
- H03L7/099
- CPC H03L7/0807
- H04N19/513
- G06T7/12
- H04N19/139
- H04N19/176
- CPC H04N19/521
