NVIDIA Corporation patent applications on January 23rd, 2025
Patent Applications by NVIDIA Corporation on January 23rd, 2025
NVIDIA Corporation: 18 patent applications
NVIDIA Corporation has applied for patents in the areas of G06V10/82 (2), G10L25/78 (2), G06T3/40 (2), G06T5/00 (2), G06T17/20 (2) G01C21/3881 (1), G06T15/06 (1), G10L17/20 (1), G08G1/096725 (1), G06V20/70 (1)
With keywords such as: data, pixel, features, adcs, processing, based, value, datacenter, audio, and segmentation in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Galen Collins of Seattle WA (US) for nvidia corporation, Vladimir Shestak of Boulder CO (US) for nvidia corporation
IPC Code(s): G01C21/00, G06F16/22, G06F16/29
CPC Code(s): G01C21/3881
Abstract: in various examples, a method to manage map data includes storing a map of a geographic area using an immutable tree. the immutable tree comprises a plurality of nodes stored using a distributed hash table. the plurality of nodes include a plurality of map tiles. at least two map tiles of the plurality of map tiles cover different geographic subregions of the geographic area of the map. the method includes hosting one or more binary large objects (blobs) that correspond to the plurality of map tiles in an origin data plane. the method includes making the one or more blobs available for distribution to one or more client devices using a content delivery network (cdn).
Inventor(s): Ziyi Xu of Shenzhen (CN) for nvidia corporation, Zheng Wu of San Jose CA (US) for nvidia corporation, Ben Pei En Tsai of Uusimaa (FI) for nvidia corporation, Xuan Wang of Xuzhou (CN) for nvidia corporation
IPC Code(s): G06F1/324, H03L7/099
CPC Code(s): G06F1/324
Abstract: technologies directed to input current limiter (icl) circuits with frequency control loops are described. one integrated circuit includes a processing core and an icl circuit. the icl circuit can limit an input current to the processing core within a current limit of the processing core. the icl circuit can determine an input current and a supply voltage provided to the processing core at a first time. the icl circuit can reduce a clock of the processing core from a first clock frequency to a second clock frequency with a linear frequency drop based on the current limit, the input current, and the supply voltage. value, the second value, and the third value. the first clock frequency corresponds to a first voltage, and the second frequency corresponds to a second voltage. the icl circuit can reduce the clock to a third clock frequency corresponding to a third voltage.
Inventor(s): Shantanu SARANGI of Saratgoa CA (US) for nvidia corporation, Milind SONAWANE of Santa Clara CA (US) for nvidia corporation, Alex HSU of New Taipei (TW) for nvidia corporation, Sailendra CHADALAVADA of Saratoga CA (US) for nvidia corporation, Nitin YOGI of Milpitas CA (US) for nvidia corporation, Nithin VALENTINE of San Jose CA (US) for nvidia corporation
IPC Code(s): G01R31/3183, G01R31/317
CPC Code(s): G06F11/3457
Abstract: systems and methods are disclosed that relate to applications and platforms for performing in-system testing for autonomous or semi-autonomous systems and applications. in some embodiments, resources of a computing system may be grouped into one or more subsets of system elements (e.g., “a chiplet”) and may be configured to be controlled via an associated local controller, which may enable and/or disable the chiplet as targeted. in embodiments, the local controllers may receive instructions from a central controller and, via the enabling and/or disabling of the chiplets, may maintain a number of resources consumed during system testing within a threshold. as a result, the system may be configured to perform system testing without additional resources and/or without redirecting resources that may be intended for other operations.
Inventor(s): Sean HUVER of Ridgefield CT (US) for nvidia corporation
IPC Code(s): G06F21/62
CPC Code(s): G06F21/6254
Abstract: embodiments of the present disclosure relate to a method of performing one or more operations using a machine learning model. in some embodiments, the machine learning model may be trained, at least in part, using synthetic training data that may have been generated using one or more generative machine learning models. further, the one or more generative machine learning models may be trained to generate the synthetic training data based at least on real training data designated for protection.
Inventor(s): Swapnil Jagdish Rathi of Maharashtra (IN) for nvidia corporation, Bhushan Rupde of Maharashtra (IN) for nvidia corporation, Kaustubh Purandare of San Jose CA (US) for nvidia corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: disclosed are apparatuses, systems, and techniques for implementing automatic runtime selection and tuning of mlm processing pipelines using stream augmentation. in one embodiment, the techniques include augmenting data stream(s) with auxiliary data to obtain an augmented data stream. the techniques further include performing an inference processing of the augmented data stream using a machine learning model (mlm) to obtain a characterization of a presence of the auxiliary data in the augmented data stream and adjusting one or more runtime settings of the mlm using the obtained characterization.
Inventor(s): Timofey Cheblokov of San Jose CA (US) for nvidia corporation
IPC Code(s): G06T3/40, G06T5/00, G06T7/90
CPC Code(s): G06T3/40
Abstract: in various examples, systems and methods are disclosed relating to historical acceleration. one method includes determining a plurality of history buffers for a frame, the plurality of history buffers comprising a responsive history buffer and a normal history buffer, the responsive history buffer comprising a first pixel value at a pixel location of the frame, and the normal history buffer comprising a second pixel value at the pixel location of the frame, and the normal history buffer including a second pixel value at the pixel location of the frame. the method further includes determining at least one difference between the first pixel value of the responsive history buffer and the second pixel value of the normal history buffer and updating at least one of the first pixel value or the second pixel value based on the at least one difference and a tuning parameter.
Inventor(s): Michael RANZINGER of Park City UT (US) for nvidia corporation
IPC Code(s): G06T3/4046, G06V10/26, G06V10/82
CPC Code(s): G06T3/4046
Abstract: apparatuses, systems, and methods to use one or more neural networks to generate information about one or more images based, at least in part, on one or more confidence scores associated with the information. in at least one embodiment, a neural network downscales an image and performs an image processing task on said downscaled image according to a query input by a user.
Inventor(s): David Nister of Bellevue WA (US) for nvidia corporation, Soohwan Kim of Asan-si (KR) for nvidia corporation, Yue Wu of Mountain View CA (US) for nvidia corporation, Minwoo Park of Saratoga CA (US) for nvidia corporation, Cheng-Chieh Yang of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G06T7/215, G06T7/60, G06V10/422
CPC Code(s): G06T7/215
Abstract: in various examples, an ego-machine may analyze sensor data to identify and track features in the sensor data using. geometry of the tracked features may be used to analyze motion flow to determine whether the motion flow violates one or more geometrical constraints. as such, tracked features may be identified as dynamic features when the motion flow corresponding to the tracked features violates the one or more static constraints for static features. tracked features that are determined to be dynamic features may be clustered together according to their location and feature track. once features have been clustered together, the system may calculate a detection bounding shape for the clustered features. the bounding shape information may then be used by the ego-machine for path planning, control decisions, obstacle avoidance, and/or other operations.
Inventor(s): Siddha Ganju of Santa Clara CA (US) for nvidia corporation, Srikanth Cherukuri of Belmont CA (US) for nvidia corporation, Elad Mentovich of Tel Aviv (IL) for nvidia corporation, Yoram Zer of Megido (IL) for nvidia corporation, Ashrut Ambastha of Pune (IN) for nvidia corporation, Jeremy Rodriguez of Santa Cruz CA (US) for nvidia corporation, Lior Ofer of Tel Mond (IL) for nvidia corporation
IPC Code(s): G06T11/00, H04L43/045
CPC Code(s): G06T11/00
Abstract: systems, methods, and computer program products are provided for datacenter visualization. an example method includes receiving a request for datacenter visualization that is associated with a plurality of datacenter computing components of a physical datacenter installation. the method includes determining one or more installation characteristics associated with the physical datacenter installation and determining one or more performance parameters associated with the physical datacenter installation based at least in part on the one or more installation characteristics. the method further includes generating the datacenter visualization for presentation to a user associated with the request. the datacenter visualization is a digital representation of the physical datacenter installation that further includes a visual representation of the performance parameters associated with the plurality of datacenter computing components.
Inventor(s): Zhengyu HUANG of Shanghai (CN) for nvidia corporation, Dmitry KOROBCHENKO of London (GB) for nvidia corporation, Junjie LAI of Beijing (CN) for nvidia corporation, Tao LI of Beijing (CN) for nvidia corporation, Yeongho SEOL of Seoul (KR) for nvidia corporation, Rui ZHANG of Beijing (CN) for nvidia corporation, Weihua ZHANG of Beijing (CN) for nvidia corporation, Yingying ZHONG of Shanghai (CN) for nvidia corporation
IPC Code(s): G06T13/40, G06T13/20, G10L15/02, G10L15/04, G10L15/16
CPC Code(s): G06T13/40
Abstract: in various examples, a technique for audio-driven facial animation with adaptive speech includes determining that a rate of speech associated with an audio segment exceeds a threshold. the technique also includes based at least on the rate of speech exceeding the threshold, upsampling a first set of features associated with the audio segment into a second set of features that is different in size than the first set of features. the technique further includes generating, using one or more machine learning models and based at least on at least a subset of the second set of features, a facial animation output corresponding to the audio segment.
Inventor(s): Timofey Cheblokov of San Jose CA (US) for nvidia corporation
IPC Code(s): G06T15/06, G06T5/00
CPC Code(s): G06T15/06
Abstract: in various examples, systems and methods are disclosed relating to historical reset. one method includes determining at least one history buffer for a frame, determining, in a spatial domain, a spatial component of the accumulated pixel value at the pixel location based on a first spatial moment and a second spatial moment, determining, in a temporal domain, a temporal component of the accumulated pixel value at the pixel location based on a first temporal moment and a second temporal moment. the method further includes determining a pixel value range based at least on the spatial component and the temporal component, determining an amount of historical reset to apply, and updating the accumulated pixel value based at least on the amount of historical reset.
Inventor(s): Xingguang Yan of Burnaby (CA) for nvidia corporation, Or Perel of Tel Aviv (IL) for nvidia corporation, James Robert Lucas of Royston (GB) for nvidia corporation, Towaki Takikawa of Toronto (CA) for nvidia corporation, Karsten Julian Kreis of Vancouver (CA) for nvidia corporation, Maria Shugrina of Toronto (CA) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation, Or Litany of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G06T17/20, G06T3/40
CPC Code(s): G06T17/20
Abstract: approaches presented herein provide systems and methods for generating three-dimensional (3d) objects using compressed data as an input. one or more models may learn from a hash table of latent features to map different features to a reconstruction domain, using a hash function as part of a learned process. a 3d shape for an object may be encoded to a multi-layered grid and represented by a series of embeddings, where given point within the grid may be interpolated based on the embeddings for a given layer of the multi-layered grid. a decoder may then be trained to use the embeddings to generate an output object.
Inventor(s): Kangxue Yin of Toronto (CA) for nvidia corporation, Jun Gao of Toronto (CA) for nvidia corporation, Masha Shugrina of Toronto (CA) for nvidia corporation, Sameh Khamis of Alameda CA (US) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation
IPC Code(s): G06T19/20, G06N3/045, G06T3/02, G06T3/18, G06T7/11, G06T15/04, G06T17/20
CPC Code(s): G06T19/20
Abstract: generation of three-dimensional (d) object models may be challenging for users without a sufficient skill set for content creation and may also be resource intensive. one or more style transfer networks may be used for part-aware style transformation of both geometric features and textural components of a source asset to a target asset. the source asset may be segmented into particular parts and then ellipsoid approximations may be warped according to correspondence of the particular parts to the target assets. moreover, a texture associated with the target asset may be used to warp or adjust a source texture, where the new texture can be applied to the warped parts.
Inventor(s): Igor Tryndin of Fremont CA (US) for nvidia corporation, Abhishek Bajpayee of Santa Clara CA (US) for nvidia corporation, Yu Wang of Mountain View CA (US) for nvidia corporation, Hae-Jong Seo of Campbell CA (US) for nvidia corporation
IPC Code(s): G06V10/60, B60Q1/14, G06V10/25, G06V20/58, H05B47/125
CPC Code(s): G06V10/60
Abstract: in various examples, contrast values corresponding to pixels of one or more images generated using one or more sensors of a vehicle may be computed to detect and identify objects that trigger glare mitigating operations. pixel luminance values are determined and used to compute a contrast value based on comparing the pixel luminance values to a reference luminance value that is based on a set of the pixels and the corresponding luminance values. a contrast threshold may be applied to the computed contrast values to identify glare in the image data to trigger glare mitigating operations so that the vehicle may modify the configuration of one or more illumination sources so as to reduce glare experienced by occupants and/or sensors of the vehicle.
Inventor(s): Subhashree Radhakrishnan of Milpitas CA (US) for nvidia corporation, Ramanathan Arunachahalam of Saratoga CA (US) for nvidia corporation, Farzin Aghdasi of East Palo Alto CA (US) for nvidia corporation, Zhiding Yu of Cupertino CA (US) for nvidia corporation, Shiyi Lan of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G06V20/70, G06V10/82
CPC Code(s): G06V20/70
Abstract: approaches are disclosed herein for an automatic segmentation labeling system that identifies objects for potential open-class categories and generates segmentation masks for objects. the disclosed system may use a training pipeline that trains two segmentation models. the training pipeline may take, as input, a set of images with bounding boxes and class labels. the set of images may be fed into a first segmentation network with the bounding boxes used as ground truth for weak supervision. the first segmentation network may be trained to generate pseudo segmentation masks. in a second stage, the trained first segmentation network is used to generate pseudo masks for a set of input images. the generated pseudo masks are provided as input, along with the corresponding images, to a second segmentation network to be used as a type of ground truth data for training the second segmentation network to generate high-quality segmentation masks.
20250029489. REINFORCEMENT LEARNING FOR TRAFFIC SIMULATION_simplified_abstract_(nvidia corporation)
Inventor(s): Yulong Cao of Union City NJ (US) for nvidia corporation, Chaowei Xiao of Tempe AZ (US) for nvidia corporation, Marco Pavone of Stanford CA (US) for nvidia corporation, Boris Ivanovic of Mountain View CA (US) for nvidia corporation
IPC Code(s): G08G1/0967, G06N3/02, G08G1/01
CPC Code(s): G08G1/096725
Abstract: in various examples, a traffic model including one or more traffic scenarios may be generated and/or updated based on using human feedback. human feedback may be provided indicating a preference for various traffic scenarios to identify which scenarios in a model are more realistic. a reward model may capture the preference information and rank the realism of one or more traffic scenarios.
Inventor(s): Taejin Park of San Jose CA (US) for nvidia corporation, Ante Jukic of Culver City CA (US) for nvidia corporation, He Huang of Greenville SC (US) for nvidia corporation, Venkata Naga Krishna Chaitanya Puvvada of San Jose CA (US) for nvidia corporation, Kunal Dhawan of San Jose CA (US) for nvidia corporation, Nithin Rao Koluguri of Milpitas CA (US) for nvidia corporation, Nikolay Karpov of Moscow (RU) for nvidia corporation, Aleksandr Laptev of Erevan (AM) for nvidia corporation, Jagadeesh Balam of Campbell CA (US) for nvidia corporation
IPC Code(s): G10L17/20, G10L17/02, G10L17/18, G10L25/78
CPC Code(s): G10L17/20
Abstract: disclosed are apparatuses, systems, and techniques that may use machine learning for implementing speaker recognition, verification, and/or diarization. the techniques include receiving a first set of audio data channels (adcs) jointly capturing a speech produced by one or more speakers and obtaining, using the first set of adcs, a second set of one or more adcs. individual adcs of the second set of adcs represent one or more channels of the first set of adcs, and at least one channel of the second set of adcs represents a cluster of two or more adcs of the first set of adcs, the two of more adcs being selected based on similarity of audio data of the two or more adcs. the techniques further include processing, using an audio processing neural network model, the second set of adcs to obtain an association of the speech to the one or more speakers.
Inventor(s): Taejin Park of San Jose CA (US) for nvidia corporation, Ante Jukic of Culver City CA (US) for nvidia corporation, He Huang of Greenville SC (US) for nvidia corporation, Venkata Naga Krishna Chaitanya Puvvada of San Jose CA (US) for nvidia corporation, Kunal Dhawan of San Jose CA (US) for nvidia corporation, Nithin Rao Koluguri of Milpitas CA (US) for nvidia corporation, Nikolay Karpov of Moscow (per message on New App. Men (AM) for nvidia corporation, Aleksandr Laptev of Erevan (AM) for nvidia corporation, Jagadeesh Balam of Campbell CA (US) for nvidia corporation
IPC Code(s): G10L25/78, G10L25/30
CPC Code(s): G10L25/78
Abstract: disclosed are apparatuses, systems, and techniques that may use machine learning for implementing speaker recognition, verification, and/or diarization. the techniques include processing audio data channels (adcs) using a voice detection model to determine voice activity likelihoods (vals) that individual adcs include speech, obtaining, using vals, a second set of adc(s), and processing, using an audio processing a neural network (nn) model, the second set of adcs to obtain association of the speech to the one or more speakers. the techniques also include generating a plurality of embeddings associated with the adcs, processing the plurality of embeddings to obtain aggregated embedding(s) that represent audio data of multiple adcs, and processing the aggregated embedding(s), using the audio processing nn model, to obtain association of the speech to the one or more speakers.
NVIDIA Corporation patent applications on January 23rd, 2025
- NVIDIA Corporation
- G01C21/00
- G06F16/22
- G06F16/29
- CPC G01C21/3881
- Nvidia corporation
- G06F1/324
- H03L7/099
- CPC G06F1/324
- G01R31/3183
- G01R31/317
- CPC G06F11/3457
- G06F21/62
- CPC G06F21/6254
- G06N20/00
- CPC G06N20/00
- G06T3/40
- G06T5/00
- G06T7/90
- CPC G06T3/40
- G06T3/4046
- G06V10/26
- G06V10/82
- CPC G06T3/4046
- G06T7/215
- G06T7/60
- G06V10/422
- CPC G06T7/215
- G06T11/00
- H04L43/045
- CPC G06T11/00
- G06T13/40
- G06T13/20
- G10L15/02
- G10L15/04
- G10L15/16
- CPC G06T13/40
- G06T15/06
- CPC G06T15/06
- G06T17/20
- CPC G06T17/20
- G06T19/20
- G06N3/045
- G06T3/02
- G06T3/18
- G06T7/11
- G06T15/04
- CPC G06T19/20
- G06V10/60
- B60Q1/14
- G06V10/25
- G06V20/58
- H05B47/125
- CPC G06V10/60
- G06V20/70
- CPC G06V20/70
- G08G1/0967
- G06N3/02
- G08G1/01
- CPC G08G1/096725
- G10L17/20
- G10L17/02
- G10L17/18
- G10L25/78
- CPC G10L17/20
- G10L25/30
- CPC G10L25/78
