NVIDIA Corporation patent applications on February 20th, 2025
Patent Applications by NVIDIA Corporation on February 20th, 2025
NVIDIA Corporation: 21 patent applications
NVIDIA Corporation has applied for patents in the areas of G06V10/82 (3), B60W60/00 (2), G06N3/08 (2), G06N3/045 (2), B60Q1/14 (1) B60Q1/143 (1), G06T7/593 (1), H04L67/51 (1), H04L67/12 (1), H04B17/373 (1)
With keywords such as: based, data, systems, network, neural, techniques, images, methods, generative, and various in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Keerthi Raj NAGARAJA of Santa Clara CA (US) for nvidia corporation, Arjun GUPTA of Stanford CA (US) for nvidia corporation, Abhishek BAJPAYEE of Santa Clara CA (US) for nvidia corporation, Kivanc TEMEL of Cambridge MA (US) for nvidia corporation, Dylan DOBLAR of San Jose CA (US) for nvidia corporation, Sai Krishnan CHANDRASEKAR of Santa Clara CA (US) for nvidia corporation, Yu WANG of Mountain View CA (US) for nvidia corporation
IPC Code(s): B60Q1/14, G06V10/60, G06V10/82, G06V20/56
CPC Code(s): B60Q1/143
Abstract: the present disclosure relates to determining a first illumination level corresponding to an area based at least on a first illumination detection obtained using a first illumination detector corresponding to a machine. a second illumination level corresponding to the area may be determined based at least on a second illumination detection obtained using a second illumination detector corresponding to the machine. based at least on the first illumination level and the second illumination level, a scene illumination state of the area may be determined. based at least on the scene illumination state, one or more lights of the machine may be controlled.
20250058739. RESTRAINT DEVICE LOCALIZATION_simplified_abstract_(nvidia corporation)
Inventor(s): Feng Hu of Santa Clara CA (US) for nvidia corporation
IPC Code(s): B60R22/48, G06T7/60, G06T7/73
CPC Code(s): B60R22/48
Abstract: systems and methods are disclosed related to restraint device (e.g., seatbelt) localization. in one embodiment, the disclosure relates to systems and methods for seatbelt detection and modeling. a vehicle may be occupied by one or more occupants wearing one or more seatbelts. a camera or other sensor is placed within the vehicle to capture images of the one or more occupants. a system analyzes the images to detect and model seatbelts depicted in the images. specifically, the system may scan the images and areas of the images that may correspond to seatbelts. the system may assemble candidate areas of the images that may correspond to seatbelts, and refine the candidate areas based on various constraints. the system may build models based on the refined candidate areas that indicate the seatbelts. the system may visualize the models indicating the seatbelts using the images.
Inventor(s): Vishisht Gupta of Santa Clara CA (US) for nvidia corporation, Amir Akbarzadeh of San Jose CA (US) for nvidia corporation, Yu Sheng of San Diego CA (US) for nvidia corporation
IPC Code(s): B60W60/00, G01C21/00
CPC Code(s): B60W60/001
Abstract: in various examples, accuracy determinations for localization in autonomous and semi-autonomous systems and applications are described herein. systems and methods are disclosed that determine one or more errors associated with vehicle localization using various types of sensor data generated using a vehicle. for instance, a first component of the vehicle may use a map and first sensor data to determine an estimated pose of the vehicle. a second component of the vehicle may then determine the error(s) associated with the estimated pose based on both actual motion of the vehicle within the environment, as determined using second sensor data, and comparing features represented by the first sensor data to features represented by the map. in some examples, the second component may further determine information associated with the error(s), such as one or more uncertainties associated with the error(s).
Inventor(s): Yuxiao Chen of Newark CA (US) for nvidia corporation, Sushant Veer of Sunnyvale CA (US) for nvidia corporation, Peter Karkus of Zurich (CH) for nvidia corporation, Marco Pavone of Stanford CA (US) for nvidia corporation
IPC Code(s): B60W60/00
CPC Code(s): B60W60/0027
Abstract: in various examples, a gradient-based motion planner evaluates a cost function corresponding to routes for a machine and an obstacle to jointly update the routes. the cost function may include terms to penalize deviation from an initial route predicted for the obstacle and acceleration or jerk for the obstacle. the routes for the machine and the obstacle that are updated may be selected using motion classes that characterize relative motion between a route for the machine and a route for the obstacle. a motion class may be based at least on an angular distance between the machine and the agent and free-end homotopy, where members of the class execute the same relative motion with respect to other agents while being continuously transformable to any other member of the class. the members of the class may have the same start point and different end points.
Inventor(s): Jack CHOQUETTE of Palo Alto CA (US) for nvidia corporation, Po-An TSAI of Somerville MA (US) for nvidia corporation, Alexander L. MINKIN of Los Altos CA (US) for nvidia corporation, Manan PATEL of San Jose CA (US) for nvidia corporation, Neal Clayton CRAGO of Amherst MA (US) for nvidia corporation, Daniel STIFFLER of Santa Clara CA (US) for nvidia corporation, Kefeng DUAN of Shanghai (CN) for nvidia corporation, Yu-Jung CHEN of Hsinchu (TW) for nvidia corporation, Jing LI of Shanghai (CN) for nvidia corporation, Qian WANG of Shanghai (CN) for nvidia corporation, Ronny KRASHINSKY of Portola Valley CA (US) for nvidia corporation, Jun YANG of Beijing (CN) for nvidia corporation, Feng XIE of Shanghai (CN) for nvidia corporation
IPC Code(s): G06F7/544, G06F5/01, G06F7/50, G06F7/523
CPC Code(s): G06F7/5443
Abstract: systems and methods for efficient convolution based on matrix multiply and add (mma) are described. an example processor having a plurality of processing lanes is configured to perform convolution of a matrix of activation elements and a filter matrix in accordance with a configurable series of instructions including a plurality of mma instructions and shift instructions while reusing activation elements already loaded to the datapath or associated memory over a plurality of mma operations. associated methods are also described.
20250061078. EFFICIENT CHIP-TO-CHIP COMMUNICATIONS_simplified_abstract_(nvidia corporation)
Inventor(s): Anurag Chaudhary of San Jose CA (US) for nvidia corporation, Guan Wang of San Jose CA (US) for nvidia corporation, Harsh Kumar of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F13/40, G06F12/0831, G06F15/173
CPC Code(s): G06F13/4031
Abstract: in various examples, when a bridge of a chip has received an eviction request from a client of the chip, the bridge may transmit a read request that corresponds to the same cache line to another chip without waiting for an inter-chip completion response for the eviction request. when the read request is received, the bridge may determine whether the eviction request has already been sent to the other chip and transmit the read request based at least on the eviction request being sent to the other chip using an ordered communication network to ensure the communications are received and/or processed by the other chip in an order that maintains memory coherency. additionally, the chips may process read unique requests without using an inter-chip completion acknowledgement and may process copy back requests by transmitting corresponding copy back write data with the copy back requests.
20250061153. ITERATIVE SPATIAL GRAPH GENERATION_simplified_abstract_(nvidia corporation)
Inventor(s): Hang Chu of Toronto (CA) for nvidia corporation, Daiqing Li of Toronto (CA) for nvidia corporation, David Jesus Acuna Marrero of Toronto (CA) for nvidia corporation, Amlan Kar of Toronto (CA) for nvidia corporation, Maria Shugrina of Toronto (CA) for nvidia corporation, Ming-Yu Liu of San Jose CA (US) for nvidia corporation, Antonio Torralba Barriuso of Somerville MA (US) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation
IPC Code(s): G06F16/901, G06F30/13, G06F30/27, G06N3/044, G06N3/045, G06N3/047, G06N3/08, G06N3/084, G06N5/04, G06N20/10, G06N20/20, G06V10/764, G06V10/82, G06V10/84, G06V20/10
CPC Code(s): G06F16/9024
Abstract: a generative model can be used for generation of spatial layouts and graphs. such a model can progressively grow these layouts and graphs based on local statistics, where nodes can represent spatial control points of the layout, and edges can represent segments or paths between nodes, such as may correspond to road segments. a generative model can utilize an encoder-decoder architecture where the encoder is a recurrent neural network (rnn) that encodes local incoming paths into a node and the decoder is another rnn that generates outgoing nodes and edges connecting an existing node to the newly generated nodes. generation is done iteratively, and can finish once all nodes are visited or another end condition is satisfied. such a model can generate layouts by additionally conditioning on a set of attributes, giving control to a user in generating the layout.
20250061323. ACTIVE LEARNING WITH ANNOTATION SCORES_simplified_abstract_(nvidia corporation)
Inventor(s): Vishwesh Nath of Nolensville TN (US) for nvidia corporation, Daguang Xu of Potomac MD (US) for nvidia corporation, Bin Liu of Shanghai (CN) for nvidia corporation, Yufan He of Broomall PA (US) for nvidia corporation, Sachidanand Alle of San Ramon CA (US) for nvidia corporation, Pengcheng Ma of Shanghai (CN) for nvidia corporation, Raghav Mani of Boston MA (US) for nvidia corporation, Marc Thomas Edgar of Glenmont NY (US) for nvidia corporation, Andrew Feng of Cupertino CA (US) for nvidia corporation
IPC Code(s): G06N3/08
CPC Code(s): G06N3/08
Abstract: apparatuses, systems, and techniques to perform active learning. in at least one embodiment, one or more neural networks are trained using training data selected for manual relabeling based, at least in part, on an amount by which the training data is mis-labeled
20250061340. TRAINING NEURAL NETWORKS INDEPENDENTLY_simplified_abstract_(nvidia corporation)
Inventor(s): Sharath Turuvekere Sreenivas of San Jose CA (US) for nvidia corporation, Daniel Korzekwa of Gdansk (PL) for nvidia corporation
IPC Code(s): G06N3/096, G06N3/045
CPC Code(s): G06N3/096
Abstract: apparatuses, systems, and techniques to train neural networks. in at least one embodiment, a first neural network is trained to match accuracy of a second neural network independently of outputs of the second neural network based on, for example, a third neural network that generates weights for the first neural network.
Inventor(s): Fereshte MOZAFARI GHORABA of Zurich (CH) for nvidia corporation, Yang Gao of Santa Clara CA (US) for nvidia corporation, Yao-Lung Fang of Livingston NJ (US) for nvidia corporation
IPC Code(s): G06N10/20
CPC Code(s): G06N10/20
Abstract: in various examples, systems and methods for decomposition of quantum oracles for simulating quantum circuits are provided. a simulation platform may receive as input a representation of a quantum circuit that comprises decomposable boolean functions that define a quantum oracle and convert a boolean representation of the quantum oracle to a set of boolean functions. the boolean functions may be used to create an oracle tensor network (e.g., a mpo sub-tensor network) comprising an exact representation of the boolean representation of the quantum oracle. the oracle tensor network representation may be incorporated into a tensor network representation of the quantum circuit and passed to the simulation platform in order to simulate the quantum circuit.
Inventor(s): Henry M. Clever of Brooklyn NY (US) for nvidia corporation, Jean-Francois Victor Lafleche of Toronto (CA) for nvidia corporation
IPC Code(s): G06T7/194, G06T5/50, G06V10/774
CPC Code(s): G06T7/194
Abstract: approaches presented herein are directed to generating synthetic images with one or more augmentations realistically added to objects in the images, while ensuring the preservation and integrity of semantic or contextual information within the image. a synthetic augmentation system may identify and extract foreground image data (e.g., text), and a version of the image with the foreground image data removed can be processed by a generative diffusion model. one or more inputs can be provided to specify aspects such as a type or strength of augmentation to be performed. after an augmented image is generated using the generative diffusion model, the previously removed text can be blended back into the image. a synthetic augmentation system may use one or more blending weights for the text, such as a defect blending weight and a letter blending weight. the final result is a synthetic image with added realistic augmentations that preserves the semantic content.
Inventor(s): Jack ZHANG of Sam Jose CA (US) for nvidia corporation, Gordon GRIGOR of San Francisco CA (US) for nvidia corporation, Karsten PATZWALDT of San Francisco CA (US) for nvidia corporation, Riccardo MARIANI of Porto Azzurro (IT) for nvidia corporation
IPC Code(s): G06T7/593
CPC Code(s): G06T7/593
Abstract: the present disclosure relates to detecting objects in detection zones using multiple analysis techniques. the multiple analysis techniques may be used to analyze sensor data corresponding to the detection zones. the multiple analysis techniques may be selected based at least on at least two of the analysis techniques of the multiple analysis techniques having a computational diversity by performing different types of computational analyses on the sensor data with respect to each other, and at least two analysis techniques of the multiple analysis techniques having implementation diversity by being implemented on different types of computing platforms with respect to each other.
Inventor(s): Karsten Julian KREIS of Vancouver (CA) for nvidia corporation, Arash VAHDAT of San Mateo CA (US) for nvidia corporation, Yilun XU of Boston MA (US) for nvidia corporation
IPC Code(s): G06T11/00, G06F3/14
CPC Code(s): G06T11/00
Abstract: in various examples, systems and methods are disclosed relating to neural networks for synthetic data generation with discrete and continuous variable features. in training, an encoder can determine a plurality of encodings from a plurality of samples of training data, and the continuous generative model can operate as a decoder that is conditioned on the plurality of encodings to generate an estimated output to update the encoder and the continuous generative model. the discrete generative model can be trained over the plurality of encodings to learn to generate discrete variables corresponding to the distribution of information represented by the training data. at runtime, the discrete generative model can be used to generate a discrete variable from an input prompt, and can provide the discrete variable to the continuous generative model for the continuous generative model to generate an output, such an image, conditioned on the discrete variable.
Inventor(s): Zhengyu Huang of Shanghai (CN) for nvidia corporation, Rui Zhang of Beijing (CN) for nvidia corporation, Tao Li of Beijing (CN) for nvidia corporation, Yingying Zhong of Shanghai (CN) for nvidia corporation, Weihua Zhang of Beijing (CN) for nvidia corporation, Junjie Lai of Beijing (CN) for nvidia corporation, Yeongho Seol of Seoul (KR) for nvidia corporation, Dmitry Korobchenko of London (GB) for nvidia corporation, Simon Yuen of Playa Vista CA (US) for nvidia corporation
IPC Code(s): G06T13/20, G06T13/40, G10L15/16
CPC Code(s): G06T13/205
Abstract: systems and methods of the present disclosure include animating virtual avatars or agents according to input audio and one or more selected or determined emotions and/or styles. for example, a deep neural network can be trained to output motion or deformation information for a character that is representative of the character uttering speech contained in audio input. the character can have different facial components or regions (e.g., head, skin, eyes, tongue) modeled separately, such that the network can output motion or deformation information for each of these different facial components. during training, the network can use a transformer-based audio encoder with locked parameters to train an associated decoder using a weighted feature vector. the network output can be provided to a renderer to generate audio-driven facial animation that is emotion-accurate.
20250061729. IDENTIFYING POSITIONS OF OCCLUDED OBJECTS_simplified_abstract_(nvidia corporation)
Inventor(s): Prash Goel of Hisar (IN) for nvidia corporation, Umar Iqbal of Danville CA (US) for nvidia corporation, Akarsh Umesh Zingade of San Jose CA (US) for nvidia corporation, Pavlo Molchanov of Mountain View CA (US) for nvidia corporation
IPC Code(s): G06V20/64, G06T7/174, G06T7/70, G06V10/26, G06V10/82
CPC Code(s): G06V20/64
Abstract: apparatuses, systems, and techniques to identify three-dimensional positions of partially occluded objects in images. in at least one embodiment, one or more neural networks identify the three-dimensional positions of occluded portions of objects in a first image based, at least in part, on one or more second images including non-occluded objects.
Inventor(s): Tae Jin PARK of San Jose CA (US) for nvidia corporation, He HUANG of Greenville SC (US) for nvidia corporation, Jagadeesh BALAM of Campbell CA (US) for nvidia corporation
IPC Code(s): G10L13/02
CPC Code(s): G10L13/02
Abstract: in various examples, a technique for generating a simulated multi-speaker recording includes determining a first rate at which a first speech-based attribute occurs within a first portion of the simulated multi-speaker recording. the technique also includes computing a first difference between the first rate and a first target rate for the first speech-based attribute. the technique further includes determining, based at least on the first difference, a second rate at which the first speech-based attribute is to occur within a second portion of the simulated multi-speaker recording and generating the second portion of the simulated multi-speaker recording based at least on the second rate.
Inventor(s): Micha LIVNE of Ra'Annana (IL) for nvidia corporation, Danny Alexander REIDENBACH of San Jose CA (US) for nvidia corporation, Michelle Lynn GILL of New York NY (US) for nvidia corporation, Rajesh Kumar ILANGO of San Jose CA (US) for nvidia corporation, Yonatan ISRAELI of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G16C20/70
CPC Code(s): G16C20/70
Abstract: in various examples, systems and methods are disclosed relating to using machine learning models to generate small molecules with desired structural or physicochemical properties with high sampling efficiency. in some implementations, one or more processors receive a data structure representing a first small molecule and encode the data structure into a latent distribution of a fixed size using a machine learning model, thereby determining an encoded representation of the data structure. to generate new molecules with similar properties to the first small molecule, the processors apply noise to the encoded representation to determine a modified encoded representation. the modified encoded representation is decoded to determine a modified data structure representing a second small molecule different from the first small molecule.
Inventor(s): Xingqin Lin of San Jose CA (US) for nvidia corporation
IPC Code(s): H04B17/373, H04W24/08
CPC Code(s): H04B17/373
Abstract: apparatuses, systems, processors, circuits, and techniques to use one or more neural networks to predict a quality of one or more wireless signals based, at least in part, on one or more reference signals. in at least one embodiment, apparatuses, systems, processors, circuits, and techniques are to use one or more neural networks to determine that a radio link will be unstable or stable for a period of time or a number of frames (e.g., 10 consecutive frames).
Inventor(s): Arul Selvan Sekar of Bothell WA (US) for nvidia corporation, Elliot Andrew Simon of San Diego CA (US) for nvidia corporation
IPC Code(s): H04L67/12
CPC Code(s): H04L67/12
Abstract: in various examples, one or more logical interfaces are used to represent functional requirements of an architecture specification. the logical interfaces may indicate one or more dependencies of functionalities associated with a plurality of components of the architecture. using the logical interfaces, one or more physical interfaces between the components may be recursively determined and used to perform an operation using the plurality of components.
Inventor(s): Chunlin Li of Fremont CA (US) for nvidia corporation, Prashant Gaikwad of Cupertino CA (US) for nvidia corporation, Kaustubh Purandare of San Jose CA (US) for nvidia corporation
IPC Code(s): H04L67/51, H04L67/10
CPC Code(s): H04L67/51
Abstract: approaches presented herein provide systems and methods for generating a standardized specification and associated interface for application development. one or more microservices may be selected and graphically represented within an interface that receives connection information from one or more users. connected microservices may have one or more configuration specifications that are auto-populated based, at least, on operation parameters for an associated application and/or related microservices. a development environment may provide for visual representations of connections between microservices along with configuration parameters and validation services. deployment information may then be generated based on the configuration in the representations.
Inventor(s): Chong S. Tan of The Woodlands TX (US) for nvidia corporation, Jiaheng Zhang of Santa Clara CA (US) for nvidia corporation, Jason Yu Chih Su of San Jose CA (US) for nvidia corporation, Helen Hueijung Liu of Los Angeles CA (US) for nvidia corporation
IPC Code(s): H05K7/20, F16L55/00
CPC Code(s): H05K7/20272
Abstract: systems and methods herein are for hose management in a computing module. a rotatable support structure includes a moveable inset structure and is to support rotation movement of cooling hoses that are to cool underlying devices in the computing module, where the rotation movement is about an axis of the computing module to allow the cooling hoses to be moved away from the underlying devices of the computing module and where the movable inset structure is movable within the rotatable support structure to receive tension on the cooling hoses from being coupled to a manifold of the computing module.
NVIDIA Corporation patent applications on February 20th, 2025
- NVIDIA Corporation
- B60Q1/14
- G06V10/60
- G06V10/82
- G06V20/56
- CPC B60Q1/143
- Nvidia corporation
- B60R22/48
- G06T7/60
- G06T7/73
- CPC B60R22/48
- B60W60/00
- G01C21/00
- CPC B60W60/001
- CPC B60W60/0027
- G06F7/544
- G06F5/01
- G06F7/50
- G06F7/523
- CPC G06F7/5443
- G06F13/40
- G06F12/0831
- G06F15/173
- CPC G06F13/4031
- G06F16/901
- G06F30/13
- G06F30/27
- G06N3/044
- G06N3/045
- G06N3/047
- G06N3/08
- G06N3/084
- G06N5/04
- G06N20/10
- G06N20/20
- G06V10/764
- G06V10/84
- G06V20/10
- CPC G06F16/9024
- CPC G06N3/08
- G06N3/096
- CPC G06N3/096
- G06N10/20
- CPC G06N10/20
- G06T7/194
- G06T5/50
- G06V10/774
- CPC G06T7/194
- G06T7/593
- CPC G06T7/593
- G06T11/00
- G06F3/14
- CPC G06T11/00
- G06T13/20
- G06T13/40
- G10L15/16
- CPC G06T13/205
- G06V20/64
- G06T7/174
- G06T7/70
- G06V10/26
- CPC G06V20/64
- G10L13/02
- CPC G10L13/02
- G16C20/70
- CPC G16C20/70
- H04B17/373
- H04W24/08
- CPC H04B17/373
- H04L67/12
- CPC H04L67/12
- H04L67/51
- H04L67/10
- CPC H04L67/51
- H05K7/20
- F16L55/00
- CPC H05K7/20272
