NVIDIA Corporation patent applications on December 26th, 2024
Patent Applications by NVIDIA Corporation on December 26th, 2024
NVIDIA Corporation: 17 patent applications
NVIDIA Corporation has applied for patents in the areas of B60W60/00 (3), G06F9/54 (2), G06T1/60 (2), G06T1/20 (2), G06N3/08 (2) G06T1/60 (2), B60W60/001 (1), G01C21/3492 (1), G05D1/0027 (1), G06F1/12 (1)
With keywords such as: mission, systems, data, task, lane, change, based, road, storages, and behavior in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): David ELLIOTT of San Jose CA (US) for nvidia corporation, Gordon GRIGOR of San Francisco CA (US) for nvidia corporation
IPC Code(s): B60W60/00, G06N3/08
CPC Code(s): B60W60/001
Abstract: in various examples, behavior-based mission task management for mobile autonomous machine systems and applications are provided. a mission controller may generate a mission behavior model logic framework for a mission that accounts for the actions of a set of multiple task agents that play a role in completing the mission. the mission controller may assemble a framework starting from a mission template that defines a baseline task sequence, correlate tasks defined by the baseline task sequence with pre-defined behavior models from a task library, and customize those behavior models based on mission task customization parameters. the mission controller may provide the mission behavior model logic framework to a mission dispatch function. individual autonomous mobile task agents may then proceed to execute their assigned portions of local task sequences in accordance with the customized behavior models distributed to them by the mission dispatch function.
Inventor(s): Ronghua ZHANG of Campbell CA (US) for nvidia corporation, Marlene WAN of Cupertino CA (US) for nvidia corporation, Yinghui YAO of San Ramon CA (US) for nvidia corporation
IPC Code(s): G01C21/34, G08G1/01
CPC Code(s): G01C21/3492
Abstract: a computer-implemented method may comprise: receiving sensor data from a sensor of an autonomous vehicle; determining a presence of a lane closure object located on a lane element; determining a change of the lane closure object, selected from the presence of the lane closure object or absence of the lane closure object on the lane element; generating a change candidate based on the change in the lane closure object; obtaining a plurality of the change candidates during a time period or the autonomous vehicle being on a preceding lane element on the route; analyzing the plurality of change candidates for the change being the presence of the lane closure object or the absence of the lane closure object on the lane element; generating a final change candidate based on the change; and providing the final change candidate for updating a high definition map of the route having the lane element.
Inventor(s): David ELLIOTT of San Jose CA (US) for nvidia corporation, Gordon GRIGOR of San Francisco CA (US) for nvidia corporation
IPC Code(s): G05D1/00, B60W60/00, G06N3/08
CPC Code(s): G05D1/0027
Abstract: in various examples, behavior-based mission task management for mobile autonomous machine systems and applications are provided. a mission controller may generate a mission behavior model logic framework for a mission that accounts for the actions of a set of multiple task agents that play a role in completing the mission. the mission controller may assemble a framework starting from a baseline task sequence, correlate tasks defined by the baseline task sequence with pre-defined behavior models, and customize those behavior models based on mission task customization parameters. the mission controller may provide the mission behavior model logic framework to a mission dispatch function. individual autonomous mobile task agents may then proceed to execute their assigned portions of local task sequences in accordance with the customized behavior models distributed to them by the mission dispatch function.
Inventor(s): Sean Gillen of Sunnyvale CA (US) for nvidia corporation, Blake McHale of San Jose CA (US) for nvidia corporation, Marc R. Delvaux of Palo Alto CA (US) for nvidia corporation, Sheng-Lin Lo of San Jose CA (US) for nvidia corporation, Gordon Grigor of San Francisco CA (US) for nvidia corporation
IPC Code(s): G06F1/12
CPC Code(s): G06F1/12
Abstract: in various examples, sets of correlated timestamps are sampled from clock sources. the sets of correlated timestamps are used to compute translation data, such as offsets and/or rates of change of the clock sources. the offsets and/or rates of change may be used to translate a timestamp to a reference time domain. the sampled clock sources may be frequency locked and the translation may be performed without using the rates of change. for example, a running average of the offsets may be used to perform the translation. the translated timestamps and corresponding sensor measurements may be provided to one or more applications for use in performing one or more operations for a machine, such as perception and/or control operations.
20240427605. AUTOMATIC COMPUTE KERNEL GENERATION_simplified_abstract_(nvidia corporation)
Inventor(s): Justin Paul Luitjens of Sandy UT (US) for nvidia corporation, Clifford Keith Burdick of Vista CA (US) for nvidia corporation, Jacob Ryan Hemstad of Bloomington MN (US) for nvidia corporation
IPC Code(s): G06F9/38, G06F9/30, G06F9/355, G06F9/54
CPC Code(s): G06F9/3877
Abstract: apparatuses, systems, and techniques to receive, by a first processor, a multi-dimensional data structure and an operation to be performed on at least a first element of the multi-dimensional data structure; generate, by the first processor and using at least one of template metaprogramming or operator overloading, one or more operators to perform the operation on at least the first element of the multi-dimensional data structure; and generate, by the first processor, a kernel that comprises the one or more operators, wherein the kernel is executable by a second processor.
Inventor(s): Fnu Vishnuswaroop Ramesh of San Jose CA (US) for nvidia corporation, Vivek Belve Kini of San Jose CA (US) for nvidia corporation, Jeremy Iverson of Monticello MN (US) for nvidia corporation, Nishank Niranjan Chandawala of San Jose CA (US) for nvidia corporation, Dimitar Haralampiev Haralanov of Foster City CA (US) for nvidia corporation, Mark Hairgrove of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F9/50, G06F9/54
CPC Code(s): G06F9/5016
Abstract: apparatuses, systems, and techniques to indicate whether one or more storages correspond to one or more non-uniform memory access (numa) storages. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to indicate whether one or more storages indicated by one or more users of the api corresponds to one or more numa storages or one or more graphics processing unit (gpu) storages.
Inventor(s): Fnu Vishnuswaroop Ramesh of San Jose CA (US) for nvidia corporation, Vivek Belve Kini of San Jose CA (US) for nvidia corporation, Jeremy Iverson of Monticello MN (US) for nvidia corporation, Nishank Niranjan Chandawala of San Jose CA (US) for nvidia corporation, Dimitar Haralampiev Haralanov of Foster City CA (US) for nvidia corporation, Mark Hairgrove of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F12/02, G06F12/0862, G06F13/16
CPC Code(s): G06F12/0238
Abstract: apparatuses, systems, and techniques to cause information to be read from one or more non-uniform memory access (numa) storages. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to cause information to be read from one or more numa storages or one or more graphics processor unit (gpu) physical storages based, at least in part, on one or more indicators to be indicated by one or more users of the api.
Inventor(s): Thorsten Peter Stremlau of Cary NC (US) for nvidia corporation, Joseph Michael Pennisi of Apex NC (US) for nvidia corporation
IPC Code(s): G06F21/83, G06F3/04842, G06F21/84, H04L9/32
CPC Code(s): G06F21/83
Abstract: a system includes a graphics card comprising a first storage area accessible by an operating system and a second storage area inaccessible by the operating system. a processing device coupled to the graphics card can cause, via one or more drivers associated with the operating system, a first screen to be presented in a graphical user interface (gui) at a user device based on data read from the first storage area. the processing device can also cause, via one or more drivers associated with the graphics card, a second screen to be presented in the gui based on data read from the second storage area, wherein the second screen overlays a portion of the first screen and presents one or more selectable inputs for authentication.
Inventor(s): Enas Abdullah M Albasiri of Brooklyn NY (US) for nvidia corporation, Oluwatobi Olabiyi of Falls Church VA (US) for nvidia corporation, Mariana Voronel of New York NY (US) for nvidia corporation
IPC Code(s): G06F40/284, G06F40/211
CPC Code(s): G06F40/284
Abstract: systems and methods provide for a machine learning system to tokenize, classify, and generate representations from a provided input to provide a combined output. an input may be received and processed into tokens for classification based on semiotic classes. for a given semiotic class, particular rule-based algorithms may be selected to generate a desired output for a selected output language. an input may include an auditory or textual input, which may be in a different language from the selected output language, where the particular rule-based algorithms may include morphological rules for particular semiotic classes. different rule-based algorithms may be modularly generated for particular languages and semiotic classes to build a library of models for processing different inputs.
Inventor(s): Xianchao Wu of Tokyo (JP) for nvidia corporation, Simon SEE Chong Wee of West Coast Rise (SG) for nvidia corporation
IPC Code(s): G06F40/58, G10L15/06, G10L15/16, G10L25/18
CPC Code(s): G06F40/58
Abstract: disclosed are apparatuses, systems, and techniques that may use machine learning for reversible translations of speech utterances. the techniques include training and using duplex neural networks (nns) having a first subnetwork and a second subnetwork that are mirror images of each other. training data for training the duplex nns may include a target output that includes a first speech utterance in a first language, a first training input that includes the target output distorted by a noise, and a second training input that includes a second speech utterance in a second language. the duplex nns may be trained to identify, using the first training input and the second training input, at least one of the target output or the first noise.
Inventor(s): Fnu Vishnuswaroop Ramesh of San Jose CA (US) for nvidia corporation, Vivek Belve Kini of San Jose CA (US) for nvidia corporation, Jeremy Iverson of Monticello MN (US) for nvidia corporation, Nishank Niranjan Chandawala of San Jose CA (US) for nvidia corporation, Dimitar Haralampiev Haralanov of Foster City CA (US) for nvidia corporation, Mark Hairgrove of San Jose CA (US) for nvidia corporation
IPC Code(s): G06T1/60, G06T1/20
CPC Code(s): G06T1/60
Abstract: apparatuses, systems, and techniques to access one or more non-uniform memory access (numa) nodes. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to cause one or more numa nodes or one or more physical addresses allocated to one or more graphics processing units (gpus) to be accessed based, at least in part, on one or more indications within the api.
Inventor(s): Fnu Vishnuswaroop Ramesh of San Jose CA (US) for nvidia corporation, Vivek Belve Kini of San Jose CA (US) for nvidia corporation, Jeremy Iverson of Monticello MN (US) for nvidia corporation, Nishank Niranjan Chandawala of San Jose CA (US) for nvidia corporation, Dimitar Haralampiev Haralanov of Foster City CA (US) for nvidia corporation, Mark Hairgrove of San Jose CA (US) for nvidia corporation
IPC Code(s): G06T1/60, G06T1/20
CPC Code(s): G06T1/60
Abstract: apparatuses, systems, and techniques to store information within one or more non-uniform memory access (numa) storages. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to cause information to be stored within one or more numa storages or one or more graphics processor unit (gpu) physical storages based, at least in part, on one or more indicators to be indicated by one or more users of the api.
Inventor(s): Prabindh Sundareson of Bangalore (IN) for nvidia corporation, Suresh Yerva of Bengaluru (IN) for nvidia corporation, Shyam Kalidas Raikar of Pune (IN) for nvidia corporation
IPC Code(s): G06T3/40, G06V10/54
CPC Code(s): G06T3/4053
Abstract: approaches presented herein provide for the generation, transmission, and upsampling of content for presentation using devices with varying graphics capabilities. various computing devices can include integrated gpus or other limited capacity hardware that may be unable to support higher performance graphics upscaler algorithms, and can thus default to using a process such as hardware-implemented bilinear filtering for upscaling, resulting in lower quality displayed images. an adaptive filter can be used to reduce the number of texture accesses needed per pixel, which can provide for improved perceptive quality and increased device support. a number of input samples to be taken for an output pixel location can be adapted to the capacity of the device to perform the upsampling, where a reduced number of samples or “taps” per pixel can significantly reduce the resource capacity needed to perform upscaling and interpolation using a catnumm-rom filter or lanczos filter, implemented as a gpu shader, and allow higher quality upscaling on limited capacity systems.
Inventor(s): Yixuan Lin of San Jose CA (US) for nvidia corporation, Yu Zhang of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G06T7/73
CPC Code(s): G06T7/74
Abstract: in various examples, determining locations of road markings or other features for autonomous and semi-autonomous systems and applications is described. systems and methods are disclosed that use lidar data—and/or other sensor data types—to determine the locations of road markings, such as lane lines, within environments. for instance, sensor data, such as image data, may initially be processed in order to determine an initial location associated with a road marking. the lidar data may then be used to increase the precision of the initial location associated with the road marking. for example, a lidar image(s) may be used to determine the actual location of the road marking, such as the center of paint associated with a lane line. additionally, the initial location of the road marking may be updated, such as adjusted within a direction, based on the actual location of the road marking.
Inventor(s): Kang WANG of Bellevue WA (US) for nvidia corporation, Yue WU of Mountain View CA (US) for nvidia corporation, Minwoo PARK of Saratoga CA (US) for nvidia corporation, Gang PAN of Fremont CA (US) for nvidia corporation
IPC Code(s): G06T17/05, B60W30/09, B60W30/14, B60W40/06, B60W50/06, B60W60/00, G06F18/214, G06V20/05, G06V20/58
CPC Code(s): G06T17/05
Abstract: in various examples, to support training a deep neural network (dnn) to predict a dense representation of a 3d surface structure of interest, a training dataset is generated using a parametric mathematical modeling. a variety of synthetic 3d road surfaces may be generated by modeling a 3d road surface using varied parameters to simulate changes in road direction and lateral surface slope. in an example embodiment, a synthetic 3d road surface may be created by modeling a longitudinal 3d curve and expanding the longitudinal 3d curve to a 3d surface, and the resulting synthetic 3d surface may be sampled to form a synthetic ground truth projection image (e.g., a 2d height map). to generate corresponding input training data, a known pattern that represents which pixels may remain unobserved during 3d structure estimation may be generated and applied to a ground truth projection image to simulate a corresponding sparse projection image.
Inventor(s): Parthiv Parikh of Santa Clara CA (US) for nvidia corporation, Mehmet K. Kocamaz of San Jose CA (US) for nvidia corporation
IPC Code(s): G06V20/58
CPC Code(s): G06V20/58
Abstract: in various examples, object track management for autonomous or semi-autonomous systems and applications is described herein. systems and methods are disclosed that may limit the number of objects that are tracked based on one or more criteria. for instance, the number of objects that are tracked may be limited to a threshold number of objects when a number of detected objects exceeds a threshold. the systems and methods may use parameters associated with the detected objects to determine priority scores associated with the detected objects, and may then determine to only track the detected objects with the highest scores (e.g., high priority objects). as a result, latency and compute of the system may be reduced while still maintaining tracking with respect to safety-critical objects.
20240430037. PARITY CHECK DECODING_simplified_abstract_(nvidia corporation)
Inventor(s): Victor Podlozhnyuk of Reading (GB) for nvidia corporation, Nirmal Saxena of Los Altos Hills CA (US) for nvidia corporation, Yanxiang Huang of San Jose CA (US) for nvidia corporation
IPC Code(s): H04L1/00, H04W28/04
CPC Code(s): H04L1/0076
Abstract: apparatuses, systems, and techniques to decode encoded data. in at least one embodiment, parts of information for decoding the encoded data is provided to a plurality of processors, and parts of data decoded by the plurality of processors is combined.
NVIDIA Corporation patent applications on December 26th, 2024
- NVIDIA Corporation
- B60W60/00
- G06N3/08
- CPC B60W60/001
- Nvidia corporation
- G01C21/34
- G08G1/01
- CPC G01C21/3492
- G05D1/00
- CPC G05D1/0027
- G06F1/12
- CPC G06F1/12
- G06F9/38
- G06F9/30
- G06F9/355
- G06F9/54
- CPC G06F9/3877
- G06F9/50
- CPC G06F9/5016
- G06F12/02
- G06F12/0862
- G06F13/16
- CPC G06F12/0238
- G06F21/83
- G06F3/04842
- G06F21/84
- H04L9/32
- CPC G06F21/83
- G06F40/284
- G06F40/211
- CPC G06F40/284
- G06F40/58
- G10L15/06
- G10L15/16
- G10L25/18
- CPC G06F40/58
- G06T1/60
- G06T1/20
- CPC G06T1/60
- G06T3/40
- G06V10/54
- CPC G06T3/4053
- G06T7/73
- CPC G06T7/74
- G06T17/05
- B60W30/09
- B60W30/14
- B60W40/06
- B60W50/06
- G06F18/214
- G06V20/05
- G06V20/58
- CPC G06T17/05
- CPC G06V20/58
- H04L1/00
- H04W28/04
- CPC H04L1/0076
