NVIDIA Corporation patent applications on December 12th, 2024
Patent Applications by NVIDIA Corporation on December 12th, 2024
NVIDIA Corporation: 17 patent applications
NVIDIA Corporation has applied for patents in the areas of G01S13/931 (2), G06N3/045 (2), G06F9/50 (2), G06N20/00 (2), G01S13/72 (2) G01S13/723 (2), G01C21/3446 (1), G01D21/02 (1), G01K1/02 (1), G01S7/4802 (1)
With keywords such as: data, reference, object, processing, component, circuit, based, graph, such, and voltage in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Trung Pham of San Jose CA (US) for nvidia corporation, Minwoo Park of Saratoga CA (US) for nvidia corporation, Ha Giang Truong of Joondalup (AU) for nvidia corporation, Atchuta Venkata Vijay Chintalapudi of Visakhapatnam (IN) for nvidia corporation, Hae-Jong Seo of Campbell CA (US) for nvidia corporation
IPC Code(s): G01C21/34, G06N20/00
CPC Code(s): G01C21/3446
Abstract: in various examples, path detection using machine learning models for autonomous or semi-autonomous systems and applications is described herein. systems and methods are disclosed that use one or more machine learning models to determine a geometry associated with a path for a vehicle. to determine the geometry, the machine learning model(s) may process sensor data generated using the vehicle and, based at least on the processing, output points associated with the path. in some examples, the machine learning model(s) outputs a limited number of points, such as between five and twenty points. one or more algorithms, such as one or more bezier algorithms, may then be used to generate the geometry based at least on the points. as such, in some examples, the geometry may correspond to a bezier curve that represents the path.
Inventor(s): Parthiv PARIKH of San Jose CA (US) for nvidia corporation, Yongqing LIANG of San Jose CA (US) for nvidia corporation, Mehmet Kemal KOCAMAZ of San Jose CA (US) for nvidia corporation, Alessandro FERRARI of Brescia (IT) for nvidia corporation, Daniel Per Olof SVENSSON of Gothenburg (SE) for nvidia corporation
IPC Code(s): G01D21/02
CPC Code(s): G01D21/02
Abstract: in various examples, disclosed techniques introduce a time-window based sensor measurement scheduling engine that determines an ordering of measurements received from multiple sensors. the measurements may be sorted by detection time and submitted in sorted order to a sensor fusion system. upon receiving measurements from sensors, the scheduling engine determines a current time window between a most recently-submitted measurement and a most recent camera measurement. any measurements from other sensors, such as radar, that are less than a threshold amount of time ahead of or behind the current time window can be extrapolated to a time in the current time window for comparison with camera measurements. the scheduling engine then sorts the selected measurements based on their timestamps in the current time window, and submits the selected measurements to the fusion system in sorted order. the system may then perform downstream operations, such as object tracking, using the sorted measurements.
Inventor(s): Naor Peretz of Nahariya (IL) for nvidia corporation, Ofek Abadi of Kfar (IL) for nvidia corporation, Ido Bourstein of Pardes Hana (IL) for nvidia corporation
IPC Code(s): G01K1/02, G05F1/56
CPC Code(s): G01K1/02
Abstract: an integrated circuit includes a bandgap reference circuit configured to generate, from a digital chip supply voltage, a reference voltage and a proportional-to-absolute temperature (ptat) voltage. a voltage-to-frequency (vtf) readout circuit to receive the reference voltage and the ptat voltage as inputs. the vtf readout circuit includes sets of switched capacitors that operate as a voltage divider. the capacitors of the sets of switched capacitors are selectively charged by the ptat voltage and generate a feedback voltage. a voltage-controlled oscillator (vco) is driven by a difference between the feedback voltage and the reference voltage and generates a vco clock. a clock generator generates a feedback clock based on the vco clock. first switches of the sets of switched capacitors are controlled by the feedback clock.
Inventor(s): Nikolai Smolyanskiy of Seattle WA (US) for nvidia corporation, Ryan Oldja of Redmond WA (US) for nvidia corporation, Ke Chen of Sunnyvale CA (US) for nvidia corporation, Alexander Popov of Kirkland WA (US) for nvidia corporation, Joachim Pehserl of Lynnwood WA (US) for nvidia corporation, Ibrahim Eden of Redmond WA (US) for nvidia corporation, Tilman Wekel of Sunnyvale CA (US) for nvidia corporation, David Wehr of Redmond WA (US) for nvidia corporation, Ruchi Bhargava of Redmond WA (US) for nvidia corporation, David Nister of Bellevue WA (US) for nvidia corporation
IPC Code(s): G01S7/48, B60W60/00, G01S17/89, G01S17/931, G05D1/81, G06N3/045, G06T19/00, G06V10/10, G06V10/25, G06V10/26, G06V10/44, G06V10/764, G06V10/774, G06V10/80, G06V10/82, G06V20/56, G06V20/58
CPC Code(s): G01S7/4802
Abstract: a deep neural network(s) (dnn) may be used to detect objects from sensor data of a three dimensional (3d) environment. for example, a multi-view perception dnn may include multiple constituent dnns or stages chained together that sequentially process different views of the 3d environment. an example dnn may include a first stage that performs class segmentation in a first view (e.g., perspective view) and a second stage that performs class segmentation and/or regresses instance geometry in a second view (e.g., top-down). the dnn outputs may be processed to generate 2d and/or 3d bounding boxes and class labels for detected objects in the 3d environment. as such, the techniques described herein may be used to detect and classify animate objects and/or parts of an environment, and these detections and classifications may be provided to an autonomous vehicle drive stack to enable safe planning and control of the autonomous vehicle.
Inventor(s): James CRITCHLEY of Lake Orion MI (US) for nvidia corporation, Kyle KOLASINSKI of Howell MI (US) for nvidia corporation, Brian DOBKOWSKI of Merrick NY (US) for nvidia corporation
IPC Code(s): G01S13/72, G01S7/41, G01S13/58, G01S13/931
CPC Code(s): G01S13/723
Abstract: one or more embodiments of the present disclosure relate to identifying reference portions corresponding to a bounding shape that corresponds to an object. additionally, the reference portions may include a first reference edge, a second reference edge, and a reference where the first reference edge and the second reference edge intersect. in some embodiments, operations may further include obtaining a first state estimate corresponding to the object and receiving first sensor data corresponding to a first portion of the object, the first sensor data including a first position measurement. further, operations may further include determining that the first position measurement corresponds to a first reference portion that is one of the reference portions corresponding to the bounding shape and determining a first expected position corresponding to the first portion based at least on the first reference portion. embodiments may additionally include determining a second position estimate corresponding to the object.
Inventor(s): James CRITCHLEY of Lake Orion MI (US) for nvidia corporation, Kyle KOLASINSKI of Howell MI (US) for nvidia corporation, Shane MURRAY of San Jose CA (US) for nvidia corporation
IPC Code(s): G01S13/72, G01S13/42, G01S13/931
CPC Code(s): G01S13/723
Abstract: one or more embodiments of the present disclosure relate to obtaining a first state estimate corresponding to an object, the first state estimate including a first velocity vector estimate corresponding to the object. the disclosure may further relate to receiving first sensor data corresponding to a first portion of the object. the embodiments may further include determining a first expected measurement corresponding to the first portion, the first expected measurement including a first expected range rate determined based at least on the first angle measurement and the first velocity vector estimate of the first state estimate. and, determining a second state estimate corresponding to the object, the second state estimate including a second velocity vector estimate corresponding to the object and determined based at least on the first range rate measurement and the first expected range rate.
Inventor(s): Vishvesh VIJAYWARGIYA of Bangalore (IN) for nvidia corporation, Lalit ADITHYA V of Bangalore (IN) for nvidia corporation, Krishnan DURAISAMY of San Jose CA (US) for nvidia corporation, Rohit RAJANI of Shajapur (IN) for nvidia corporation, Gopi VADLAMUDI of Fremont CA (US) for nvidia corporation, Andrew STOCK of Placentia CA (US) for nvidia corporation, Alexander PELAVIN of Palo Alto CA (US) for nvidia corporation, Shivam MISHRA of Sacramento CA (US) for nvidia corporation, Prathik KOTIAN of Coimbatore (IN) for nvidia corporation
IPC Code(s): G06F8/65
CPC Code(s): G06F8/65
Abstract: an application management platform comprising at least a packaging and bundling component, a deployment management component, and an update component. the packaging and bundling component versions, packages, and bundles a plurality of infrastructure components for a remote data center. the deployment management component provisions one or more nodes of the remote data center with the plurality of infrastructure components for an application. the update component monitors available updates to one or more of the plurality of infrastructure components used by the remote data center and facilitates update of the one or more of the plurality of infrastructure components at the remote data center.
Inventor(s): Michael Murphy of Boston MA (US) for nvidia corporation
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5038
Abstract: approaches presented herein provide for the optimization of tasks performed for an operation such as the rendering of an image. a frame interceptor (fi) can generate a resource dependency graph (rdg) by intercepting api calls during the rendering process and determining dependencies. fi can analyze the rdg to identify potential optimizations, such as may correspond to reordering or parallel execution of certain tasks. fi can automatically test optimizations to determine whether sufficient improvement is obtained. this testing can be performed in real time by replacing the originally intercepted api calls with the newly ordered api calls generated by fi. fi can then issue a report that indicates information such as the changes made, the time taken to render the image, and potentially the fact that the images were determined to be identical.
Inventor(s): Vishvesh VIJAYWARGIYA of Bangalore (IN) for nvidia corporation, Lalit ADITHYA V of Bangalore (IN) for nvidia corporation, Krishnan DURAISAMY of San Jose CA (US) for nvidia corporation, Rohit RAJANI of Shajapur (IN) for nvidia corporation, Gopi VADLAMUDI of Fremont CA (US) for nvidia corporation, Andrew STOCK of Placentia CA (US) for nvidia corporation, Alexander PELAVIN of Palo Alto CA (US) for nvidia corporation, Shivam MISHRA of Sacramento CA (US) for nvidia corporation, Prathik KOTIAN of Coimbatore (IN) for nvidia corporation
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5077
Abstract: an application management platform comprising at least a packaging and bundling component, a deployment management component, and an update component. the packaging and bundling component versions, packages, and bundles a plurality of infrastructure components for a remote data center. the deployment management component provisions one or more nodes of the remote data center with the plurality of infrastructure components for an application. the update component monitors available updates to one or more of the plurality of infrastructure components used by the remote data center and facilitates update of the one or more of the plurality of infrastructure components at the remote data center.
Inventor(s): William James Dally of Incline Village NV (US) for nvidia corporation, Carl Thomas Gray of Apex NC (US) for nvidia corporation, Stephen W. Keckler of Austin TX (US) for nvidia corporation, James Michael O'Connor of Austin TX (US) for nvidia corporation
IPC Code(s): G06F13/16, G11C8/12, H03K19/1776
CPC Code(s): G06F13/161
Abstract: embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. in an embodiment, one or more memory dies are stacked on the processor die. the processor die includes multiple processing tiles and each memory die includes multiple memory tiles. vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. an application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.
Inventor(s): Chia-Tung HO of Santa Clara CA (US) for nvidia corporation, Haoxing Ren of Austin TX (US) for nvidia corporation
IPC Code(s): G06F30/392, G06F30/394
CPC Code(s): G06F30/392
Abstract: lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. the metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during routing of the nets for the circuit, a graph comprising virtual nodes and edges from the virtual nodes to grid locations for pins external to the circuit is generated. routing to the external net of the circuit is performed according to the graph nodes and the graph edges.
Inventor(s): Chia-Tung HO of Santa Clara CA (US) for nvidia corporation, Haoxing Ren of Austin TX (US) for nvidia corporation
IPC Code(s): G06F30/394, G06F30/392
CPC Code(s): G06F30/394
Abstract: lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. the metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during routing of the nets for the circuit, a graph comprising virtual nodes and edges from the virtual nodes to grid locations for pins external to the circuit is generated. routing to the external net of the circuit is performed according to the graph nodes and the graph edges.
Inventor(s): Dong ZHANG of Churchill TN (US) for nvidia corporation, Tae Eun CHOE of Belmont CA (US) for nvidia corporation, Seungwoo YOO of Yongin (KR) for nvidia corporation, Sangmin OH of San Jose CA (US) for nvidia corporation, Minwoo PARK of Saratoga CA (US) for nvidia corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: systems and methods are disclosed that relate to training a machine learning system using simulated objects. a simulated object may be generated based at least on extracting at least a portion of the simulated object from a simulated textured representation. further, the simulated anomaly object may be combined with an existing image to generate a training image. one or more parameters of a machine learning model may be updated based at least on the training image and ground truth data corresponding to the training image.
Inventor(s): Rui Zhang of Beijing (CN) for nvidia corporation, Zhengyu Huang of Zhejiang (CN) for nvidia corporation, Lance Li of Beijing (CN) for nvidia corporation, Weihua Zhang of Beijing (CN) for nvidia corporation, Yingying Zhong of Anhui (CN) for nvidia corporation, Junjie Lai of Beijing (CN) for nvidia corporation, Yeongho Seol of Seoul (KR) for nvidia corporation, Dmitry Korobchenko of Yerevan (AM) for nvidia corporation
IPC Code(s): G06T13/40, G06N3/045, G06N3/094, G10L25/30, G10L25/63
CPC Code(s): G06T13/40
Abstract: in various examples, techniques are described for animating characters by decoupling portions of a face from other portions of the face. systems and methods are disclosed that use one or more neural networks to generate high-fidelity facial animation using inputted audio data. in order to generate the high-fidelity facial animations, the systems and methods may decouple effects of implicit emotional states from effects of audio on the facial animations during training of the neural network(s). for instance, the training may cause the audio to drive the lower face animations while the implicit emotional states drive the upper face animations. in some examples, in order to encourage more expressive expressions, adversarial training is further used to learn a discriminator that predicts if generated emotional states are from real distribution.
Inventor(s): Jacopo Pantaleoni of Berlin (DE) for nvidia corporation
IPC Code(s): G06T15/06, G06T15/50, G06T17/20
CPC Code(s): G06T15/06
Abstract: disclosed approaches provide for interactions of light transport paths in a virtual environment to share directional radiance when rendering a scene. directional radiance that may be shared includes outgoing directional radiance of interactions, incoming directional radiance of interactions, and/or information derived therefrom. the shared directional radiance may be used for various purposes, such as computing lighting contributions at one or more interactions of a light transport path, and/or for path guiding. directional radiance of an interaction may be shared with another interaction when the interaction is sufficiently similar (e.g., in radiance direction) to serve as an approximation of a sample for the other interaction. sharing directional radiance may provide for online learning of directional radiance, which may build finite element approximations of light fields at the interactions.
Inventor(s): Shagan Sah of Santa Clara CA (US) for nvidia corporation, Nishant Puri of San Francisco CA (US) for nvidia corporation, Yuzhuo Ren of Sunnyvale CA (US) for nvidia corporation, Rajath Bellipady Shetty of Sunnyvale CA (US) for nvidia corporation, Weili Nie of Sunnyvale CA (US) for nvidia corporation, Arash Vahdat of San Mateo CA (US) for nvidia corporation, Animashree Anandkumar of Pasadena CA (US) for nvidia corporation
IPC Code(s): G06V10/776, G06N3/094, G06T11/00, G06V10/75, G06V10/774, G06V10/82, G06V40/16
CPC Code(s): G06V10/776
Abstract: apparatuses, system, and techniques use one or more first neural networks to generate one or more synthetic data to train one or more second neural networks based, at least in part, on one or more performance metrics of one or more second neural networks.
Inventor(s): Amit Parikh of Santa Clara CA (US) for nvidia corporation, Ganapathy Raman Kasi of Fremont CA (US) for nvidia corporation, Olivier Lapicque of Deerfield Beach FL (US) for nvidia corporation
IPC Code(s): H04N21/2347, H04L9/40
CPC Code(s): H04N21/2347
Abstract: in various examples, processing content data using graphics processing units for video streaming systems and applications is described herein. systems and methods are disclosed that offload at least a portion of the processing that is typically performed by a central processing unit (cpu) to a graphics processing unit (gpu). for example, and for a streaming application, the gpu may initially generate and then encode a content stream (e.g., a video stream, an audio stream, etc.). in some examples, the gpu generates and/or encodes the content stream based on input data received from one or more client devices. the gpu may then perform additional processing associated with the encoded content stream, such as packetization, forward error correction (fec), encryption, and/or any other processing. the cpu may then use packet pacing when causing the processed content stream to be streamed to the client device(s).
NVIDIA Corporation patent applications on December 12th, 2024
- NVIDIA Corporation
- G01C21/34
- G06N20/00
- CPC G01C21/3446
- Nvidia corporation
- G01D21/02
- CPC G01D21/02
- G01K1/02
- G05F1/56
- CPC G01K1/02
- G01S7/48
- B60W60/00
- G01S17/89
- G01S17/931
- G05D1/81
- G06N3/045
- G06T19/00
- G06V10/10
- G06V10/25
- G06V10/26
- G06V10/44
- G06V10/764
- G06V10/774
- G06V10/80
- G06V10/82
- G06V20/56
- G06V20/58
- CPC G01S7/4802
- G01S13/72
- G01S7/41
- G01S13/58
- G01S13/931
- CPC G01S13/723
- G01S13/42
- G06F8/65
- CPC G06F8/65
- G06F9/50
- CPC G06F9/5038
- CPC G06F9/5077
- G06F13/16
- G11C8/12
- H03K19/1776
- CPC G06F13/161
- G06F30/392
- G06F30/394
- CPC G06F30/392
- CPC G06F30/394
- CPC G06N20/00
- G06T13/40
- G06N3/094
- G10L25/30
- G10L25/63
- CPC G06T13/40
- G06T15/06
- G06T15/50
- G06T17/20
- CPC G06T15/06
- G06V10/776
- G06T11/00
- G06V10/75
- G06V40/16
- CPC G06V10/776
- H04N21/2347
- H04L9/40
- CPC H04N21/2347
