NVIDIA Corporation patent applications on August 29th, 2024
Patent Applications by NVIDIA Corporation on August 29th, 2024
NVIDIA Corporation: 14 patent applications
NVIDIA Corporation has applied for patents in the areas of G06F9/54 (5), G06F9/30 (4), G06F9/38 (4), G06F9/52 (2), G06F13/16 (2) A63F13/73 (1), G06F9/3004 (1), G06F9/3009 (1), G06F9/3887 (1), G06F9/52 (1)
With keywords such as: interface, performed, memory, systems, api, operations, perform, techniques, gaze, and instructions in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Lucien Dunning of Ramsey NJ (US) for nvidia corporation, Seth Schneider of San Jose CA (US) for nvidia corporation, Dwayne Swoboda of San Jose CA (US) for nvidia corporation, Marko Mitic of San Jose CA (US) for nvidia corporation, Daniel Rohrer of Cary NC (US) for nvidia corporation
IPC Code(s): A63F13/73, A63F13/75, H04L9/40
CPC Code(s): A63F13/73
Abstract: in examples, properties of an execution environment may be verified for a game session to comply with security policies based at least on analyzing attestation reports generated using one or more host devices. content items may be associated with the game session to indicate the verification for presentation with a live stream video of the game session, in a pre-recorded video of the game session, and/or in another user interface associated with the game session. a record of the verification may be stored in a database, and the database may be queried to display the content item and/or to determine whether the verification occurred. the attestation reports may include an attestation report(s) generated using an input device(s) used to capture user inputs for the game session, such as an input device used to control the game session and/or provide a video capture of the player during the game session.
Inventor(s): Jesus Ramos of San Jose CA (US) for nvidia corporation, Jiri Johannes Kraus of Bonn (DE) for nvidia corporation, Sebastian Jodlowski of San Jose CA (US) for nvidia corporation, Fnu Vishnuswaroop Ramesh of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/3004
Abstract: apparatuses, systems, and techniques to execute software programs. in at least one embodiment, an application programming interface (api) is performed to cause an indication to be stored of whether one or more memory operations to be performed are dependent on one or more other memory operations.
Inventor(s): Piotr Tomasz Ciolkosz of Stalowa Wola (PL) for nvidia corporation, Kyrylo Perelygin of Broomfield CO (US) for nvidia corporation, Harold Carter Edwards of Campbell CA (US) for nvidia corporation, Gonzalo Brito Gadeschi of Munich (DE) for nvidia corporation, Georgii Evtushenko of Yerevan (AM) for nvidia corporation, Jake Hemstad of Bloomington MN (US) for nvidia corporation, Vishalkumar Ketankumar Mehta of Stäfa (CH) for nvidia corporation, Michal Dominiak of Santa Clara CA (US) for nvidia corporation, Olivier Giroux of Santa Clara CA (US) for nvidia corporation, Konstantinos Kyriakopoulos of Weinsberg (DE) for nvidia corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/3009
Abstract: apparatuses, systems, and techniques to perform an application programming interface (api) to select a single thread from a group of threads to perform a set of instructions. in at least one embodiment, processors or computer systems are to perform an api to indicate instructions to be performed by a single thread and to select that thread from a group of threads to perform said instructions.
Inventor(s): Apoorv PARLE of Santa Clara CA (US) for nvidia corporation, Ronny KRASHINSKY of Santa Clara CA (US) for nvidia corporation, John EDMONDSON of Santa Clara CA (US) for nvidia corporation, Jack CHOQUETTE of Santa Clara CA (US) for nvidia corporation, Shirish GADRE of Santa Clara CA (US) for nvidia corporation, Steve HEINRICH of Santa Clara CA (US) for nvidia corporation, Manan PATEL of Santa Clara CA (US) for nvidia corporation, Prakash Bangalore PRABHAKAR, JR. of Santa Clara CA (US) for nvidia corporation, Ravi MANYAM of Santa Clara CA (US) for nvidia corporation, Wish GANDHI of Santa Clara CA (US) for nvidia corporation, Lacky SHAH of Santa Clara CA (US) for nvidia corporation, Alexander L. Minkin of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06F9/38, G06F9/52, G06F13/16, G06F13/40, G06T1/20, G06T1/60, H04L49/101
CPC Code(s): G06F9/3887
Abstract: this specification describes a programmatic multicast technique enabling one thread (for example, in a cooperative group array (cga) on a gpu) to request data on behalf of one or more other threads (for example, executing on respective processor cores of the gpu). the multicast is supported by tracking circuitry that interfaces between multicast requests received from processor cores and the available memory. the multicast is designed to reduce cache (for example, layer 2 cache) bandwidth utilization enabling strong scaling and smaller tile sizes.
Inventor(s): Jesus Ramos of San Jose CA (US) for nvidia corporation, Jiri Johannes Kraus of Bonn (DE) for nvidia corporation, Sebastian Jodlowski of San Jose CA (US) for nvidia corporation, Fnu Vishnuswaroop Ramesh of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/52
Abstract: apparatuses, systems, and techniques to execute software programs. in at least one embodiment, an application programming interface (api) is performed to cause context information to be updated to indicate whether one or more memory operations to be performed are dependent on one or more other memory operations.
Inventor(s): Piotr Tomasz Ciolkosz of Stalowa Wola (PL) for nvidia corporation, Kyrylo Perelygin of Broomfield CO (US) for nvidia corporation, Harold Carter Edwards of Campbell CA (US) for nvidia corporation, Gonzalo Brito Gadeschi of Munich (DE) for nvidia corporation, Georgii Evtushenko of Yerevan (AM) for nvidia corporation, Jake Hemstad of Bloomington MN (US) for nvidia corporation, Vishalkumar Ketankumar Mehta of Stäfa (CH) for nvidia corporation, Michal Dominiak of Santa Clara CA (US) for nvidia corporation, Olivier Giroux of Santa Clara CA (US) for nvidia corporation, Konstantinos Kyriakopoulos of Weinsberg (DE) for nvidia corporation
IPC Code(s): G06F9/54, G06F9/38
CPC Code(s): G06F9/541
Abstract: apparatuses, systems, and techniques to perform an application programming interface (api) to select a single thread from a group of threads to perform a set of instructions and to broadcast a result of performance of said set of instructions to said group of threads. in at least one embodiment, processors or computer systems are to perform an api to indicate instructions to be performed by a single thread and to select that thread from a group of threads to perform said instructions, and to make available to said group of threads data generated as a result of performance of said instructions.
Inventor(s): David Anthony Fontaine of Mountain View CA (US) for nvidia corporation, Steven Arthur Gurfinkel of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F9/54, G06F9/52
CPC Code(s): G06F9/542
Abstract: apparatuses, systems, and techniques to perform an application programming interface (api) to add one or more graph nodes to a software graph, wherein the api is to store an indication of whether a node within a software graph was performed based, at least in part, on a dependency type indicated by the api. in at least one embodiment, one or more nodes are added to a graph in accordance to one or more dependency types.
Inventor(s): Jesus Ramos of San Jose CA (US) for nvidia corporation, Jiri Johannes Kraus of Bonn (DE) for nvidia corporation, Sebastian Jodlowski of San Jose CA (US) for nvidia corporation, Fnu Vishnuswaroop Ramesh of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F9/30, G06F9/54
CPC Code(s): G06F9/544
Abstract: apparatuses, systems, and techniques to execute software programs. in at least one embodiment, an application programming interface (api) is performed to cause an indication to be read of whether one or more memory operations to be performed are dependent on one or more other memory operations.
20240289239. ONLINE FAULT DETECTION IN RERAM-BASED AI/ML_simplified_abstract_(nvidia corporation)
Inventor(s): Krishnendu Chakrabarty of Chapel Hill NC (US) for nvidia corporation, Mengyun Liu of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06F11/16, G06F11/14, G06F11/30, G06N3/063, G06N20/10
CPC Code(s): G06F11/165
Abstract: the disclosure describes a method of monitoring the dynamic power consumption of reram crossbars and determines the occurrence of faults when a changepoint is detected in the monitored power-consumption time series. statistical features are computed before and after the changepoint and train a predictive model using machine-learning techniques. in this way, the computationally expensive fault localization and error-recovery steps are carried out only when a high fault rate is estimated. with the proposed fault-detection method and the predictive model, the test time is significantly reduced while high classification accuracy for well-known ai/ml datasets using a reram-based computing system (rcs) can still be ensured.
Inventor(s): Jesus Ramos of San Jose CA (US) for nvidia corporation, Jiri Johannes Kraus of Bonn (DE) for nvidia corporation, Sebastian Jodlowski of San Jose CA (US) for nvidia corporation, Fnu Vishnuswaroop Ramesh of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F12/02, G06F9/54
CPC Code(s): G06F12/0223
Abstract: apparatuses, systems, and techniques to execute software programs. in at least one embodiment, an application programming interface (api) is performed to cause an indication to be read from a primary context data structure of whether one or more memory operations to be performed are dependent on one or more other memory operations.
Inventor(s): Igor Mitsyanko of San Carlos CA (US) for nvidia corporation, Aki Petteri Niemi of Vancouver (CA) for nvidia corporation, Junghyun Kim of Dublin CA (US) for nvidia corporation
IPC Code(s): G06F13/42, G06F13/16
CPC Code(s): G06F13/4282
Abstract: a controller device includes a memory storing instructions. an interface bus is coupled to sensors and configured to operate with a multi-target interface protocol. a processor is coupled to the memory and the interface bus. the processor broadcasts initialization data, according to the multi-target interface protocol, to the sensors. the processor generates, from the initialization data, using at least one cryptographic function, an authentication tag for each sensor. each authentication tag is specific to a corresponding sensor of the sensors. the processor also unicasts, according to the multi-target interface protocol, each authentication tag to the corresponding sensor of the sensors.
Inventor(s): Jesus Ramos of San Jose CA (US) for nvidia corporation, Jiri Johannes Kraus of Bonn (DE) for nvidia corporation, Sebastian Jodlowski of San Jose CA (US) for nvidia corporation, Fnu Vishnuswaroop Ramesh of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F16/23, G06F9/54
CPC Code(s): G06F16/2379
Abstract: apparatuses, systems, and techniques to execute software programs. in at least one embodiment, an application programming interface (api) is performed to cause an indication to be stored within a primary context data structure of whether one or more memory operations to be performed are dependent on one or more other memory operations.
Inventor(s): Kangxue Yin of Toronto (CA) for nvidia corporation, Huan Ling of Toronto (CA) for nvidia corporation, Masha Shugrina of Toronto (CA) for nvidia corporation, Sameh Khamis of Alameda CA (US) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation
IPC Code(s): G06T19/20, G06N3/0475, G06N3/08, G06T15/04, G06T15/10
CPC Code(s): G06T19/20
Abstract: generation of three-dimensional (3d) object models may be challenging for users without a sufficient skill set for content creation and may also be resource intensive. one or more style transfer networks may be combined with a generative network to generate objects based on parameters associated with a textual input. an input including a 3d mesh and texture may be provided to a trained system along with a textual input that includes parameters for object generation. features of the input object may be identified and then tuned in accordance with the textual input to generate a modified 3d object that includes a new texture along with one or more geometric adjustments.
Inventor(s): Martin HEMPEL of Mountain View CA (US) for nvidia corporation, Nishant PURI of San Francisco CA (US) for nvidia corporation, Anshul JAIN of San Jose CA (US) for nvidia corporation, Chun-Wei CHEN of San Jose CA (US) for nvidia corporation, Dae Jin KIM of San Jose CA (US) for nvidia corporation, Frederic VATNSDAL of San Jose CA (US) for nvidia corporation
IPC Code(s): G06V20/59, B60W40/08, G06F3/01
CPC Code(s): G06V20/597
Abstract: in various examples, systems and method are provided for generation of ground truth gaze data for training in-cabin monitoring systems and applications. a gaze target projector mounted to a known position inside a cabin may be used to project a gaze target onto an interior surface of the cabin. because a beam of light may be used to produce the projected gaze target, the projected gaze target may be displayed at a projection point on the surface of the cabin interior, even if the surface at the projection point is curved, small, or an irregular shape. three-dimensional coordinates of a projected gaze target in the cabin coordinate system may be determined and used to label image data that is captured as a projected gaze target is selectively projected onto an interior surface of the cabin and a test occupant's gaze is directed at the projected gaze target.
- NVIDIA Corporation
- A63F13/73
- A63F13/75
- H04L9/40
- CPC A63F13/73
- Nvidia corporation
- G06F9/30
- G06F9/38
- CPC G06F9/3004
- CPC G06F9/3009
- G06F9/52
- G06F13/16
- G06F13/40
- G06T1/20
- G06T1/60
- H04L49/101
- CPC G06F9/3887
- CPC G06F9/52
- G06F9/54
- CPC G06F9/541
- CPC G06F9/542
- CPC G06F9/544
- G06F11/16
- G06F11/14
- G06F11/30
- G06N3/063
- G06N20/10
- CPC G06F11/165
- G06F12/02
- CPC G06F12/0223
- G06F13/42
- CPC G06F13/4282
- G06F16/23
- CPC G06F16/2379
- G06T19/20
- G06N3/0475
- G06N3/08
- G06T15/04
- G06T15/10
- CPC G06T19/20
- G06V20/59
- B60W40/08
- G06F3/01
- CPC G06V20/597
