NVIDIA Corporation patent applications on August 22nd, 2024
Patent Applications by NVIDIA Corporation on August 22nd, 2024
NVIDIA Corporation: 8 patent applications
NVIDIA Corporation has applied for patents in the areas of G06V10/82 (2), G01C21/36 (1), G06V10/774 (1), H01M8/04119 (1), H01M8/04089 (1) G01C21/3644 (1), G01R31/2808 (1), G06F9/5083 (1), G06F21/44 (1), G06T7/50 (1)
With keywords such as: object, regressed, data, probe, generate, used, device, processing, systems, and tile in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Joshua Edward ABBOTT of Draper UT (US) for nvidia corporation, Amir AKBARZADEH of San Jose CA (US) for nvidia corporation, Joachim PEHSERL of Lynnwood WA (US) for nvidia corporation, Samuel OGDEN of Duvall WA (US) for nvidia corporation, David WEHR of Redmond WA (US) for nvidia corporation, Ke CHEN of Cupertino CA (US) for nvidia corporation
IPC Code(s): G01C21/36, B60W60/00, G06V10/82
CPC Code(s): G01C21/3644
Abstract: in various examples, one or more dnns may be used to detect landmarks (e.g., lane lines) and regress a representation of their shape. a dnn may be used to jointly generate classifications of measured 3d points using one output head (e.g., a classification head) and regress a representation of one or more fitted shapes (e.g., polylines, circles) using a second output head (e.g., a regression head). in some embodiments, multiple dnns (e.g., a chain of multiple dnns or multiple stages of a dnn) are used to sequentially generate classifications of measured 3d points and a regressed representation of the shape of one or more detected landmarks. as such, classified landmarks and corresponding fitted shapes may be decoded and used for localization, navigation, and/or other uses.
20240280629. AUTOMATIC BOARD PROBING STATION_simplified_abstract_(nvidia corporation)
Inventor(s): Akhilesh Sandeep Thakur of Portland OR (US) for nvidia corporation, Ryan Kelsey Albright of Beaverton OR (US) for nvidia corporation, Frans Johannes Fourie of Portland OR (US) for nvidia corporation, Jorian Matias Bruslind of Beaverton OR (US) for nvidia corporation, Kevin Matthew Hoser of Portland OR (US) for nvidia corporation, Zachary Jacob Watkins of Hillsboro OR (US) for nvidia corporation, Audrey Grace Cummings of Hillsboro OR (US) for nvidia corporation, Jose Eduardo Barcenas of Portland OR (US) for nvidia corporation, Daniel Garanton of Hillsboro OR (US) for nvidia corporation, Grant Michael Skidmore of Portland OR (US) for nvidia corporation
IPC Code(s): G01R31/28, G01R1/073, G01R35/00
CPC Code(s): G01R31/2808
Abstract: systems and methods herein are for an automatic board probing station in which a plurality of probe tips are associated with a plurality of probe arms and with a plurality of motorized connectors, where the plurality of motorized connectors is to cause individual ones of the plurality of probe tips and individual ones of the plurality of probe arms to be movable independently, and where the plurality of probe tips is to communicate probe signals with a circuit analysis system and is to concurrently probe a plurality of probe points of a circuit board.
Inventor(s): Donghyuk Lee of Cedar Park TX (US) for nvidia corporation, Leul Wuletaw Belayneh of Dallas TX (US) for nvidia corporation, Niladrish Chatterjee of Kirkland WA (US) for nvidia corporation, James Michael O'Connor of Austin TX (US) for nvidia corporation
IPC Code(s): G06F9/50, G06F9/54
CPC Code(s): G06F9/5083
Abstract: an initiating processing tile generates an offload request that may include a processing tile id, source data needed for the computation, program counter, and destination location where the computation result is stored. the offload processing tile may execute the offloaded computation. alternatively, the offload processing tile may deny the offload request based on congestion criteria. the congestion criteria may include a processing workload measure, whether a resource needed to perform the computation is available, and an offload request buffer fullness. in an embodiment, the denial message that is returned to the initiating processing tile may include the data needed to perform the computation (read from the local memory of the offload processing tile). returning the data with the denial message results in the same inter-processing tile traffic that would occur if no attempt to offload the computation were initiated.
Inventor(s): Christopher Anthony Grant HILLIER of Fort Collins CO (US) for nvidia corporation, Raghupathy KRISHNAMURTHY of San Jose CA (US) for nvidia corporation, Varun SAMPATH of Santa Clara CA (US) for nvidia corporation, Mayur Vivek GUDMETI of Durham NC (US) for nvidia corporation
IPC Code(s): G06F21/44, H04L9/30
CPC Code(s): G06F21/44
Abstract: systems and methods are described herein for implementing a mutable device ownership transfer (dot) of a device. an example system receives a request from a first customer to record a mutable dot of a device using a first customer authentication key (fcak); receives the fcak from the first customer in response to receiving the request; determines whether the device is capable of recording the mutable dot; and installs, using a dot circuitry, the fcak in a non-volatile memory of a root of trust (rot) associated with the device in an instance in which the device is capable of recording the mutable dot. installing the fcak in the non-volatile memory of the root of trust (rot) results in no permanent modification to the device.
Inventor(s): Joshua Edward ABBOTT of Draper UT (US) for nvidia corporation, Amir AKBARZADEH of San Jose CA (US) for nvidia corporation, Joachim PEHSERL of Lynnwood WA (US) for nvidia corporation, Samuel Ogden of Duvall WA (US) for nvidia corporation, David WEHR of Redmond WA (US) for nvidia corporation, Ke CHEN of Cupertino CA (US) for nvidia corporation
IPC Code(s): G06T7/50, G01S17/89
CPC Code(s): G06T7/50
Abstract: in various examples, perception of landmark shapes may be used for localization in autonomous systems and applications. in some embodiments, a deep neural network (dnn) is used to generate (e.g., per-point) classifications of measured 3d points (e.g., classified lidar points), and a representation of the shape of one or more detected landmarks is regressed from the classifications. for each of one or more classes, the classification data may be thresholded to generate a binary mask and/or dilated to generate a densified representation, and the resulting (e.g., dilated, binary) mask may be clustered into connected components that are iteratively: fitted a shape (e.g., a polynomial or bezier spline for lane lines, a circle for top-down representations of poles or traffic lights), weighted, and merged. as such, the resulting connected components and their fitted shapes may be used to represent detected landmarks and used for localization, navigation, and/or other uses.
Inventor(s): Yang ZHENG of Thousand Oak CA (US) for nvidia corporation, Trung Pham of Santa Clara CA (US) for nvidia corporation, Minwoo Park of Saratoga CA (US) for nvidia corporation
IPC Code(s): G06V20/58, G06V10/764, G06V10/774, G06V10/82, G06V20/56
CPC Code(s): G06V20/58
Abstract: in various examples, one or more object detectors may regress bounding polygons for detected objects in systems (e.g., autonomous or semi-autonomous driving systems and applications) that provide object awareness, object identification, object avoidance, and/or object localization. the object detector may determine regression data representing a regressed polygon associated with a given shape of a detected object represented by classification data determined from a scene. the object detector may determine regression data for different regressed angles between different pairs of successive vertices of the regressed polygon and regressed lengths of vectors from a regressed geometric center of the regressed polygon to vertices of the regressed polygon. the object detector may generate, based at least in part on the regression data, a bounding shape for a detected object in the scene. in some embodiments, the object detector may be trained by deforming a regressed polygon to match a ground truth polygon.
Inventor(s): Samuel Hung of Santa Clara CA (US) for nvidia corporation, Animesh Khemka of Fremont CA (US) for nvidia corporation
IPC Code(s): H04N23/11, G06V10/143, G06V10/25, H04N23/73
CPC Code(s): H04N23/11
Abstract: disclosed are apparatuses, systems, and techniques that implement runtime configuration of sensors that combine visible light sensing elements with infrared sensing elements and deploy pulsed illumination sources in real-time data generating and streaming applications. in one disclosed embodiment, a sensing system includes a plurality of infrared (ir) sensing elements to generate an ir portion of an image and a plurality of visible light (vl) sensing elements to generate one or more vl portions of the image. a processing device identifies a source parameter characterizing a photon count associated with the ir portion of the image relative to the photon count associated with the one or more vl portions of the image, and determines, using the source parameter, one or more settings of the sensing system.
20240284640. ENERGY EFFICIENT LIQUID-COOLED DATACENTERS_simplified_abstract_(nvidia corporation)
Inventor(s): Ali Heydari of Napa CA (US) for nvidia corporation
IPC Code(s): H05K7/20, G06F1/26, H01M8/04007, H01M8/04089, H01M8/04119, H05K7/14
CPC Code(s): H05K7/208
Abstract: systems and methods for operating a datacenter are disclosed. in at least one embodiment, method for operating a datacenter includes receiving a source of gas to a fuel cell to produce electrical power. the method further includes providing the electrical power to one or more electronic components in the datacenter. the method further includes capturing waste heat, generated by the fuel cell in converting the gas to the electrical power, using a heat exchanger. the method further includes providing the waste heat to an absorption chiller to produce cooled liquid to be utilized with a cooling system to remove heat from the one or more electronic components.
- NVIDIA Corporation
- G01C21/36
- B60W60/00
- G06V10/82
- CPC G01C21/3644
- Nvidia corporation
- G01R31/28
- G01R1/073
- G01R35/00
- CPC G01R31/2808
- G06F9/50
- G06F9/54
- CPC G06F9/5083
- G06F21/44
- H04L9/30
- CPC G06F21/44
- G06T7/50
- G01S17/89
- CPC G06T7/50
- G06V20/58
- G06V10/764
- G06V10/774
- G06V20/56
- CPC G06V20/58
- H04N23/11
- G06V10/143
- G06V10/25
- H04N23/73
- CPC H04N23/11
- H05K7/20
- G06F1/26
- H01M8/04007
- H01M8/04089
- H01M8/04119
- H05K7/14
- CPC H05K7/208