NVIDIA Corporation patent applications on August 1st, 2024
Patent Applications by NVIDIA Corporation on August 1st, 2024
NVIDIA Corporation: 16 patent applications
NVIDIA Corporation has applied for patents in the areas of H05K7/20 (3), G06V20/56 (2), G06T15/50 (2), G06T5/70 (2), G06T15/06 (2) G06T15/06 (2), B25J9/163 (1), G01C21/3848 (1), G01R19/1659 (1), G06F1/26 (1)
With keywords such as: data, voltage, power, systems, image, surface, within, determine, locations, and center in patent application abstracts.
Patent Applications by NVIDIA Corporation
20240253217. LOSS-GUIDED DIFFUSION MODELS_simplified_abstract_(nvidia corporation)
Inventor(s): Arash Vahdat of Mountain View CA (US) for nvidia corporation, Hongxu Yin of San Jose CA (US) for nvidia corporation, Jan Kautz of Lexington MA (US) for nvidia corporation, Jiaming Song of San Carlos CA (US) for nvidia corporation, Ming-Yu Liu of San Jose CA (US) for nvidia corporation, Morteza Mardani of Santa Clara CA (US) for nvidia corporation, Qinsheng Zhang of Atlanta GA (US) for nvidia corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/163
Abstract: apparatuses, systems, and techniques to calculate a combined loss value based on applying one or more loss functions to the plurality of samples generated by a diffusion model to update the samples to determine a synthesized motions of one or more objects.
Inventor(s): Yixuan Lin of San Jose CA (US) for nvidia corporation
IPC Code(s): G01C21/00, G06T7/70, G06V20/56
CPC Code(s): G01C21/3848
Abstract: in various examples, intersections may be identified using sensor data for mapping in autonomous or semi-autonomous systems and applications. systems and methods are disclosed that receive sensor data, such as image data, generated using one or more sensor of one or more vehicles navigating within an environment. the systems and methods may then use the sensor data to determine the locations and/or layouts of intersections within the environment and update a map to indicate the locations and/or layouts. for instance, the sensor data may be analyzed to detect the locations of the intersections, such as the locations of the boundaries of the intersections for which the vehicles navigated through. the map may then be updated to indicate the locations of the intersections by indicating the locations of the boundaries within the map, such as by using bounding shapes that are generated based on the locations of the boundaries.
20240255551. OVERVOLTAGE AND UNDERVOLTAGE DETECTOR_simplified_abstract_(nvidia corporation)
Inventor(s): Abhishek Akkur of Santa Clara CA (US) for nvidia corporation, Tezaswi Raja of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G01R19/165, G01R19/17, H02H3/20
CPC Code(s): G01R19/1659
Abstract: the disclosure provides a voltage detecting circuit that detects voltage increases and voltage decreases using a diode drop and voltage thresholds. the voltage detecting circuit, referred to as a voltage variation detector, uses the diode to maintain a differential between the voltage being monitored and a voltage threshold. when the diode is reversed bias, the voltage variation detector generates a detecting signal indicating the monitored voltage crossed the voltage threshold. in one example a voltage variation detector is disclosed that includes: (1) a transistor stack that corresponds to a voltage threshold, (2) a transistor diode, and (3) an inverter that receives an input signal and provides an detection signal that controls one or more gates of the transistor stack, wherein the transistor stack and the transistor diode provide the input signal and the detection signal indicates when the voltage crosses the voltage threshold.
20240256023. INTELLIGENT DATA CENTER_simplified_abstract_(nvidia corporation)
Inventor(s): Alex R. Naderi of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06F1/26, G06F1/20, G06F1/30, H05K7/20
CPC Code(s): G06F1/26
Abstract: provided, in one aspect, is a data center. the data center, in this aspect, includes a data center enclosure, the data center enclosure designed for a given supply of power (p). the data center, according to this aspect, further includes n independent coolable clusters of data center racks located within the data center enclosure, wherein n is at least two, and further wherein the n independent coolable clusters each have an ostensible power demand (p) approximately equal to p/n, and each of the n independent coolable clusters has a respective actual power demand (p) adjustable at, above or below the ostensible power demand (p).
20240256153. MEMORY PAGE ACCESS INSTRUMENTATION_simplified_abstract_(nvidia corporation)
Inventor(s): Niladrish Chatterjee of Kirkland WA (US) for nvidia corporation, Zachary Joseph Susskind of Austin TX (US) for nvidia corporation, Donghyuk Lee of Cedar Park TX (US) for nvidia corporation, James Michael O'Connor of Austin TX (US) for nvidia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: embodiments of the present disclosure relate to memory page access instrumentation for generating a memory access profile. the memory access profile may be used to co-locate data near the processing unit that accesses the data, reducing memory access energy by minimizing distances to access data that is co-located with a different processing unit (i.e., remote data). execution thread arrays and memory pages for execution of a program are partitioned across multiple processing units. the partitions are then each mapped to a specific processing unit to minimize inter-partition traffic given the processing unit physical topology.
Inventor(s): Piotr Majcher of Sunnyvale CA (US) for nvidia corporation, Mostafa Hagog of Folsom CA (US) for nvidia corporation, Philippe Vandermersch of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F17/16, G06F9/30, G06N3/08, G06N5/046
CPC Code(s): G06F17/16
Abstract: apparatuses, systems, and techniques to determine a matrix multiplication algorithm for a matrix multiplication operation. in at least one embodiment, a matrix multiplication operation is analyzed to determine an appropriate matrix multiplication algorithm to perform the matrix multiplication algorithm.
Inventor(s): Shaurakar Das of San Jose CA (US) for nvidia corporation, Haoxing Ren of Austin TX (US) for nvidia corporation, Santosh Santosh of Los Gatos CA (US) for nvidia corporation, SeshasaiJyothi Kolli of San Jose CA (US) for nvidia corporation, Muhammad Arif Mirza of Austin TX (US) for nvidia corporation, Sreedhar Pratty of Campbell CA (US) for nvidia corporation
IPC Code(s): G06F30/392, G06F30/398, H01L27/02
CPC Code(s): G06F30/392
Abstract: to ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. ir drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. before fabrication, placement of the cells is reorganized within bounding box regions. power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. the reorganization is ir aware and has minimal impact on timing and ir drop is mitigated because distributing current consumption between the supply rails reduces current spikes and ir drops.
Inventor(s): Daiqing Li of Oakville (CA) for nvidia corporation, Huan Ling of Toronto (CA) for nvidia corporation, Seung Wook Kim of Toronto (CA) for nvidia corporation, Karsten Julian Kreis of Vancouver (CA) for nvidia corporation, Antonio Torralba Barriuso of Somerville MA (US) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation, Amlan Kar of Toronto (CA) for nvidia corporation
IPC Code(s): G06N3/045, G06T5/00, G06V10/774, G06V10/82
CPC Code(s): G06N3/045
Abstract: in various examples, systems and methods are disclosed relating to generating a response from image and/or video input for image/video-based artificial intelligence (ai) systems and applications. systems and methods are disclosed for a first model (e.g., a teacher model) distilling its knowledge to a second model (a student model). the second model receives a downstream image in a downstream task and generates at least one feature. the first model generates first features corresponding to an image which can be a real image or a synthetic image. the second model generates second features using the image as an input to the second model. loss with respect to first features is determined. the second model is updated using the loss.
Inventor(s): Karthik Vaidyanathan of Oakland CA (US) for nvidia corporation, Marco Salvi of Seattle WA (US) for nvidia corporation, Bartlomiej Wronski of Brooklyn NY (US) for nvidia corporation, Tomas Akenine-Moller of Lund (SE) for nvidia corporation, Johan Pontus Ebelin of LUND (SE) for nvidia corporation, Aaron Eliot Lefohn of Kirkland WA (US) for nvidia corporation, John Matthew Burgess of Austin TX (US) for nvidia corporation, Steven James Heinrich of Madison AL (US) for nvidia corporation, Michael Alan Fetterman of Lancaster MA (US) for nvidia corporation, Shirish Gadre of Fremont CA (US) for nvidia corporation, Mark Alan Gebhart of Round Rock TX (US) for nvidia corporation
IPC Code(s): G06T9/00
CPC Code(s): G06T9/002
Abstract: in computer graphics, texture refers to a type of surface, including the material characteristics, that can be applied to an object in an image. a texture may be defined using numerous parameters, such as color(s), roughness, glossiness, etc. in some implementations, a texture may be represented as an image that can be placed on a three-dimensional (3d) model of an object to give surface details to the 3d object. to reduce a size of textures (e.g. for storage and transmission), the present disclosure provides, in one embodiment, for compression of a texture set using a non-linear function and quantization. in another embodiment, the disclosure provides for compression of one or more textures using a non-linear function configured to compress textures with an arbitrary number of channels and/or an arbitrary ordering of channels.
20240257437. REAL-TIME NEURAL APPEARANCE MODELS_simplified_abstract_(nvidia corporation)
Inventor(s): Karthik Vaidyanathan of Oakland CA (US) for nvidia corporation, Alex John Bauld Evans of London (GB) for nvidia corporation, Jan Novák of Dobrichovice (CZ) for nvidia corporation, Andrea Weidlich of Montreal (CA) for nvidia corporation, Fabrice Pierre Armand Rousselle of Ostermundigen (CH) for nvidia corporation, Aaron Eliot Lefohn of Kirkland WA (US) for nvidia corporation, Franz Petrik Clarberg of Lund (SE) for nvidia corporation, Benedikt Bitterli of Kirkland WA (US) for nvidia corporation, Tizian Lucien Zeltner of Zürich (CH) for nvidia corporation
IPC Code(s): G06T15/06, G06T7/33, G06T7/40, G06T15/50
CPC Code(s): G06T15/06
Abstract: embodiments of the present disclosure relate to real-time neural appearance models. using a neural decoder, scenes are rendered in real-time with complex material appearance previously reserved for offline use. learned hierarchical textures representing the material properties are encoded as latent codes. when a ray is cast and intersects with geometry in the scene, the intersection point is mapped to one of the latent codes. the latent code is interpreted using neural decoders, which produce reflectance values and importance-sampled directions that can be used to determine a pixel color.
Inventor(s): Shiqiu Liu of Santa Clara CA (US) for nvidia corporation, Christopher Ryan Wyman of Redmond WA (US) for nvidia corporation, Jon Hasselgren of Bunkeflostrand (SE) for nvidia corporation, Jacob Munkberg of Skane (SE) for nvidia corporation, Ignacio Llamas of Palo Alto CA (US) for nvidia corporation
IPC Code(s): G06T15/06, G06T5/20, G06T5/70, G06T15/50, G06T15/60
CPC Code(s): G06T15/06
Abstract: disclosed approaches may leverage the actual spatial and reflective properties of a virtual environment—such as the size, shape, and orientation of a bidirectional reflectance distribution function (brdf) lobe of a light path and its position relative to a reflection surface, a virtual screen, and a virtual camera—to produce, for a pixel, an anisotropic kernel filter having dimensions and weights that accurately reflect the spatial characteristics of the virtual environment as well as the reflective properties of the surface. in order to accomplish this, geometry may be computed that corresponds to a projection of a reflection of the brdf lobe below the surface along a view vector to the pixel. using this approach, the dimensions of the anisotropic filter kernel may correspond to the brdf lobe to accurately reflect the spatial characteristics of the virtual environment as well as the reflective properties of the surface.
20240257443. SCENE RECONSTRUCTION FROM MONOCULAR VIDEO_simplified_abstract_(nvidia corporation)
Inventor(s): Christopher B. Choy of Los Angeles CA (US) for nvidia corporation, Or Litany of Sunnyvale CA (US) for nvidia corporation, Charles Loop of Redmond WA (US) for nvidia corporation, Yuke Zhu of Austin TX (US) for nvidia corporation, Animashree Anandkumar of Pasadena CA (US) for nvidia corporation, Wei Dong of Pittsburgh PA (US) for nvidia corporation
IPC Code(s): G06T15/20, G06T1/20, G06T5/50, G06T5/70, G06T7/579, G06T7/90, G06T19/20
CPC Code(s): G06T15/20
Abstract: a technique for reconstructing a three-dimensional scene from monocular video adaptively allocates an explicit sparse-dense voxel grid with dense voxel blocks around surfaces in the scene and sparse voxel blocks further from the surfaces. in contrast to conventional systems, the two-level voxel grid can be efficiently queried and sampled. in an embodiment, the scene surface geometry is represented as a signed distance field (sdf). representation of the scene surface geometry can be extended to multi-modal data such as semantic labels and color. because properties stored in the sparse-dense voxel grid structure are differentiable, the scene surface geometry can be optimized via differentiable volume rendering.
20240257460. NEURAL NETWORKS TO GENERATE PIXELS_simplified_abstract_(nvidia corporation)
Inventor(s): Chen-Hsuan Lin of Santa Clara CA (US) for nvidia corporation, Zhaoshuo Li of Baltimore MD (US) for nvidia corporation, Thomas Müller-Höhne of Baar (CH) for nvidia corporation, Alex John Bauld Evans of London (GB) for nvidia corporation, Ming-Yu Liu of San Jose CA (US) for nvidia corporation, Alexander Georg Keller of Berlin (DE) for nvidia corporation
IPC Code(s): G06T17/10
CPC Code(s): G06T17/10
Abstract: apparatuses, systems, and techniques to generate pixels based on other pixels. in at least one embodiment, one or more neural networks are used to generate one or more pixels based, at least in part, on sets of pixels surrounding the one or more pixels.
Inventor(s): Nuri Murat Arar of Zurich (CH) for nvidia corporation, Niranjan Avadhanam of Saratoga CA (US) for nvidia corporation, Yuzhuo Ren of San Jose CA (US) for nvidia corporation
IPC Code(s): G06V20/59, B60W30/09, B60W30/095, B60W40/08, B60W50/14, B60W60/00, G06V20/56
CPC Code(s): G06V20/597
Abstract: in various examples, estimated field of view or gaze information of a user may be projected external to a vehicle and compared to vehicle perception information corresponding to an environment outside of the vehicle. as a result, interior monitoring of a driver or occupant of the vehicle may be used to determine whether the driver or occupant has processed or seen certain object types, environmental conditions, or other information exterior to the vehicle. for a more holistic understanding of the state of the user, attentiveness and/or cognitive load of the user may be monitored to determine whether one or more actions should be taken. as a result, notifications, aeb system activations, and/or other actions may be determined based on a more complete state of the user as determined based on cognitive load, attentiveness, and/or a comparison between external perception of the vehicle and estimated perception of the user.
Inventor(s): Sien CHEN of Shenzhen (CN) for nvidia corporation, Xuan WANG of Shenzhen (CN) for nvidia corporation, Ziyi XU of Shenzhen (CN) for nvidia corporation
IPC Code(s): H05K1/14, H05K1/02, H05K7/20
CPC Code(s): H05K1/144
Abstract: according to various embodiments, a processing subsystem includes a first printed circuit board (pcb); a processor mounted directly on a first side of the first pcb; and one or more power components. the one or more power components are coupled to a second side of the first pcb and electrically coupled to the processor, where the first side of the first pcb is opposite to the second side of the first pcb.
Inventor(s): Ali Heydari of Albany CA (US) for nvidia corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20836
Abstract: systems and methods for cooling a datacenter are disclosed. in at least one embodiment, a modular unit is swappable or hot-swappable and has a heat exchanger, a variable speed fan, and at least one flow controller to pass fluid through microchannels of a cold plate, so that the fluid extracts heat from at least one computing device and so that fluid through a heat exchanger enables dissipation of heat by forced air from a variable speed fan.
- NVIDIA Corporation
- B25J9/16
- CPC B25J9/163
- Nvidia corporation
- G01C21/00
- G06T7/70
- G06V20/56
- CPC G01C21/3848
- G01R19/165
- G01R19/17
- H02H3/20
- CPC G01R19/1659
- G06F1/26
- G06F1/20
- G06F1/30
- H05K7/20
- CPC G06F1/26
- G06F3/06
- CPC G06F3/0625
- G06F17/16
- G06F9/30
- G06N3/08
- G06N5/046
- CPC G06F17/16
- G06F30/392
- G06F30/398
- H01L27/02
- CPC G06F30/392
- G06N3/045
- G06T5/00
- G06V10/774
- G06V10/82
- CPC G06N3/045
- G06T9/00
- CPC G06T9/002
- G06T15/06
- G06T7/33
- G06T7/40
- G06T15/50
- CPC G06T15/06
- G06T5/20
- G06T5/70
- G06T15/60
- G06T15/20
- G06T1/20
- G06T5/50
- G06T7/579
- G06T7/90
- G06T19/20
- CPC G06T15/20
- G06T17/10
- CPC G06T17/10
- G06V20/59
- B60W30/09
- B60W30/095
- B60W40/08
- B60W50/14
- B60W60/00
- CPC G06V20/597
- H05K1/14
- H05K1/02
- CPC H05K1/144
- CPC H05K7/20836
