NVIDIA Corporation patent applications on April 4th, 2024
Contents
- 1 Patent Applications by NVIDIA Corporation on April 4th, 2024
- 1.1 Overview of NVIDIA Corporation Patent Applications (April 4, 2024)
- 1.1.1 Key Areas of Innovation
- 1.1.2 Innovations in Neural Networks and AI
- 1.1.3 Questions about NVIDIA Corporation's Patent Applications
- 1.1.3.1 How do these innovations enhance NVIDIA's product offerings?
- 1.1.3.2 What are the potential impacts of these patents on the autonomous vehicle industry?
- 1.1.3.3 How do NVIDIA’s advancements in AI affect data privacy?
- 1.1.3.4 What commercial applications can arise from NVIDIA's patented technologies?
- 1.1.3.5 How does NVIDIA's focus on efficiency in neural network processing benefit the broader tech industry?
- 1.1.3.6 Patent Applications by NVIDIA Corporation
- 1.1 Overview of NVIDIA Corporation Patent Applications (April 4, 2024)
Patent Applications by NVIDIA Corporation on April 4th, 2024
Overview of NVIDIA Corporation Patent Applications (April 4, 2024)
On April 4, 2024, NVIDIA Corporation, a leader in graphics and artificial intelligence technologies, filed 18 patent applications. These applications span a variety of areas such as image processing, memory management, and autonomous machine technologies, underscoring NVIDIA's continued focus on advancing the state of computing and artificial intelligence.
Key Areas of Innovation
NVIDIA’s patent filings are categorized under several IPC codes, with significant contributions in the following areas:
- Autonomous Machines and Object Detection
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- Techniques like LIDAR-based object detection for autonomous vehicles, detailed under IPC codes G06V10/764, G06V10/80, and G06V10/82
- Leveraging multidimensional sensor data for computationally efficient object detection, involving IPC codes like G06N3/084 and G06V10/25
- Memory and Data Management
- Artificial Intelligence Enhancements
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- Developing generative machine learning models for privacy-preserving data synthesis using IPC codes G06F21/62 and G06N3/0455
- Accelerating neural network performance with logarithmic-based arithmetic, described by IPC codes G06N3/063, G06F7/483, and G06F17/16
Innovations in Neural Networks and AI
NVIDIA Corporation is particularly focused on enhancing the capabilities of neural networks and AI systems. Key innovations include:
- Neural Network Acceleration
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- Utilizing logarithmic arithmetic to improve the efficiency of neural networks, particularly in convolution operations which are fundamental to AI processing.
- Privacy-Preserving Synthetic Data Generation
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- Utilizing diffusion techniques in generative models to maintain privacy while training AI, which is crucial for adhering to privacy regulations and maintaining user trust.
Questions about NVIDIA Corporation's Patent Applications
Below are several questions that arise from this overview of NVIDIA Corporation’s recent patent filings:
How do these innovations enhance NVIDIA's product offerings?
These patents could lead to significant improvements in NVIDIA's core products, such as GPUs for gaming and professional visualization, as well as automotive and AI platforms.
What are the potential impacts of these patents on the autonomous vehicle industry?
NVIDIA’s patents related to LIDAR and sensor data processing for autonomous machines suggest potential advancements in autonomous vehicle technologies, which could lead to safer and more efficient autonomous driving systems.
How do NVIDIA’s advancements in AI affect data privacy?
The development of privacy-preserving generative models indicates NVIDIA's commitment to enhancing data privacy within AI systems, an essential factor as AI becomes more integrated into everyday applications.
What commercial applications can arise from NVIDIA's patented technologies?
Potential applications include improved gaming experiences through advanced image processing techniques, more efficient data centers through better memory management systems, and enhanced capabilities in AI-driven applications.
How does NVIDIA's focus on efficiency in neural network processing benefit the broader tech industry?
By improving the efficiency of neural network operations, NVIDIA not only enhances its own computing platforms but also sets a benchmark for the industry, potentially leading to broader adoption of these efficient techniques in various tech sectors.
NVIDIA Corporation: 18 patent applications
NVIDIA Corporation has applied for patents in the areas of G06V10/25 (8), G06V10/82 (6), H04N19/513 (4), G06V10/764 (4), G06V10/80 (4)
With keywords such as: data, frames, frame, device, systems, images, reference, based, array, and memory in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Tilman Wekel of Sunnyvale CA (US) for nvidia corporation, Sangmin Oh of san Jose CA (US) for nvidia corporation, David Nister of Bellevue WA (US) for nvidia corporation, Joachim Pehserl of Lynnwood WA (US) for nvidia corporation, Neda Cvijetic of East palo Alto CA (US) for nvidia corporation, Ibrahim Eden of Redmond WA (US) for nvidia corporation
IPC Code(s): G01S7/48, G01S7/481, G01S17/894, G01S17/931, G06V10/764, G06V10/80, G06V10/82, G06V20/58
Abstract: in various examples, a deep neural network (dnn) may be used to detect and classify animate objects and/or parts of an environment. the dnn may be trained using camera-to-lidar cross injection to generate reliable ground truth data for lidar range images. for example, annotations generated in the image domain may be propagated to the lidar domain to increase the accuracy of the ground truth data in the lidar domain—e.g., without requiring manual annotation in the lidar domain. once trained, the dnn may output instance segmentation masks, class segmentation masks, and/or bounding shape proposals corresponding to two-dimensional (2d) lidar range images, and the outputs may be fused together to project the outputs into three-dimensional (3d) lidar point clouds. this 2d and/or 3d information output by the dnn may be provided to an autonomous vehicle drive stack to enable safe planning and control of the autonomous vehicle.
Inventor(s): Gautam BHATIA of Mountain View CA (US) for nvidia corporation, Robert BLOEMER of Sterling MA (US) for nvidia corporation
IPC Code(s): G06F3/06
Abstract: various embodiments include a memory device that is capable of performing write training operations. prior approaches for write training involve storing a long data pattern into the memory followed by reading the long data pattern to determine whether the data was written to memory correctly. instead, the disclosed memory device stores a first data pattern (e.g., in a fifo memory within the memory device) or generates the first data pattern (e.g., using prbs) that is compared with a second data pattern being transmitted to the memory device by an external memory controller. if data patterns match, then the memory device stores a pass status in a register, otherwise a fail status is stored in the register. the memory controller reads the register to determine whether the write training passed or failed.
20240111532.LOCK-FREE UNORDERED IN-PLACE COMPACTION_simplified_abstract_(nvidia corporation)
Inventor(s): Pascal GAUTRON of Speracedes (FR) for nvidia corporation
IPC Code(s): G06F9/30
Abstract: various embodiments include techniques for lock-free, unordered in-place compaction of an array. the techniques include receiving a first array that includes a first plurality of data entries, generating a second array that includes a second plurality of data entries, and storing, in the second array, respective index positions of valid data entries included in the first array and invalid data entries included in the first array. the techniques further include determining invalid data entries included in a first portion of the first array based at least on the index positions, determining valid data entries included in a second portion of the first array based at least on the index positions, and replacing contents of the invalid data entries included in the first portion of the first array with contents of the valid data entries included in the second portion of the first array.
Inventor(s): Seema Kumar of Santa Clara CA (US) for nvidia corporation, Ish Chadha of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F13/42, G06F1/12
Abstract: a system includes a first device and a second device coupled to a link having one or more lanes. the first device is to transmit two or more frames to synchronize the one or more data lanes, where each frame comprises a quantity of bits. the second device is to receive a first set of bits from each data lane corresponding to the quantity of bits in each frame of the two or more frames. the second device is to determine that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of the two or more frames. the second device is further to synchronize each data lane of the one or more data lanes with respect to the frame boundary, responsive to determining that the first set of bits does not correspond to the frame boundary.
Inventor(s): Karsten Julian KREIS of Vancouver (CA) for nvidia corporation, Tim DOCKHORN of Waterloo (CA) for nvidia corporation, Tianshi CAO of Toronto (CA) for nvidia corporation, Arash VAHDAT of Mountain View CA (US) for nvidia corporation
IPC Code(s): G06F21/62, G06N3/0455
Abstract: in various examples, systems and methods are disclosed relating to differentially private generative machine learning models. systems and methods are disclosed for configuring generative models using privacy criteria, such as differential privacy criteria. the systems and methods can generate outputs representing content using machine learning models, such as diffusion models, that are determined in ways that satisfy differential privacy criteria. the machine learning models can be determined by diffusing the same training data to multiple noise levels.
Inventor(s): William James Dally of Incline Village CA (US) for nvidia corporation, Rangharajan Venkatesan of San Jose CA (US) for nvidia corporation, Brucek Kurdo Khailany of Austin TX (US) for nvidia corporation
IPC Code(s): G06N3/063, G06F7/483, G06F17/16
Abstract: neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. however, performing addition on logarithmic format values is more complex. conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. the sum may then be converted back into the logarithmic format.
Inventor(s): Hainan Xu of Baltimore MD (US) for nvidia corporation, Boris Ginsburg of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G06N3/08
Abstract: systems and methods provide for a machine learning system to train a machine learning model to output a multi-frame blank symbol when processing an auditory input. for example, as the system generates paths through a probability lattice, one or more paths include a multi-frame blank that skips at least one frame associated with the probability lattice. the inclusion of the multi-frame blank symbol may increase a total number of potential paths through the probability lattice, and may allow the machine learning model to more quickly and accurately process audio frames, while disregarding audio frames of less value. in deployment, when an output of the machine learning model indicates a multi-frame blank symbol or token, one or more frames of the auditory input may be omitted from processing.
Inventor(s): Innfarn Yoo of Fremont CA (US) for nvidia corporation, Rohit Taneja of Fremont CA (US) for nvidia corporation
IPC Code(s): G06N3/084, G06N3/045, G06N20/00, G06T7/30, G06T7/50, G06T7/521, G06T15/00, G06V10/25, G06V10/44, G06V10/764, G06V10/80, G06V10/82, G06V20/58, G06V20/64
Abstract: in various examples, a two-dimensional (2d) and three-dimensional (3d) deep neural network (dnn) is implemented to fuse 2d and 3d object detection results for classifying objects. for example, regions of interest (rois) and/or bounding shapes corresponding thereto may be determined using one or more region proposal networks (rpns)—such as an image-based rpn and/or a depth-based rpn. each roi may be extended into a frustum in 3d world-space, and a point cloud may be filtered to include only points from within the frustum. the remaining points may be voxelated to generate a volume in 3d world space, and the volume may be applied to a 3d dnn to generate one or more vectors. the one or more vectors, in addition to one or more additional vectors generated using a 2d dnn processing image data, may be applied to a classifier network to generate a classification for an object.
Inventor(s): Yogesh Dangi of Pune (IN) for nvidia corporation, Manas Ranjan Jagadev of San Jose CA (US) for nvidia corporation, Sandip Kumar of Pune (IN) for nvidia corporation, Kiran Sutar of Pune (IN) for nvidia corporation
IPC Code(s): G06N5/04, G06F1/3296, G06N5/02
Abstract: apparatuses, systems, and techniques to determine a number of idle cores of a computing device using a machine learning (ml) model based on a set of processes executed by the computing device are described. one method determines a set of processes executed by the computing device and determines, using an ml model, a number of cores of the computing device to be powered down based at least on the set of processes. the method updates a first mode of the number of cores to a second mode in which the number of cores consumes less power than in the first mode.
Inventor(s): Bojan Skaljak of San Jose CA (US) for nvidia corporation, Andrew Edelsten of Morgan Hill CA (US) for nvidia corporation
IPC Code(s): G06T1/20, G06F9/54, G06T1/60, H04N7/01
Abstract: apparatuses, systems, and techniques to generate computer graphics. in at least one embodiment, an application programming interface call to output an application-generated frame of computer graphics is intercepted. one or more interpolated frames of computer graphics are generated based on the application-generated frames. the application-generated and interpolated frames are output in accordance with a goal rate.
20240112308.JOINT NEURAL DENOISING OF SURFACES AND VOLUMES_simplified_abstract_(nvidia corporation)
Inventor(s): Nikolai Till Hofmann of Nuremberg (DE) for nvidia corporation, Jon Niklas Theodor Hasselgren of Bunkeflostrand (SE) for nvidia corporation, Carl Jacob Munkberg of Malmö (SE) for nvidia corporation
IPC Code(s): G06T5/00, G06T5/20, G06T15/06
Abstract: denoising images rendered using monte carlo sampled ray tracing is an important technique for improving the image quality when low sample counts are used. ray traced scenes that include volumes in addition to surface geometry are more complex, and noisy when low sample counts are used to render in real-time. joint neural denoising of surfaces and volumes enables combined volume and surface denoising in real time from low sample count renderings. at least one rendered image is decomposed into volume and surface layers, leveraging spatio-temporal neural denoisers for both the surface and volume components. the individual denoised surface and volume components are composited using learned weights and denoised transmittance. a surface and volume denoiser architecture outperforms current denoisers in scenes containing both surfaces and volumes, and produces temporally stable results at interactive rates.
Inventor(s): Karthick Sekkappan of Pune (IN) for nvidia corporation, Aurobinda Maharana of Chinchwad (IN) for nvidia corporation, Vipul Parashar of Pune (IN) for nvidia corporation
IPC Code(s): G06T7/269, G06V10/25, G06V10/26, H04N19/132, H04N19/139, H04N19/513
Abstract: systems and methods estimate optical flow vectors for occluded pixels between frames of a video sequence. regions of occluded pixels may be identified and a cause of their occlusion may be determined. different estimation techniques may be applied based, at least in part, on the cause of occlusion to provide a lightweight, less resource intensive estimation of optical flow data. optical flow vectors for pixels that are occluded due to movement out of a frame may be estimated using a first technique while optical flow vectors for pixels that are occluded due to foreground movement may be estimated using a second technique.
Inventor(s): Yuzhuo Ren of Sunnyvale CA (US) for nvidia corporation, Dawid Stanislaw Pajak of San Carlos CA (US) for nvidia corporation, Niranjan Avadhanam of Saratoga CA (US) for nvidia corporation
IPC Code(s): G06T11/00, G06T11/60
Abstract: in various examples, color harmonization is applied to images of an environment in a reference light space. for example, different cameras on an ego-object may use independent capturing algorithms to generate processed images of the environment representing a common time slice using different capture configuration parameters. the processed images may be transformed into deprocessed images by inverting one or more stages of image processing to transform the processed images into a reference light space of linear light, and color harmonization may be applied to the deprocessed images in the reference light space. after applying color harmonization, corresponding image processing may be reapplied to the harmonized images using corresponding capture configuration parameters, the resulting processed harmonized images may be stitched into a stitched image, and a visualization of the stitched image may be presented (e.g., on a monitor visible to an occupant or operator of the ego-object).
Inventor(s): Yuzhuo Ren of Sunnyvale CA (US) for nvidia corporation, Dawid Stanislaw Pajak of San Carlos CA (US) for nvidia corporation, Niranjan Avadhanam of Saratoga CA (US) for nvidia corporation, Guangli DAI of Houston TX (US) for nvidia corporation
IPC Code(s): G06V20/56, G06T7/90, G06T15/20, G06V10/10, G06V10/25, G06V10/56
Abstract: in various examples, color statistic(s) from ground projections are used to harmonize color between reference and target frames representing an environment. the reference and target frames may be projected onto a representation of the ground (e.g., a ground plane) of the environment, an overlapping region between the projections may be identified, and the portion of each projection that lands in the overlapping region may be taken as a corresponding ground projection. color statistics (e.g., mean, variance, standard deviation, kurtosis, skew, correlation(s) between color channels) may be computed from the ground projections (or a portion thereof, such as a majority cluster) and used to modify the colors of the target frame to have updated color statistics that match those from the ground projection of the reference frame, thereby harmonizing color across the reference and target frames.
20240114144.FRAME SELECTION FOR STREAMING APPLICATIONS_simplified_abstract_(nvidia corporation)
Inventor(s): Aurobinda Maharana of Chinchwad (IN) for nvidia corporation, Vignesh Ungrapalli of Udupi (IN) for nvidia corporation, Ming-Yu Liu of San Jose CA (US) for nvidia corporation
IPC Code(s): H04N19/137, H04N19/186, H04N19/513
Abstract: systems and methods herein address reference frame selection in video streaming applications using one or more processing units to identify a frame of a sequence of frames as a blurred frame based at least in part on a first variance of motion (vom) of the frame being less than or equal to an adaptive threshold that is based in part on a moving average of variance of motion (maov) determined using one or more reference frames.
20240114162.FRAME SELECTION FOR STREAMING APPLICATIONS_simplified_abstract_(nvidia corporation)
Inventor(s): Aurobinda Maharana of Chinchwad (IN) for nvidia corporation, Arun Mallya of Mountain View CA (US) for nvidia corporation, Ming-Yu Liu of San Jose CA (US) for nvidia corporation, Abhijit Patait of Pune (IN) for nvidia corporation
IPC Code(s): H04N19/50, H04N19/21
Abstract: systems and methods herein address reference frame selection in video streaming applications using one or more processing units to decode a frame of an encoded video stream that uses an inter-frame depicting an object and an intra-frame depicting the object, the intra-frame being included in a set of intra-frames based at least in part on at least one attribute of the object as depicted in the intra-frame being different from the at least one attribute of the object as depicted in other intra-frames of the set of intra-frames.
Inventor(s): Aurobinda Maharana of Chinchwad (IN) for nvidia corporation, Abhijit Patait of Pune (IN) for nvidia corporation
IPC Code(s): H04N19/70, G06T5/50, G06T7/246, G06T7/60, G06V10/25, G06V10/82, G06V40/16, H04N7/15
Abstract: systems and methods relate to facial video encoding and reconstruction, particularly in ultra-low bandwidth settings. in embodiments, a video conferencing or other streaming application uses automatically tracked feature cropping information. a bounding shape size—used to identify the cropped region—varies and is dynamically determined to maintain a proportion for feature reconstruction, such as resizing in the event of a zoom-in on a face (or other feature of interest) or a zoom-out. the tracking scheme may be used to smooth sudden movements, including lateral ones, to generate more natural transitions between frames. tracking and cropping information (e.g., size and position of the cropped region) may be embedded within an encoded bitstream as supplemental enhancement information (“sei”), for eventual decoding by a receiver and for compositing a decoded face at a proper location in the applicable stream.
20240114180.FRAME SELECTION FOR STREAMING APPLICATIONS_simplified_abstract_(nvidia corporation)
Inventor(s): Aurobinda Maharana of Chinchwad (IN) for nvidia corporation, Vignesh Ungrapalli of Udupi (IN) for nvidia corporation, Ming-Yu Liu of San Jose CA (US) for nvidia corporation
IPC Code(s): H04N21/231, H04N19/136, H04N19/154, H04N19/172, H04N19/423, H04N19/70
Abstract: systems and methods herein address reference frame selection in video streaming applications using one or more processing units to replace, during receipt of an encoded video stream, a first set of frames stored in a cache with a second set of frames based at least in part on an indication within the encoded video stream that the second set of frames includes a non-blurred frame (nbf).
- G06V10/764
- G06V10/80
- G06V10/82
- G06N3/084
- G06V10/25
- G06F3/06
- G06F9/30
- G06F21/62
- G06N3/0455
- G06N3/063
- G06F7/483
- G06F17/16
- NVIDIA Corporation
- G01S7/48
- G01S7/481
- G01S17/894
- G01S17/931
- G06V20/58
- Nvidia corporation
- G06F13/42
- G06F1/12
- G06N3/08
- G06N3/045
- G06N20/00
- G06T7/30
- G06T7/50
- G06T7/521
- G06T15/00
- G06V10/44
- G06V20/64
- G06N5/04
- G06F1/3296
- G06N5/02
- G06T1/20
- G06F9/54
- G06T1/60
- H04N7/01
- G06T5/00
- G06T5/20
- G06T15/06
- G06T7/269
- G06V10/26
- H04N19/132
- H04N19/139
- H04N19/513
- G06T11/00
- G06T11/60
- G06V20/56
- G06T7/90
- G06T15/20
- G06V10/10
- G06V10/56
- H04N19/137
- H04N19/186
- H04N19/50
- H04N19/21
- H04N19/70
- G06T5/50
- G06T7/246
- G06T7/60
- G06V40/16
- H04N7/15
- H04N21/231
- H04N19/136
- H04N19/154
- H04N19/172
- H04N19/423
