NVIDIA Corporation patent applications on April 25th, 2024
Patent Applications by NVIDIA Corporation on April 25th, 2024
NVIDIA Corporation: 9 patent applications
NVIDIA Corporation has applied for patents in the areas of G06T13/40 (2), G06N3/08 (2), G06T17/00 (2), G06T15/06 (2), G06T5/50 (2)
With keywords such as: data, image, network, representation, test, processing, generated, vpu, various, and mlm in patent application abstracts.
Patent Applications by NVIDIA Corporation
20240131706.COLLISION-FREE MOTION GENERATION_simplified_abstract_(nvidia corporation)
Inventor(s): Balakumar Sundaralingam of Seattle WA (US) for nvidia corporation, Siva Kumar Sastry Hari of Sunnyvale CA (US) for nvidia corporation, Adam Harper Fishman of Seattle WA (US) for nvidia corporation, Caelan Reed Garrett of Seattle WA (US) for nvidia corporation, Alexander James Millane of Zurich (CH) for nvidia corporation, Elena Oleynikova of Zurich (CH) for nvidia corporation, Ankur Handa of Seattle WA (US) for nvidia corporation, Fabio Tozeto Ramos of Seattle WA (US) for nvidia corporation, Nathan Donald Ratliff of Seattle WA (US) for nvidia corporation, Karl Van Wyk of Issaquah WA (US) for nvidia corporation, Dieter Fox of Seattle WA (US) for nvidia corporation
IPC Code(s): B25J9/16
Abstract: apparatuses, systems, and techniques to perform collision-free motion generation (e.g., to operate a real-world or virtual robot). in at least one embodiment, at least a portion of the collision-free motion generation is performed in parallel.
Inventor(s): Anitha Kalva of San Jose CA (US) for nvidia corporation, Jae Wu of Los Gatos CA (US) for nvidia corporation, Shantanu Sarangi of Saratoga CA (US) for nvidia corporation, Sailendra Chadalavada of Saratoga CA (US) for nvidia corporation, Milind Sonawane of Santa Clara CA (US) for nvidia corporation, Chen Fang of Shanghai (CN) for nvidia corporation, Abilash Nerallapally of Newark CA (US) for nvidia corporation
IPC Code(s): B60W50/02
Abstract: systems and methods are disclosed that relate to testing processing elements of an integrated processing system. a first system test may be performed on a first processing element of an integrated processing system. the first system test may be based at least on accessing a test node associated with the first processing element. the first system test may be accessed using a first local test controller. a second system test may be performed on a second processing element of the integrated processing system. the second system test may be based at least on accessing a second test node associated with the second processing element. the second system test may be accessed using a second local test controller.
Inventor(s): Ahmad Itani of San Jose CA (US) for nvidia corporation, Yen-Te Shih of Zhubei City (TW) for nvidia corporation, Jagadeesh Sankaran of Dublin CA (US) for nvidia corporation, Ravi P Singh of Austin TX (US) for nvidia corporation, Ching-Yu Hung of Pleasanton CA (US) for nvidia corporation
IPC Code(s): G06F9/30, G06F13/28, G06F15/80
Abstract: in various examples, a vpu and associated components may be optimized to improve vpu performance and throughput. for example, the vpu may include a min/max collector, automatic store predication functionality, a simd data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. in addition, decoupled accelerators may be used to offload vpu processing tasks to increase throughput and performance, and a hardware sequencer may be included in a dma system to reduce programming complexity of the vpu and the dma system. the dma and vpu may execute a vpu configuration mode that allows the vpu and dma to operate without a processing controller for performing dynamic region based data movement operations.
Inventor(s): Yilin Yang of Santa Clara CA (US) for nvidia corporation, Bala Siva Sashank Jujjavarapu of Sunnyvale CA (US) for nvidia corporation, Pekka Janis of Uusimaa (FI) for nvidia corporation, Zhaoting Ye of Santa Clara CA (US) for nvidia corporation, Sangmin Oh of San Jose CA (US) for nvidia corporation, Minwoo Park of Saratoga CA (US) for nvidia corporation, Daniel Herrera Castro of Uusimaa (FI) for nvidia corporation, Tommi Koivisto of Uusimaa (FI) for nvidia corporation, David Nister of Bellevue WA (US) for nvidia corporation
IPC Code(s): G06N3/08, B60W30/14, B60W60/00, G06F18/214, G06V10/762, G06V20/56
Abstract: in various examples, a deep neural network (dnn) is trained to accurately predict, in deployment, distances to objects and obstacles using image data alone. the dnn may be trained with ground truth data that is generated and encoded using sensor data from any number of depth predicting sensors, such as, without limitation, radar sensors, lidar sensors, and/or sonar sensors. camera adaptation algorithms may be used in various embodiments to adapt the dnn for use with image data generated by cameras with varying parameters—such as varying fields of view. in some examples, a post-processing safety bounds operation may be executed on the predictions of the dnn to ensure that the predictions fall within a safety-permissible range.
Inventor(s): Steen KRISTENSEN of Santa Clara CA (US) for nvidia corporation, Simon KIEFHABER of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T3/40, G06F3/01
Abstract: in various examples, a stitched image may be generated from overlapping image frames using a dynamic seam placement that depends on scene content and/or other factors. since an optimized seam placement may jump from a previous location from time slice to time slice, one or more constraints may be applied to limit the movement of dynamically placed seams such that any given seam moves gradually over time, limiting potential discontinuities in a visualization of the stitched image on a display. eye tracking may be used to detect a saccade of a monitored person and/or detect that the monitored person is not looking at the display, and one or more of the constraints used to limit the movement of dynamically placed seams may be relaxed or lifted when the monitored person is experiencing a saccade and/or is looking away from the display.
Inventor(s): Haotian Zhang of Stanford CA (US) for nvidia corporation, Ye Yuan of Santa Clara CA (US) for nvidia corporation, Jason Peng of Vancouver (CA) for nvidia corporation, Viktor Makoviichuk of Santa Clara CA (US) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation
IPC Code(s): G06T13/40, G06T7/70, G06T17/00, G06V40/20
Abstract: in various examples, artificial intelligence (ai) agents can be generated to synthesize more natural motion by simulated actors in various visualizations (such as video games or simulations). ai agents may employ one or more machine learning models and techniques, such as reinforcement learning, to enable synthesis of motion with enhanced realism. the ai agent can be trained based on widely-available broadcast video data, without the need for more costly and limited motion capture data. to account for the lower quality of such video data, various techniques can be employed, such as taking into account the motion of joints, and applying physics-based constraints on the actors, resulting in higher quality, more lifelike motion.
Inventor(s): Koki Nagano of Playa Vista CA (US) for nvidia corporation, Eric Ryan Wong Chan of Alameda CA (US) for nvidia corporation, Tero Tapani Karras of Helsinki (FI) for nvidia corporation, Shalini De Mello of San Francisco CA (US) for nvidia corporation, Miika Samuli Aittala of Helsinki (FI) for nvidia corporation, Matthew Aaron Wong Chan of Los Altos CA (US) for nvidia corporation
IPC Code(s): G06T15/06, G06T5/00, G06T5/50, G06V10/44, G06V10/771
Abstract: a method and system for performing novel image synthesis using generative networks are provided. the encoder-based model is trained to infer a 3d representation of an input image. a feature image is then generated using volume rendering techniques in accordance with the 3d representation. the feature image is then concatenated with a noisy image and processed by a denoiser network to predict an output image from a novel viewpoint that is consistent with the input image. the denoiser network can be a modified noise conditional score network (ncsn). in some embodiments, multiple input images or keyframes can be provided as input, and a different 3d representation is generated for each input image. the feature image is then generated, during volume rendering, by sampling each of the 3d representations and applying a mean-pooling operation to generate an aggregate feature image.
Inventor(s): Vladimir Bataev of Yerevan (AM) for nvidia corporation, Roman Korostik of Yerevan (AM) for nvidia corporation, Evgenii Shabalin of Moskva (RU) for nvidia corporation, Vitaly Sergeyevich Lavrukhin of Campbell CA (US) for nvidia corporation, Boris Ginsburg of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G10L15/16, G10L15/065
Abstract: in various examples, first textual data may be applied to a first mlm to generate an intermediate speech representation (e.g., a frequency-domain representation), the intermediate audio representation and a second mlm may be used to generate output data indicating second textual data, and parameters of the second mlm may be updated using the output data and ground truth data associated with the first textual data. the first mlm may include a trained text-to-speech (tts) model and the second mlm may include an automatic speech recognition (asr) model. a generator from a generative adversarial networks may be used to enhance an initial intermediate audio representation generated using the first mlm and the enhanced intermediate audio representation may be provided to the second mlm. the generator may include generator blocks that receive the initial intermediate audio representation to sequentially generate the enhanced intermediate audio representation.
20240137410.MULTICAST-REDUCTION ASSISTED BY NETWORK DEVICES_simplified_abstract_(nvidia corporation)
Inventor(s): Glenn Dearth of Groton MA (US) for nvidia corporation, Mark Hummel of Franklin MA (US) for nvidia corporation, Nan Jiang of Sudbury MA (US) for nvidia corporation, Gregory Thorson of Eau Claire WI (US) for nvidia corporation
IPC Code(s): H04L67/1008, H04L47/70, H04L47/80, H04L67/1014
Abstract: systems and techniques for performing multicast-reduction operations. in at least one embodiment, a network device receives first network data associated with a multicast operation to be collectively performed by at least a plurality of endpoints. the network device reserves resources to process second network data to be received from the endpoints, and sends the first network data to a plurality of additional network devices. the network device receives the second network data, and processes the second network data using the reserved resources.
