NANYA TECHNOLOGY CORPORATION patent applications on October 17th, 2024
Patent Applications by NANYA TECHNOLOGY CORPORATION on October 17th, 2024
NANYA TECHNOLOGY CORPORATION: 19 patent applications
NANYA TECHNOLOGY CORPORATION has applied for patents in the areas of H01L21/768 (10), H01L23/528 (8), H01L23/522 (5), H01L21/762 (3), H10B12/00 (3) H01L23/5283 (4), H01L21/76224 (2), H01L21/76802 (2), H01L23/528 (2), H10B12/33 (2)
With keywords such as: layer, semiconductor, dielectric, structure, surface, conductive, pillars, substrate, top, and disposed in patent application abstracts.
Patent Applications by NANYA TECHNOLOGY CORPORATION
Inventor(s): Tien Yu CHEN of New Taipei City (TW) for nanya technology corporation
IPC Code(s): G01R1/44, G01R31/28
CPC Code(s): G01R1/44
Abstract: a preheating control system comprising a testing device and a processor is provided in present disclosure. the testing device is configured to perform a wafer testing on a wafer lot and perform a device preheating on the testing device. the processor is coupled to the testing device and comprises a timing circuit and a controlling circuit. the timing circuit is configured to calculate a lot-changing time, wherein the lot-changing time is a difference between a time corresponding to removal of a previous wafer lot from the testing device and a time corresponding to insertion of the wafer lot into the testing device. the controlling circuit is configured to control the testing device to perform the wafer testing, and configured to control the testing device to perform the device preheating according to the lot-changing time and a standard lot-changing time.
Inventor(s): KUO-CHUNG HSU of KAOHSIUNG CITY (TW) for nanya technology corporation, EN-JUI LI of NEW TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L21/762, H10B10/00, H10B12/00, H10B20/25
CPC Code(s): H01L21/76224
Abstract: a semiconductor device and a method for manufacturing the same are provided. the semiconductor device includes a substrate and a first isolation structure. the substrate has a cell region and a peripheral region. the first isolation structure is disposed in the cell region of the substrate. the first isolation structure includes a first dielectric layer and a second dielectric layer. the second dielectric layer is spaced apart from the substrate by the first dielectric layer. the second dielectric layer is doped with an impurity.
Inventor(s): KUO-CHUNG HSU of KAOHSIUNG CITY (TW) for nanya technology corporation, EN-JUI LI of NEW TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L21/762
CPC Code(s): H01L21/76224
Abstract: a semiconductor device and a method for manufacturing the same are provided. the semiconductor device includes a substrate having an active region and a shallow trench isolation (sti) adjacent to the active region of the substrate. the sti includes a charge trapping layer and a liner disposed between the charge trapping layer and the active region of the substrate, wherein the charge trapping layer is doped with an impurity.
Inventor(s): CHEN-TSUNG LIAO of NEW TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L21/762, H01L21/3065, H01L21/311, H01L29/66
CPC Code(s): H01L21/76232
Abstract: the present disclosure provides a method of manufacturing a semiconductor structure having fins. the method includes providing a semiconductor substrate including a plurality of initial fin structures. the method also includes forming an isolation material covering the plurality of initial fin structures. the method further includes performing an anisotropic etching operation on the isolation material and the plurality of initial fin structures to form a plurality of fins. the method also includes performing an isotropic etching operation on the isolation material to form an isolation structure surrounding the plurality of fins.
Inventor(s): YING-CHENG CHUANG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L21/768, H01L23/528
CPC Code(s): H01L21/76802
Abstract: the present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. a substrate is provided, wherein the substrate includes a plurality of pillars, and a top surface of each of the plurality of pillars is a substantially planar surface. a first oxide layer is formed over the substrate conformal to the pillars, wherein the formation of the first oxide layer includes oxidizing top corners of the pillars, thereby causing the top surface of each of the plurality of pillars to become a convex surface. a first dielectric layer is formed among the pillars, wherein the first oxide layer above the plurality of pillars is partially exposed through the first dielectric layer. a planarization is performed on the pillars to partially or entirely remove the convex surface.
Inventor(s): YING-CHENG CHUANG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L21/768, H01L23/528
CPC Code(s): H01L21/76802
Abstract: the present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. a substrate is provided, wherein the substrate includes a plurality of pillars, and a top surface of each of the plurality of pillars is a substantially planar surface. a first oxide layer is formed over the substrate conformal to the pillars, wherein the formation of the first oxide layer includes oxidizing top corners of the pillars, thereby causing the top surface of each of the plurality of pillars to become a convex surface. a first dielectric layer is formed among the pillars, wherein the first oxide layer above the plurality of pillars is partially exposed through the first dielectric layer. a planarization is performed on the pillars to partially or entirely remove the convex surface.
Inventor(s): PIN-JHU LI of NEW TAIPEI CITY (TW) for nanya technology corporation, SHIH-FAN KUAN of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/522, H01L21/768
CPC Code(s): H01L23/5226
Abstract: a conductive structure and a capacitor structure and a method of manufacturing a conductive structure are provided. the conductive structure includes a first support layer, a second support layer, a first conductive via, a third support layer and a second conductive via. the second support layer is disposed over the first support layer. the first conductive via is disposed between the first support layer and the second support layer. the third support layer is disposed over the second support layer. the second conductive via is disposed between the second support layer and the third support layer, and electrically connected to the first conductive via. a lateral surface of the first conductive via is discontinuous with a lateral surface of the second conductive via.
Inventor(s): YING-CHENG CHUANG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/528, H01L21/768
CPC Code(s): H01L23/528
Abstract: the present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. the semiconductor structure includes a substrate, a residual nitrogen, an oxide layer, a plurality of first contacts, and a plurality of second contacts. the substrate includes a plurality of pillars in an array region of the substrate, wherein a top surface of each of the plurality of pillars is a substantially planar surface. the residual nitrogen is partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars. the oxide layer surrounds each of the pillars. the plurality of first contacts extends from the top surfaces of the pillars into the pillars. the plurality of second contacts extends from the top surface of the first dielectric layer into the first dielectric layer.
Inventor(s): YING-CHENG CHUANG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/528, H01L21/768
CPC Code(s): H01L23/528
Abstract: the present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. the semiconductor structure includes a substrate, a residual nitrogen, a first dielectric layer, a plurality of first contacts, and a plurality of second contacts. the substrate includes a plurality of pillars in an array region of the substrate, wherein a top surface of each of the plurality of pillars is a substantially planar surface. the residual nitrogen is partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars. the first dielectric layer surrounds each of the pillars. the plurality of first contacts extends from the top surfaces of the pillars into the pillars. the plurality of second contacts extends from the top surface of the first dielectric layer into the first dielectric layer.
Inventor(s): CHIN-LING HUANG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/532
CPC Code(s): H01L23/5283
Abstract: a semiconductor device includes a first insulating layer inwardly positioned in a substrate and including a u-shaped cross-sectional profile; a first assisting layer conformally positioned on the first insulating layer and the substrate; a first filler layer positioned on the first assisting layer; and a capping dielectric layer positioned on the substrate and covering the first assisting layer and the first filler layer. a top surface of the first insulating layer is at a vertical level lower than a top surface of the substrate. the first assisting layer includes a first step portion and a second step portion, the first step portion of the first assisting layer is adjacent to the top surface of the first insulating layer, and the second step portion of the first assisting layer is adjacent to the top surface of the substrate.
Inventor(s): ZIH-HONG YANG of NEW TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/522
CPC Code(s): H01L23/5283
Abstract: an interconnection structure and a method of manufacturing an interconnection structure are provided. the interconnection structure includes a first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first conductive layer disposed in the first dielectric layer. the interconnection structure also includes a conductive via electrically connected with the first conductive layer and extending through the first dielectric layer and the second dielectric layer. the conductive via has a first lateral surface surrounded by the first dielectric layer and a second lateral surface surrounded by the second dielectric layer. the first lateral surface and the second lateral surface have different slopes.
Inventor(s): CHIN-LING HUANG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/532
CPC Code(s): H01L23/5283
Abstract: a semiconductor device includes a first insulating layer inwardly positioned in a substrate and including a u-shaped cross-sectional profile; a first assisting layer conformally positioned on the first insulating layer and the substrate; a first filler layer positioned on the first assisting layer; and a capping dielectric layer positioned on the substrate and covering the first assisting layer and the first filler layer. a top surface of the first insulating layer is at a vertical level lower than a top surface of the substrate. the first assisting layer includes a first step portion and a second step portion, the first step portion of the first assisting layer is adjacent to the top surface of the first insulating layer, and the second step portion of the first assisting layer is adjacent to the top surface of the substrate.
Inventor(s): ZIH-HONG YANG of NEW TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/522
CPC Code(s): H01L23/5283
Abstract: an interconnection structure and a method of manufacturing an interconnection structure are provided. the interconnection structure includes a first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first conductive layer disposed in the first dielectric layer. the interconnection structure also includes a conductive via electrically connected with the first conductive layer and extending through the first dielectric layer and the second dielectric layer. the conductive via has a first lateral surface surrounded by the first dielectric layer and a second lateral surface surrounded by the second dielectric layer. the first lateral surface and the second lateral surface have different slopes.
Inventor(s): Chun-Wei WANG of New Taipei City (TW) for nanya technology corporation, Jen-I LAI of New Taipei City (TW) for nanya technology corporation, Rou-Wei WANG of New Taipei City (TW) for nanya technology corporation
IPC Code(s): H01L23/532, H01L21/311, H01L21/768, H01L23/522
CPC Code(s): H01L23/53238
Abstract: a method of manufacturing a semiconductor structure includes a number of operations. a first oxide layer is provided on a semiconductor integrated circuit. a conductive layer of the semiconductor integrated circuit is exposed from a top surface of the first oxide layer. an etch stop layer is formed on the top surface of the first oxide layer. a second oxide layer is formed on the etch stop layer. a through via is formed extending through the second oxide layer and the etch stop layer to expose the conductive layer. acid is provided on the conductive layer to form a protective layer on the conductive layer. the protective layer includes a compound of the acid and material of the conductive layer. a fence of the second oxide layer at an edge on the through via is removed at the through via by a hydrofluoric acid etching.
Inventor(s): PIN-JHU LI of NEW TAIPEI CITY (TW) for nanya technology corporation, SHIH-FAN KUAN of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L21/02, H01L23/522
CPC Code(s): H01L28/55
Abstract: a capacitor structure and a method of manufacturing a capacitor structure are provided. the capacitor structure includes a conductive via, an intermediate dielectric layer and a top electrode. the conductive via includes a neck portion located near a middle portion thereof. the intermediate dielectric layer is disposed on the conductive via. the top electrode is disposed on the intermediate dielectric layer.
Inventor(s): YAO-HSIUNG KUNG of TAOYUAN CITY (TW) for nanya technology corporation, YU-LI WU of NEW TAIPEI CITY (TW) for nanya technology corporation, SHAO-EN YEH of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/33
Abstract: the present disclosure provides a semiconductor structure and a method of manufacturing a semiconductor structure. the semiconductor structure includes: a data storage unit in a first dielectric layer; a word line disposed over the data storage unit; an array of conductive pads disposed over the word line; a hard mask layer disposed over the array of conductive pads; and a second dielectric layer laterally surrounding the hard mask layer and the array of conductive pads, the second dielectric layer is leveled with the hard mask layer.
Inventor(s): YAO-HSIUNG KUNG of TAOYUAN CITY (TW) for nanya technology corporation, YU-LI WU of NEW TAIPEI CITY (TW) for nanya technology corporation, SHAO-EN YEH of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/33
Abstract: the present disclosure provides a semiconductor structure and a method of manufacturing a semiconductor structure. the semiconductor structure includes: a data storage unit in a first dielectric layer; a word line disposed over the data storage unit; an array of conductive pads disposed over the word line; a hard mask layer disposed over the array of conductive pads; and a second dielectric layer laterally surrounding the hard mask layer and the array of conductive pads, the second dielectric layer is leveled with the hard mask layer.
20240349518. SEMICONDUCTOR DEVICE STRUCTURE_simplified_abstract_(nanya technology corporation)
Inventor(s): SHING-YIH SHIH of NEW TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H10B80/00
CPC Code(s): H10B80/00
Abstract: a semiconductor device structure and method of manufacturing the same are provided. the semiconductor device structure includes an interposer and a first electronic component. the interposer includes a first semiconductor die and a second semiconductor die. the first semiconductor die includes a first cache memory and a first memory control circuit. the second semiconductor die includes a second cache memory and a second memory control circuit. the first electronic component is disposed on the interposer and in communication with the first semiconductor die and the second semiconductor die.
20240349519. SEMICONDUCTOR DEVICE STRUCTURE_simplified_abstract_(nanya technology corporation)
Inventor(s): SHING-YIH SHIH of NEW TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H10B80/00
CPC Code(s): H10B80/00
Abstract: a semiconductor device structure and method of manufacturing the same are provided. the semiconductor device structure includes an interposer and a first electronic component. the interposer includes a first semiconductor die and a second semiconductor die. the first semiconductor die includes a first cache memory and a first memory control circuit. the second semiconductor die includes a second cache memory and a second memory control circuit. the first electronic component is disposed on the interposer and in communication with the first semiconductor die and the second semiconductor die.
NANYA TECHNOLOGY CORPORATION patent applications on October 17th, 2024
- NANYA TECHNOLOGY CORPORATION
- G01R1/44
- G01R31/28
- CPC G01R1/44
- Nanya technology corporation
- H01L21/762
- H10B10/00
- H10B12/00
- H10B20/25
- CPC H01L21/76224
- H01L21/3065
- H01L21/311
- H01L29/66
- CPC H01L21/76232
- H01L21/768
- H01L23/528
- CPC H01L21/76802
- H01L23/522
- CPC H01L23/5226
- CPC H01L23/528
- H01L23/532
- CPC H01L23/5283
- CPC H01L23/53238
- H01L21/02
- CPC H01L28/55
- CPC H10B12/33
- H10B80/00
- CPC H10B80/00
