Micron technology, inc. (20240315001). Memory Circuitry And Methods Used In Forming Memory Circuitry simplified abstract
Contents
Memory Circuitry And Methods Used In Forming Memory Circuitry
Organization Name
Inventor(s)
Kamal M. Karda of Boise ID (US)
David Daycock of Boise ID (US)
Memory Circuitry And Methods Used In Forming Memory Circuitry - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240315001 titled 'Memory Circuitry And Methods Used In Forming Memory Circuitry
The memory circuitry described in the patent application consists of vertically-alternating tiers of insulative material and memory cells, each comprising a transistor with a first source/drain region, a second source/drain region, and a channel region between them, along with a gate proximate to the channel region. Capacitors in the circuitry have a first and second electrode with a capacitor insulator between them, where the first electrode is directly connected to the first source/drain region, and the second electrode of multiple capacitors are connected to each other. Digitlines run vertically through the tiers, with the second source/drain regions of transistors in different memory-cell tiers directly connected to individual digitlines. Wordlines in each memory-cell tier contain the gates of multiple transistors, with wider wordlines in lower tiers compared to higher tiers.
- Memory circuitry with vertically-alternating tiers of insulative material and memory cells
- Transistors in memory cells with first and second source/drain regions and a channel region
- Capacitors with first and second electrodes connected to source/drain regions and each other
- Digitlines running vertically through the tiers, connecting source/drain regions to individual digitlines
- Wordlines in memory-cell tiers containing gates of multiple transistors, with varying widths in different tiers
Potential Applications: - High-density memory storage devices - Advanced computing systems - Data processing applications
Problems Solved: - Increased memory storage capacity - Enhanced data processing speed - Improved efficiency in computing systems
Benefits: - Higher performance in memory-intensive tasks - Greater data storage capabilities - Enhanced overall system efficiency
Commercial Applications: Title: "Innovative Memory Circuitry for High-Performance Computing Systems" This technology could be utilized in: - Data centers - Supercomputers - High-speed servers
Questions about Memory Circuitry: 1. How does the vertically-alternating tier design improve memory circuitry performance? 2. What are the advantages of directly connecting the second electrode of capacitors in the memory cells?
Frequently Updated Research: Stay updated on the latest advancements in memory circuitry design and applications to leverage the full potential of this innovative technology.
Original Abstract Submitted
memory circuitry comprises vertically-alternating tiers of insulative material and memory cells. the memory cells individually comprising a transistor comprise a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. a gate is operatively-proximate the channel region. a capacitor comprises a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes. the first capacitor electrode is directly electrically coupled to the first source/drain region. the second capacitor electrode of multiple of the capacitors is directly electrically coupled with one another. digitlines extend elevationally through the vertically-alternating tiers. individual of the second source/drain regions of individual of the transistors that are in different memory-cell tiers are directly electrically coupled to individual of the digitlines. a wordline is in individual of the memory-cell tiers that comprises the gate of multiple of the individual transistors in the individual memory-cell tiers. the wordline in a lower of the memory-cell tiers has a greater minimum width than a minimum width of the wordline in a higher of the memory-cell tiers that is directly above the lower memory-cell tier. methods are also disclosed.
