Micron technology, inc. (20240265989). TRACKING AND REFRESHING STATE METRICS IN MEMORY SUB-SYSTEMS simplified abstract
Contents
TRACKING AND REFRESHING STATE METRICS IN MEMORY SUB-SYSTEMS
Organization Name
Inventor(s)
Michael Sheperek of Longmont CO (US)
Bruce A. Liikanen of Berthoud CO (US)
Steven Michael Kientz of Westminster CO (US)
TRACKING AND REFRESHING STATE METRICS IN MEMORY SUB-SYSTEMS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240265989 titled 'TRACKING AND REFRESHING STATE METRICS IN MEMORY SUB-SYSTEMS
The abstract of the patent application describes a system that includes a memory device and a processing device. The processing device, in response to detecting a triggering event, selects a family of memory blocks associated with a set of bins, each bin having multiple read voltage offsets for read operations. Calibration operations are performed to determine data state metric values for the read voltage offsets of different bins. Based on the determined data state metrics, a target bin is identified and the selected family is associated with the target bin.
- Memory device and processing device work together in the system.
- Triggering event prompts the selection of a family of memory blocks.
- Each bin in the selected family has various read voltage offsets for read operations.
- Calibration operations determine data state metric values for the read voltage offsets.
- Target bin is identified based on the data state metrics and associated with the selected family.
Potential Applications: - Data storage systems - Semiconductor manufacturing - Memory management in electronic devices
Problems Solved: - Efficient selection and management of memory blocks - Optimization of read voltage offsets for improved performance
Benefits: - Enhanced data storage efficiency - Improved read operation performance - Better memory management in electronic devices
Commercial Applications: Title: Advanced Memory Management System for Electronic Devices This technology can be utilized in various electronic devices such as smartphones, laptops, and servers to optimize memory usage and improve overall performance. It can also be integrated into data storage systems for enhanced efficiency and reliability.
Questions about the technology: 1. How does the system determine the target bin based on the data state metrics? 2. What are the potential implications of using different read voltage offsets for memory blocks in electronic devices?
Original Abstract Submitted
disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to detecting a triggering event, selecting a family of memory blocks of the memory device, the selected family being associated with a set of bins, each bin associated with a plurality of read voltage offsets to be applied to base read voltages during read operations. the operations performed by the processing device further include calibration operations to determine data state metric values characterizing application of read voltage offsets of various bins. the operations performed by the processing device further include identifying, based on the determined data state metrics, a target bin and associating the selected family with the target bin.
