Micron technology, inc. (20240265979). Selective and Dynamic Deployment of Error Correction Code Techniques in Integrated Circuit Memory Devices simplified abstract
Selective and Dynamic Deployment of Error Correction Code Techniques in Integrated Circuit Memory Devices
Organization Name
Inventor(s)
James Fitzpatrick of Laguna Niguel CA (US)
Phong Sy Nguyen of Livermore CA (US)
Dung Viet Nguyen of San Jose CA (US)
Sivagnanam Parthasarathy of Carlsbad CA (US)
Selective and Dynamic Deployment of Error Correction Code Techniques in Integrated Circuit Memory Devices - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240265979 titled 'Selective and Dynamic Deployment of Error Correction Code Techniques in Integrated Circuit Memory Devices
Simplified Explanation:
The memory system described in the patent application can adjust the amount of redundant information stored in memory cells based on the bit error rate of a wordline on an integrated circuit die.
- The system stores first data items as independent first codewords in a portion of the memory cells when the bit error rate is above a threshold.
- It generates second data items as redundant information from the first codewords and stores them in another portion of the memory cells.
- When the bit error rate is below the threshold, third data items are stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.
Key Features and Innovation:
- Dynamic adjustment of redundant information based on bit error rate
- Storage of data items as independent codewords and redundant information
- Utilization of error correction code techniques for data storage
Potential Applications:
- Integrated circuits
- Memory systems
- Error correction in data storage
Problems Solved:
- Addressing bit errors in memory cells
- Optimizing storage efficiency
- Enhancing data reliability
Benefits:
- Improved data integrity
- Efficient memory utilization
- Enhanced error correction capabilities
Commercial Applications:
The technology can be utilized in various industries such as telecommunications, data centers, and consumer electronics for improving data storage reliability and efficiency.
Questions about Memory System Innovation: 1. How does the memory system dynamically adjust the amount of redundant information based on the bit error rate? 2. What are the potential implications of this innovation in the field of integrated circuits and data storage systems?
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Original Abstract Submitted
a memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. for example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. if the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.
