Micron technology, inc. (20240258273). SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE STACKS OF DIFFERENT SEMICONDUCTOR DIES simplified abstract
Contents
SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE STACKS OF DIFFERENT SEMICONDUCTOR DIES
Organization Name
Inventor(s)
Blaine J. Thurgood of Nampa ID (US)
SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE STACKS OF DIFFERENT SEMICONDUCTOR DIES - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240258273 titled 'SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE STACKS OF DIFFERENT SEMICONDUCTOR DIES
Simplified Explanation: The patent application describes a semiconductor device assembly with multiple stacks of semiconductor dies of different sizes encapsulated on a package substrate.
- The assembly includes a package substrate, a first stack of semiconductor dies with one set of dimensions, and a second stack with a different set of dimensions.
- An encapsulant covers the substrate, first stack, and second stack.
- The combined area of the first and second stacks can be a significant portion of the substrate area.
Key Features and Innovation:
- Semiconductor device assembly with multiple stacks of dies.
- Different planform dimensions for each stack.
- Encapsulation of the substrate and stacks.
Potential Applications:
- Electronics manufacturing
- Semiconductor industry
- Integrated circuit production
Problems Solved:
- Efficient use of space on the substrate
- Enhanced functionality in a compact design
Benefits:
- Increased component density
- Improved performance
- Cost-effective manufacturing
Commercial Applications:
- High-density electronic devices
- Compact consumer electronics
- Advanced computing systems
Questions about Semiconductor Device Assembly: 1. How does the encapsulation process impact the overall durability of the assembly? 2. What are the potential challenges in integrating multiple stacks of dies on a single substrate?
Frequently Updated Research: Ongoing research in semiconductor packaging technologies and materials could further enhance the efficiency and performance of such device assemblies.
Original Abstract Submitted
a semiconductor device assembly is provided. the assembly comprises a package substrate, a first stack of semiconductor dies having a first set of planform dimensions disposed over a first location on the substrate, a second stack of semiconductor dies having a second set of planform dimensions different from the first set disposed over a second location on the substrate, and an encapsulant at least partially encapsulating the substrate, the first stack and the second stack. the first stack of semiconductor dies has a first planform area, the second stack of semiconductor dies has a second planform area, and a sum of the first and second planform areas can be at least 50%, 67%, 75%, or even more of an area of the package substrate.
