Micron technology, inc. (20240256145). SCAN FRAGMENTATION IN MEMORY DEVICES simplified abstract
Contents
SCAN FRAGMENTATION IN MEMORY DEVICES
Organization Name
Inventor(s)
Vamsi Pavan Rayaprolu of Santa Clara CA (US)
Christopher M. Smitchger of Boise ID (US)
Saeed Sharifi Tehrani of San Diego CA (US)
SCAN FRAGMENTATION IN MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240256145 titled 'SCAN FRAGMENTATION IN MEMORY DEVICES
The memory system described in the abstract consists of a memory device and a processing device that work together. The processing device is responsible for identifying mandatory scan wordlines and remaining wordlines of the memory device, as well as performing multiple scan iterations on various pages of the memory device.
- The processing device identifies mandatory scan wordlines and remaining wordlines of the memory device.
- It conducts multiple scan iterations on different pages of the memory device.
- Each scan iteration involves identifying scheduled scan wordlines and scanning a subset of pages addressable by these wordlines.
- The combination of pages addressable by scheduled scan wordlines and mandatory wordlines makes up the total pages of the memory device.
Potential Applications: - This technology can be applied in high-speed memory systems. - It can enhance memory testing processes in semiconductor manufacturing.
Problems Solved: - Efficient identification and scanning of wordlines in memory devices. - Streamlining the testing process for memory systems.
Benefits: - Improved memory testing accuracy. - Enhanced efficiency in memory device operations.
Commercial Applications: Title: Advanced Memory Testing System for Semiconductor Manufacturing This technology can be utilized in semiconductor manufacturing facilities to optimize memory testing processes, leading to increased productivity and reduced testing time.
Prior Art: Researchers can explore existing patents related to memory testing systems and semiconductor manufacturing processes to understand the evolution of this technology.
Frequently Updated Research: Researchers in the field of semiconductor testing and memory systems continuously work on enhancing memory testing methodologies and improving the efficiency of memory devices.
Questions about the technology: 1. How does this memory system improve the testing process compared to traditional methods? 2. What are the potential cost savings associated with implementing this technology in semiconductor manufacturing?
Original Abstract Submitted
a memory system includes a memory device and a processing device, operatively coupled to the memory device. the processing device performs operations comprising: identifying one or more mandatory scan wordlines of the memory device and one or more remaining wordlines of the memory device; performing a plurality of scan iterations with respect to a plurality of pages of the memory device, such that performing each scan iteration comprises: identifying, among the remaining wordlines, one or more scheduled scan wordlines of the memory device, scanning a subset of pages of the memory device that are addressable by the mandatory scan wordlines and the scheduled scan wordlines; wherein a combination of a first plurality of pages addressable by the scheduled scan wordlines selected by the plurality of scan iterations and a second plurality of pages addressable by the mandatory wordlines comprises the plurality of pages of the memory device.
