Micron technology, inc. (20240232013). ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC simplified abstract

ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC

Organization Name

micron technology, inc.

Inventor(s)

Kishore Kumar Muchherla of San Jose CA (US)

Niccolo’ Righetti of Boise ID (US)

Sivagnanam Parthasarathy of Carlsbad CA (US)

Mustafa N. Kaynak of San Diego CA (US)

Mark A. Helm of Santa Cruz CA (US)

James Fitzpatrick of Laguna Niguel CA (US)

Ugo Russo of Boise ID (US)

ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240232013 titled 'ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC

The method described in the patent application involves determining a memory endurance state metric for a segment of a memory device in a memory sub-system, using a processing device. Based on this metric, a target value of a code rate is determined, and the code rate of the memory device is adjusted accordingly. The code rate represents the ratio of memory units designated for storing host-originated data to the total number of memory units designated for storing both data and error correction metadata.

• The method involves determining a memory endurance state metric for a memory device segment.
• Based on the metric, a target value of a code rate is calculated.
• The code rate of the memory device is adjusted according to the target value.
• The code rate reflects the ratio of memory units for storing data to the total memory units for data and error correction metadata.

Potential Applications: - This technology can be applied in memory systems to optimize performance and endurance. - It can be used in data centers to enhance data storage efficiency. - Manufacturers of memory devices can implement this method to improve the reliability of their products.

Problems Solved: - Addresses the need for efficient memory management in memory sub-systems. - Optimizes the code rate of memory devices based on their endurance state metrics. - Enhances the overall performance and reliability of memory systems.

Benefits: - Improved memory device performance and longevity. - Enhanced data storage efficiency and reliability. - Optimal utilization of memory units for storing data and error correction metadata.

Commercial Applications: Title: Memory Code Rate Optimization Technology for Enhanced Data Storage This technology can be utilized in various commercial applications such as: - Data centers - Cloud storage providers - Memory device manufacturers

Questions about Memory Code Rate Optimization Technology: 1. How does this technology impact the overall performance of memory devices?

  - This technology significantly improves the performance and reliability of memory devices by optimizing the code rate based on memory endurance state metrics.

2. What are the potential implications of implementing this technology in data centers?

  - Implementing this technology in data centers can lead to enhanced data storage efficiency and improved overall system reliability.

Original Abstract Submitted

a method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.